JPS62233984A - Recorder - Google Patents

Abstract

PURPOSE:To prevent a video signal to be recorded from being concealed by a data signal by displaying only the video signal without displaying the data signal recorded together with the video signal on a monitor. CONSTITUTION:When the ID switch 73 of the data signal is turned on, a CPU 40 fetches a reproducing ID from a RAM27 in the case of a reproducing mode and an ID display mode, controls a character generator 84 and outputs the reproducing ID from the character generator 84 as a character pattern. Every time when the ID switch 73 is turned on, the reproducing ID is superimposed on the video signal and the ID display mode to be monitored and an ID non- display mode in which the reproducing ID is not outputted are repeated. In case of a recording mode, an ID setting mode in which all the set IDs are displayed, an ID character display mode in which only the character of ID is displayed and a mode in which the ID is not displayed on the monitor are changed over every time when the ID switch 73 is turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a recording/reproducing apparatus for video signals, and particularly to a recording/reproducing apparatus for recording a plurality of data signals together with a video signal on a recording medium.

<Prior Art> A conventional device for recording and reproducing a plurality of data signals together with a video signal on a recording medium has a method of superimposing the video signal to be recorded and the data signal when recording the data signal and the video signal. The data signal and the video signal are recorded on the recording medium in response to a trigger signal for recording in such a state.

<Problems to be Solved by the Invention> However, in the conventional apparatus, when the number of types of the plurality of data signals increases, the video signal to be recorded and the data signal are superimposed and the data signal is superimposed and checked on a monitor. A problem arises in that the video signal to be recorded is obscured over a wide area by the signal, which is extremely troublesome.

The present invention aims to solve such problems.

<Means for Solving the Problems> In order to solve the above-mentioned problems, the present invention provides a recording device that records both a video signal and a data signal related to the video signal on a recording medium, in which the data signal is converted into a video signal. The present invention is characterized by comprising a first means for superimposing the data signal on the video signal and outputting it to the monitor, and a second means for outputting the data signal on the monitor without superimposing the data signal on the video signal.

<Function> In the above configuration, the data signal is superimposed on the video signal and output to the monitor by the first means, and the data signal is not superimposed on the video signal and only the video signal is output to the monitor by the second means. .

3 (4 pages missing) <Example> The present invention will be described in detail below with reference to the drawings. In the embodiment of the present invention described below, a disk-shaped recording medium, specifically a disk-shaped magnetic sheet A recording and reproducing apparatus for recording a still image video signal or reproducing a recorded still image video signal will be described.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a magnetic sheet on which recording/reproducing tracks, track pitches, and track positions for video signals are predetermined, and the tracks are formed in concentric circles, and one field of video signals is stored in one track. In the case of a frame video signal, one field of video signal is recorded on each of two adjacent tracks to form a frame video signal. The magnetic sheet l is placed in a jacket (not shown) in advance, and the jacket is provided with a claw to prevent accidental erasure, and by breaking the claw in advance, the erasing operation is prohibited in the same way as an audio cassette. . 2
is a DC motor for rotating the magnetic sheet l at a constant speed, 3
-1.3-2 is an inline type head that accesses two adjacent tracks, 3-1 accesses the outer circumferential side, and 3-2 accesses the inner circumferential side. 4 is a magnetic head 3-1.3-2
A magnetic head moving mechanism 5 moves the magnetic head so as to access the track formed on the magnetic sheet 1, and a magnetic head moving mechanism 5 moves the magnetic head 3-1 when the magnetic head 3-1 accesses the innermost track 1 on the magnetic sheet 1 by the magnetic head moving mechanism 4. The state switches from off to on, and the microcomputer (hereinafter C
(referred to as PU) 40 is an innermost detection switch that outputs an L level signal, 6 is a reproducing amplifier for amplifying the signal detected by the magnetic head 3-1.3-2, and 7 is a signal from the reproducing amplifier 6. a level detector that detects the average value of the output signal;
8 is a comparator that detects whether the output of the level detector 7 is higher than a threshold value set by a reference voltage source (not shown); 9 is a demodulation circuit that demodulates the output signal of the reproduction amplifier 6;
O is a 1/2H delay circuit that delays the output of the demodulation circuit 9 by 1/2 horizontal scanning period (hereinafter referred to as 1/2H), and 11 is a circuit that outputs the horizontal synchronization signal Hsync, vertical synchronization signal Vsync, etc. from the output of the demodulation circuit 9. 12 is a data demodulator that detects a predetermined data signal from the output of the reproduction amplifier 6 and demodulates the data signal according to the timing of the sync signal separated from the sync signal separation circuit 11; It is. The data signal is a signal for determining what kind of information is recorded on the track, for example, whether it is a field video signal or a frame video signal, and a signal for the date set by the user. , freely set by the user! The signal indicates a one-digit number and is recorded in a frequency band lower than that of the video signal at a position having a predetermined relationship with the portion of the track where the synchronization signal is recorded. The reason why the demodulation circuit 9 and the data demodulation circuit 12 are provided separately here is as follows. In other words, the video signal recorded on the magnetic sheet l is FM modulated, but the data signals other than the video signal are DPSK modulated (Differatia! Phase), which is different from FM modulation.
5hft Keying) is adopted. Therefore, the demodulation circuit 9 described above is an FM demodulation circuit, and the data demodulation circuit 12 is a DPSK demodulation circuit.

13 is a monitor for reproducing and observing video signals, and 13' is a printer connected to print the video signals. The printer 13' starts operating when the signal at the start signal input terminal becomes I (level), and the busy signal output terminal is set to L level during operation. A synchronization signal separation circuit 1 is a modulator that performs DPSK modulation on output data, and is a synchronization signal separation circuit 1 from a video signal input from a video input terminal 18.
H s yn , V s y separated by 7
The data modulated at the timing according to nc is output to the recording amplifier 16.

15 is F for the video signal input from the video signal input terminal 18.
This is a recording amplifier that performs processing necessary for recording such as M modulation and outputs it to the recording amplifier 16. A reference signal generator 19 generates accurate reference pulses (60 Hz) for rotating the magnetic sheet 1 and an alternating signal for erasing.

Reference numeral 20 denotes a magnetic piece provided on the magnetic sheet 1 described above, and as will be described later, the reference signal generator I9 uses a signal from the magnetic piece 20 to generate the signal No1! ,・(I
The rotation control of the DC motor 2 is performed in exactly synchronized manner.

21 is a PC coil for detecting a signal from the magnetic piece 20 when the magnetic sheet 1 is rotated by the DC motor 2.

22 is a waveform shaping circuit that shapes the waveform of the signal output from the PC coil 21, and the output of the waveform shaping circuit 22 is manually input to a CPU 40 and a motor control circuit 23, which will be described later.

Reference numeral 23 denotes a control circuit for controlling the rotation of the DC motor 2, which outputs Vsync from the synchronization signal separation circuit 17 or the output signal of the reference signal generator 19, and the output of the waveform shaping circuit 22, i.e. The rotation of the I)C motor 2 is controlled so that the phase relationship with the signal from the magnetic piece provided on the magnetic sheet l is in a predetermined relationship, for example, so that the two phases are always shifted by 71-1. Here, magnetic head 3-1.3-2
When a recording operation is performed, S W t is switched in advance to the synchronization signal separation circuit 17 side, and Vsync and the signal input from the waveform shaping circuit 22 , that is, the magnetic piece 20 provided on the magnetic sheet 1 The rotation of the DC motor 2 is controlled based on signals from the magnetic head: 3-1.
3-2, when the reproduction operation is performed, the SWI is switched to the reference signal generator 19 side, and the reference signal from the reference signal generator 19 and the signal input from the waveform shaping circuit 22, that is, the magnetic sheet 1 Magnetic piece 20 provided on top
The rotation of the DC motor 2 is controlled based on signals from the DC motor 2.

23' is a driver that drives a step motor 24 for controlling the position of the head 3-1, 3-2 based on a signal from the CPU 40, which will be described later, and the step motor 24 drives the head moving mechanism 4. Via・\rad3-
1. Move 3-2.

25' is a display circuit driven by a signal from the CPU 40, and as a display element, as shown in FIG. -1.3-2 7-segment display element to display the feed speed in 2 digits, PR and LED to indicate playback mode, RFC and LED to indicate record mode Frame mode FRAM E, t-E to display I)Fll screen to display field mode 1. It consists of D, I, E I).

26 is a ROM in which the program of the CPU 40 is stored.
.

27 is a RAM in which data of CI) U 40 is temporarily stored. 28 is a timer driven by the CPU 40, and 29 is a crystal oscillator that generates a reference clock for the CPU 40. Note that 80 is a detection circuit connected to photocouplers 81 and 82 that constitute a detection switch for detecting whether or not the magnetic sheet 1 is inserted.

83.84 and SW6 are data signals (hereinafter N
)) on the monitor 13 and printer 13-; 83 is a circuit for displaying Vsync and Llsync of a video signal input via SW5 for adjusting the timing of data characters to be generated; This is a synchronous separation circuit that separates the synchronous separation circuit, and has the same configuration as the synchronous separation circuit shown as 17. 84 is a character generator for generating characters corresponding to data signals in synchronization with Vsync and Hsync separated by the synchronization separation circuit 83. I to monitor 13 and printer 13-
When displaying No. D16 by superimposing it on the video signal, c
A control signal is applied from the PU 40, the SW 6 is turned on, and the synchronization signal and the data signal are added by the adder shown as ■ in FIG. 1, and are displayed at a specific position on the monitor 13 or printer +3-. The details will be described later.

85 is an erase signal generator for erasing signals on any track of the magnetic sheet l. Note that the AC signal for erasing is provided from the reference signal generator 19.

Here, the erasure signal generator 85 generates a constant amplitude period TI and a subsequent attenuation period 1 as shown in FIG. 29, for example.
A recording amplifier 16 generates an attenuated signal formed by
connected to.

SWI is a switch whose state is changed by a signal from the control circuit 30 driven based on a signal from the CPU 40, and a video signal is input from the video signal input terminal 18, and Hs y n is input from the synchronization signal separation circuit I7. c is being output, and when a signal indicating that it is in recording mode is input from the CPU, the synchronization signal separation circuit 17 and the motor control circuit 23 are connected, and the synchronization signal separation circuit 17) lsync is not output, or a signal indicating the reproduction mode is input from the CPU II O, or the reference signal generator 19 and the motor control circuit 23 are connected in the erase mode.

SW2 is a switch whose state is changed based on a signal from the CPU 40, and is connected to the state where the head 3-1 is connected to the recording amplifier 16, the state where it is connected to the playback amplifier 6, and whether the head 3-1 is connected to the recording amplifier 16 or the playback amplifier 6. Switch between an intermediate state in which no connections are made.

Like SW2, SW3 is a switch that changes its state based on the signal from the CPU 40, and connects the head 3-2 to the recording amplifier 16, connects it to the playback amplifier 6, and connects the head 3-2 to the recording amplifier I6 and the playback amplifier. 6 and an intermediate state in which it is not connected to any of

When reproducing a video signal from the magnetic sheet 1, the SW4 is switched to the upper position in FIG. When the head 3-1 is connected and a field video signal is reproduced using only the head 3-1, the demodulation circuit 9 is switched to the upper side and the lower side in FIG.
This switch is driven by the CPU 40 so that the state connected to the I/2H delay circuit and the state connected to the I/2H delay circuit are alternately switched for each field.

SW5 connects the monitor 13 to the video signal input terminal 18 during recording.
This is a switch driven by the CPU 40 to connect the monitor 13 to SW4 during playback.

By the way, as mentioned above, the video signal recorded on or reproduced from the magnetic sheet 1 can be a field video signal consisting of only one field, or a frame video signal consisting of two fields in a pair. However, in such a case, SW2. SW3. Switching of the states of SW4 and SW5 will be explained using FIG. 2.

Figure 2 shows SW2. SW3. SW4. It is a figure which shows the combination of the switching state of SW5.

During field playback, SW2 connects the head 3-1 to the playback amplifier 6, and sets SW3 to an intermediate state, that is, the head:
1-2 is not connected to either the playback amplifier 6 or the recording amplifier 16, and SW4 outputs the signal directly from the circuit 9 to the monitor 13 in odd fields, and delays 1/2) in even fields. Monitor 1 via circuit 10
The signal is alternately switched for each field so that the signal is output to the 3rd field, thereby preventing the occurrence of skew distortion.

Next, in frame reproduction, SW2 connects the head 3-1 to the reproduction amplifier 6 in odd fields, and is in an intermediate state in even fields, SW3 is in an intermediate state in odd fields, and connects the head 3-2 to the reproduction amplifier 6 in even fields. Connect to. Therefore, during frame reproduction, signals from either head 3-1 or 3-2 are alternately output to the reproduction amplifier 6 for each field.

In this case, SW4 is switched to the upper side of FIG. 1, and the signal from demodulation circuit 9 is directly output to monitor I3.

In any of the above-described field reproduction and frame reproduction states, SW5 is driven so that the monitor 13 is connected to SW4.

Next, in field recording, SW2 connects the head 3-1 to the recording apparatus 16, and SW3 is in an intermediate state.

Therefore, when recording in the field, head 3-1 produces 8
A self-recording session will be held.

In frame recording, SW2 connects the head 3-1 to the recording amplifier 16 in odd fields and is in an intermediate state in even fields; SW3 is in an intermediate state in odd fields, and connects the head 3-2 to the recording amplifier 16 in even fields. Connecting. In frame recording, the combination of heads 3-1 and 3-2 can also be reversed.

Further, in both field recording and frame recording, during recording, the SW 5 is switched so that the monitor 13 is connected to the video signal input terminal 18 so that the video signal to be recorded can be observed on the monitor 13. In addition, if this occurs, SW
4 may be in any state.

Next, the erase mode will be explained. In the erase standby state, which will be described later, SWl is on the reference signal generator side;
5 is connected to the upper side in FIG. 1, and is in the same state as the reproduction mode. At this time, the field /11 erases only the track being reproduced by the magnetic head 3-1, for example. A case will be described.In this case, at the same time as erasing starts, a control signal is sent from the CPU 40 so that SW2 is placed on the recording amplifier side and SW3 is placed in an intermediate state.Furthermore, an erase signal trigger pulse is sent from the CPU 40 to the erase signal generator 85, and the head The erase signal is sent only to 3-1.

Next, a description will be given of frame erasing in which tracks being accessed by heads 3-1 and 3-2 are simultaneously erased. When erasing a frame, an erasing signal is sent to the heads 3-1 and 3-2 at the same time, so the CPU 40 sends a control signal so that SW2 and SW3 are both on the recording amplifier side. and cp
A trigger pulse from u40 generates an erase signal, which flows to both heads via the recording amplifier.

Furthermore, in this embodiment, when performing field erasing, the erasing is performed using head 3-1, but when field erasing is performed using head 3-2, SW 2 is in an intermediate state.
It is only necessary to control SW3 so that it is on the recording amplifier side.

Next, the switches 51 to 78 shown in FIG. 1 will be explained.

In giving this explanation, the external appearance of the apparatus of this embodiment shown in FIGS. 3 and 4 will also be explained.

FIG. 3 is a front view of the apparatus of this embodiment, and FIG. 4 is a front view of a remote control device used in the apparatus of this embodiment.

The switches 51 to 79 and 72 shown in FIG. 1 are the switch group provided in the device shown in FIG. 3, the switch group provided in the remote control device shown in FIG. The switches are divided into groups of switches provided in both the illustrated device and the remote control device shown in FIG. 4, and switches having the same functions are given the same reference numerals in FIGS. 1 to 4. Note that the switch installed in the device shown in FIG. 3, which in FIG. 1 is recessed only in the remote control device shown in FIG.
I) For convenience, the signal is shown as being connected to U/lO, but the signal generated by operating the switch provided only with the remote control device shown in FIG. The light is converted into infrared light by the control device and input to the CPU 40 of the device shown in FIG. 3 via the remote control light receiving section 45 provided in the device.

It should be noted that the method of arranging the switches 51 to 79 can be considered in various other variations of this embodiment, and is not limited to this embodiment.

In FIGS. 1 to 4, 41 is a power switch, 42
is a slot for inserting the magnetic sheet 1, and when the inject button 43 is turned on while the magnetic sheet 1 is inserted into the slot 42, it opens automatically and the magnetic sheet 1 is inserted.
is injected. 43 is the above-mentioned inject button, 44A and 44n are the above-mentioned r'n, LED, and REC, respectively.
, LED, 45 is a remote control light receiving part that receives a signal from the remote control device shown in FIG. 25 is the aforementioned 2-digit 7-segment LED.

5OA and 50 skin 50C each have one program playback setting switch 58, an interval time setting switch 57,
This is an LED that displays the operating state of the program track setting switch 62.

51 is a REC mode switch for setting the recording mode and checking whether the track accessed by the head in the recording mode is recorded or unrecorded; when the switch is turned on, the track accessed by the head is (If the track being accessed by head 3-1 is already recorded during field recording, which track is being accessed by head 3-1.:l-2 during frame recording) REC if already recorded)
, the LED flashes to indicate that the track being accessed by the head cannot be recorded, and if it has not been recorded,
Further, when the control circuit 30 determines that no video signal is input, the REC and LED light up to indicate that recording is possible.

52 determines the timing to perform recording movement 1'1+
<ZC switch and RIζC mode setting switch 51
When the recording mode is set by , and the switch 51 is turned on, recording is performed on the magnetic sheet 1. If continuous recording is set in advance by a track feed speed setting switch 56, which will be described later, the head 3-1 is automatically set while the switch 51 is on.
．． Continuous recording is performed while 3-2 is shifted.

Reference numeral 53 denotes a [lB mode setting switch] for setting the playback mode, and when the switch 53 is turned on, PB, T, and ED light up to indicate the playback mode.

54 is a track U I) switch, and the switch 5
4, the driver 23' is controlled to rotate the step motor 24, and the head moving mechanism 4 moves the heads 3-1 and 3-2.
1. Shift 3-2 to change the track that the head is accessing more toward the inner circumference. Further, when recording is performed in frames using a field/frame setting switch 59, which will be described later, the recording progresses two tracks at a time. When the track Lll) switch 54 is turned on when playback is set, the heads 3-1, 3-2 are shifted two tracks at a time, and
The segment LED 25 also displays the track number shifted by 2 tracks instead of the track number shifted by 1 track, and when field recording or playback is set, the track UP switch 5 is displayed.
When the head 4 is turned on, the head 3-1.12 is shifted one track at a time toward the inner circumference, and the shift number shifted one track at a time is also displayed on the seven segment LED 25.

In addition, when the recording mode is set and the track UP switch 54 is operated, the head 3-1°3-2
REC if the track accessed by the head 3-1.3-2 has already been recorded when the head 3-1.3-2 is shifted.

RED44B performs a blinking display. 55 is a track DOW switch which is opposite to the track UP switch 54 and is used to change the access of the heads 3-1, 3-2 toward the outer circumference.
It is an N switch.

When the switch 55 is also set to frame playback in the same way as the track UP switch 54, when the switch 55 is operated and frames are being recorded on the outermost track of track 1 and the track on the outer circumference of track 2. The track number shifted by 2 tracks is displayed on the 7 segment LED 25 instead of the track number shifted by 1 track, and when the switch 55 is operated when field recording or playback is set, 1 track is displayed. The shifted track number will be displayed.

Also, in the case where the recording mode has been set in advance as described above with respect to the track UP switch 54, and when the head 3-1.3-2 is shifted by operating the track DOWN switch 55, REC if the track has already been recorded.

The LED 44B performs a blinking display.

56 automatically switches whether to perform such operations continuously or singly while shifting the head when recording and reproducing, and if the operation is performed continuously, the bancho determines how many times per second the operation is performed. This is a track feed speed 1 setting switch for setting the track feed speed shown.

When the switch 56 is pressed once and turned on, the track feed speed is displayed instead of the track number on the 7-segment LED 25, and in this state, the track feed speed setting switch 56 is turned on again within the predetermined time clocked by the timer 28 shown in FIG. is turned on, each time the switch 56 is turned on, the 7-segment LED 2
For example, "5" indicates continuous recording or playback of 2 screens per second, "5" indicates continuous recording or playback of 5 screens per second, or continuous recording or playback of 10 screens per second. 11, "/D" indicating that the recording or playback will be performed, and "8" indicating that recording or reproduction will be performed singly are displayed cyclically. Also, by turning on and then turning off the switch 56, the track feed speed is displayed instead of the track number on the 7-segment LED 25, and the timer 28 is displayed without turning on the switch 56 again.
When the measurement of the predetermined time is completed, the corresponding L E D
25 returns from the state where the track feed speed is displayed to the state where the normal track number is displayed.

Furthermore, when the track feed speed is changed by the switch 56, if frame video recording is set in advance by the field/frame setting switch 59 and the REC mode setting switch 51, continuous recording of 10 screens per second is not set. .

57 is an interval time setting switch. That is, the interval time setting switch is used to set the interval time for track forwarding when continuous playback is performed but the playback interval time is relatively long, or when program playback is set by the program track setting switch 58 described later. and
An interval time is set using the ten key switches 63 to 72 within 10 seconds after the switch is turned on.

Incidentally, when any switch other than the 10 key switches 62 to 72 is turned on after the interval time setting switch 57 is turned on, the interval time setting is automatically canceled. Reference numeral 58 denotes a program playback setting switch for setting a program playback mode in which the order of playback tracks is programmed in advance and the playback operation is performed continuously at the interval time interval set by the interval time setting switch 57.

To designate the order of playback tracks, first turn on the switch 58 to set the program playback mode, and then operate the track UP switch 54 and track DOWN switch 55 to select the track being accessed by heads 3-1°:3-2. This is done by changing the number of the desired track, reproducing the video of the desired track, checking it on the monitor 13, and turning on a program track setting switch 62, which will be described later, to memorize the number of the track being checked on the monitor 13. Reference numeral 59 denotes the aforementioned field/frame setting switch, and each time the switch is turned on, the field recording or playback mode is switched, and the frame recording or playback mode is switched to companion.

Note that if the continuous recording mode of 10 screens per second is set in advance by the REC mode setting switch 51 and the track feed speed setting switch 56, and the frame recording is selected by the field/frame setting switch 59, the track feed will start. The speed is automatically changed to continuous recording mode of 5 screens per second.

That is, compared to field recording, during frame recording the head 3-1.3-2 must be shifted two tracks at a time, so when recording 10 screens per second, 20 tracks per second are required. In other words, taking into consideration the time to record the video signal, the head must be shifted for two tracks in 4/60 seconds, but such a high-speed head shift would be cumbersome, so this implementation was carried out. In the example, continuous recording of frames for 10 screens per second is prohibited.

Reference numeral 60 is a start switch for performing continuous interval playback or program playback. When the start switch is turned on, if interval playback is set, the recorded tracks will be played back sequentially starting from the first track during the interval time. Interval playback 1 is started according to the interval time set by the setting switch 57 and the ten key switches 63 to 72, and when program playback is set, program playback is started. 61
is a stop switch that stops the playback operation started by the start switch 60, and when the switch 61 is turned on during program playback, the playback of the program is stopped while the track being played at the time is being played.

62 is the aforementioned program track setting switch.

Reference numeral 73 is a switch for starting TD stage setting in the recording mode and for switching whether or not to display the ID contents in the playback mode. That is, by turning on the switch 73 in the recording mode, it becomes the ID setting mode, and by turning on the switch 73 in the playback mode, it is possible to switch between displaying or not displaying the contents of the ID. 74, 75.
Reference numerals 76 denote a switch that is turned on when setting the year as an ID when the ID setting mode is entered by the switch 73, a switch that is turned on when setting the month, and a switch that is turned on when setting the day. In FIG. 1, the switches 74, 75, 76 and the aforementioned switches 57, 58, 62 are shown as independent switches, respectively, for convenience, but in this embodiment, the switches 74, 75, 76 and the switches 57, 58, 62 are shown as independent switches, respectively, as shown in the remote control device of FIG. 75 and 76 are also used as switches 58 and 57 and 62, respectively. That is, the switch 57 is used to set the program using the interval time setting switch 58, and the switch 62 is used to set the program track independently of the ID setting of September 9, 2009, so in this embodiment, the switch is also used. This reduces the number of switch members and improves operability and reliability.

In addition, various other combinations can be considered when the switch is also used.

77 is an erase standby switch for temporarily placing the device in an erase standby state when erasing information recorded on the magnetic sheet l; 78 is for executing an erase operation in the erase standby state set by the erase standby switch 77; This is the erase switch. Reference numeral 79 is an all-track erase standby switch that sets a mode for erasing all tracks.

When erasing the information recorded on the sheet I, the switch 77 is first turned on to set an erasing standby state. In such a state, the playback mode is automatically set, so that the video recorded on the track to be erased can be confirmed on the monitor 13 or on the printer 13'' before erasure is executed.

Further, by operating the 10 key switches 63 to 72 in the standby state, the number of tracks to be successively erased can be specified. Next, by turning on the erasing switch 78, one of the heads 3-1 and 3-2 is connected to the recording amplifier 16, and the data is recorded on the track by the erasing signal shown in FIG. 32 generated from the erasing signal generator 85. All tracks are automatically erased by turning on the all track erase standby switch 79 and then turning on the erase switch 78.

Next, the operation of the embodiment of the present invention will be explained using flowcharts shown in FIGS. 5 to 20, 23, and 25 to 27.

First, when the power switch 41 shown in FIG. 3 is pushed in, the power of the device shown in FIG. 1 is turned on, power is supplied to each part of the circuit, and operation is started.

#l: Then, in FIG. 5, the register S described later becomes “0”.
", the PB mode flag is set, the track feed speed is initially set to 2 screens per second, and the interval time is set to 3 seconds. Therefore, when the power is turned on, continuous playback mode is automatically set in advance. Ru.

#2: Detect whether or not a jacket having a magnetic belt I is inserted. When the jacket is pushed in, the flow branches to #3, and when it is not pushed in, the flow skips #3 and branches to #4.

#3: When the jacket having the magnetic sheet 1 is being pushed in in #2, the DC motor 3 is driven.

#4: Detect whether the head 3-1 is accessing the 50th track by detecting whether the switch 5 shown in FIG. When the head 3-1 is not accessing the 50th track, the flow branches to #5, and the step motor 24 shown in FIG. 1 is driven. The loops of #4 and #5 are repeated so that the head 3-1 accesses the 50th track.

#6: When the head 3-11 accesses the 50th track, the flow reaches this step, and in this step, the register N for accessing the memory (RAM 27) is set to 50.

#7: In this step, it is detected whether the DC motor 2 is being driven. When the jacket having the magnetic sheet 1 described above is inserted, the DC motor 2 is being driven by executing #3, so the flow advances to step #8 and the field flag is set. When the jacket is not inserted, the flow proceeds without passing through #3, so the DC motor 2 is not driven. Therefore, the flow returns to #2 to detect whether a jacket is inserted or not.

#8: When the DC motor 4 is being driven in #7, a field flag is set. Therefore, the LED 44A indicating the field mode shown in FIG. 3 lights up, and a display indicating the field mode is performed. That is, in this embodiment, when the power is turned on and the jacket is inserted, the field mode is automatically set.

#9: Detect the output of the level detection circuit 7 shown in FIG. 1 to determine whether the track being accessed by the head 3-1 is a recorded track or not.

Here, since the track that the head 3-1 is accessing has already been recorded, when the output of the level detection circuit 7 becomes H level, the flow advances to #10, and the level detection circuit 7
When the output becomes L level, the flow advances to #16.

Here, #16 will be explained first.

#16: Set "0000" to address N in memory. Here, "0000" indicates that the track corresponding to the memory address is unrecorded.

Next, the flow from #IO onwards will be explained.

At #10:19, when the output of the level detection circuit 7 is at H level, the signal recorded on the track is reproduced,
The ID signal is taken in from the data demodulator 12.

#11 Detect the contents of the ID signal to determine whether the video signal recorded on the track is a field video signal or a frame video signal. If it is a field video signal, the flow advances to #15, and if it is a frame video signal, the flow advances to #12.

#12: In this step, it is determined whether the video signal of the track that the head 3-1 is accessing is an inner track or an outer track of the frame video signal. If it is the inside track, the flow advances to #14. If it is an outside track, the flow advances to #13.

#13: If the video signal of the track that the head 3-1 is accessing is a track outside the frame video signal, set the memory address N to "0011". Note #l
When proceeding to this step for the first time, N is set to 50 in #6.

#14: In the case of a frame video transmission video inner track, set the memory address N to 0010''.

#17: When the head 3-1 is shifted to the first track and it is detected that N=1, the flow is #2.
If N=1, the flow advances to #18.

#18: When it is detected that N=1 is not in #17! The head 3-1 is shifted toward the outer circumferential side by a track amount.

#19: When the head 3-1 is shifted toward the outer circumferential side in #I8, it is subtracted from N to obtain N.

#20: If N=1 is detected in #17, that is,
When the head 3-1 accesses the first track provided on the outermost periphery and the presence or absence of recording is set in the memory, the data at the N address of the memory, that is, the first address of the memory is read here and is "0011". “If it is, specifically the first
If the track is the outer track of the two tracks that make up the frame video signal, the flow advances to #21;
If not, the flow advances to #23.

#21: If it is detected in #20 that the first track is a track outside the tracks constituting the frame video signal, the flow advances to this step. In this step, if the data at address N+1 of the memory, that is, the second address of the memory, is read and it is "0OIO", specifically, if the second track is the inner track of the two tracks constituting the frame video signal. for#
Proceed to 22.

#22: When frame video signals are recorded on two tracks, the first track and the second track, the flow moves to this step. Therefore, the field flag set in #8 is cleared and the field mode is changed to frame mode. Therefore, the field frame display LED 48 shown in FIG. 3 lights up to indicate the frame mode.

#23. #24: The register N indicating the address of the memory mentioned above is connected to the 2-digit 7-segment LED shown in Figures 1 and 3.
25.

This display allows the user to recognize the track number that the head 3-1 is accessing.

When this flow ends, the process jumps to the next flow shown in A. The flowchart shown in FIG. 6 will be explained below.

#A-1: Detects whether the REC mode setting switch 51 is turned on, and when the switch 5I is turned on, the flow calls subroutine ■ to set the recording mode, and when it is not turned on, the flow calls # Proceed to A-2.

#A-2: It is detected whether the REC switch 57 is turned on, and when the switch 52 is turned on, subroutine (2) is called, and when it is not turned on, the process proceeds to #A-3.

#A-3: Detect whether the PB mode setting switch 53 is turned on, and when the switch 53 is turned on, call the subroutine ◎, and when it is not turned on, proceed to #A-4.

#A-4: When the track UP switch 54 is turned on, the flow calls subroutine (2), and when it is not turned on, the flow advances to #A-5.

#A-5+When the track DOWN switch 55 is turned on, the flow calls subroutine (2), and when it is not turned on, the flow advances to #A-6.

#A-6: When the track feed speed setting switch 56 is turned on, the flow calls subroutine [F], and when it is not turned on, the flow advances to #A-7.

#A-7: When the interval time setting switch 57 is turned on, the subroutine ◎ is called, and when it is not turned on, the process proceeds to #A-8.

#A-8 When the nib program setting switch 58 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-9.

#A-9 When the nib program track setting switch 62 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-10.

#A-1o: When the field frame setting switch 59 is turned on, the subroutine is called; when it is not turned on, the process advances to #Δ-11.

#A-11 When the start switch 60 is turned on, subroutine (2) is called, and when it is not turned on, the process advances to #A-12.

#A-12 When the stop switch 61 is not turned on, the subroutine [phase] is called, and when it is not turned on, the process advances to #A-13.

When #A-13+jacket detection switch (corresponding to the detection circuit 80 in Fig. 1) is turned on, jumps to subroutine ■, and when it is not turned on, jumps to #A-14.
Proceed to.

#A-14 Clear the Niprogram playback mode flag and the program playback execution flag.

#A-15: When any of the to key switches 63 to 72 is turned on, subroutine (2) is called, and when it is turned on, the process proceeds to #A-16.

#A-16: When the ID switch 73 is on, call subroutine 0, and when it is on, call #A-16.
Proceed to A-17.

#A-17: When the year setting switch 74 is on, call subroutine ■; when it is on, call #
Proceed to A-18.

#A-18: When the month setting switch 75 is on, subroutine ■ is called, and when it is on, #
Proceed to A-19.

#A-19: When the date setting switch 76 is turned on, subroutine ■ is called, and when it is turned on, #
Proceed to A-20.

#A-20: When the erase standby switch 77 is turned on, subroutine (2) is called, and when it is turned on, the process advances to #A-21.

#A-21: When the all-track erase standby switch 79 is on, subroutine (2) is called, and when it is on, the process advances to #A-13.

As explained above, after the head 3-1 accesses the first track of the magnetic sheet by executing the flow shown in FIG. 5, the flow jumps to the flow shown in FIG. While detecting the state of each switch shown in FIGS. 3 and 4, the flow shown in FIG. 3 is repeatedly executed until the state of each switch changes, and a subroutine corresponding to the operated switch is called.

Here, the subroutine [F] called when the track setting feed speed switch 56 is turned on will be explained using FIG.

FIG. 7 is a flowchart showing a subroutine executed when the switch 56 for changing the track setting feed speed is turned on.

#F-1. The set value of the track feed speed is read from the #F-2+ memory, and the set value is set in a track number display buffer (not shown).

Therefore, the two-digit 7-segment LE shown in Figure 3
The track feed speed is displayed on D25. If the flow comes to this step for the first time, 2 per second in #1.
Since the track advance speed on the screen is set, select “2”.
“ is displayed.

#F-3 When the Nidrak feed speed setting switch 56 is on, the flow repeats #F-3, and when the switch 56 is turned off, the flow moves to #F-4.

As mentioned above, once the track feed speed setting switch 56 is turned on, the two-digit 7-segment LED 25 shown in FIG. 3 switches from displaying the track number to displaying the track feed speed.
Next, the track feeding speed is changed by turning on the switch 56 again.

#F-3 is provided so that the track feed speed is switched only when the switch 56 is turned on, once turned off, and then turned on again as described above.

#F-4. #F-5. #F-6. #F-7: In these steps, the track feed speed setting switch 56 is turned on, and the 2-digit 7-segment LED 25 shown in FIG.
If the switch 56 or any other switch is not turned on for a predetermined period of time (2 seconds #I) after the display switches from displaying the track number to displaying the track feed speed, the track feed speed is set. This is a step provided to stop the process.

Predetermined time (2 seconds) after timer 1 starts counting
When the track feed speed setting switch 56 is turned on during this period, the flow progresses from #F-7 to #F-10, and when timer 1 completes timing, or when another switch is turned on, the flow advances from #F-7 to #F-10. The flow advances from -6 to #F-8.

#F-8: Clear the count value of timer l.

#F-9: Contrary to #F-1, the two-digit 7 shown in Figure 3
The display of the segment LED 25 is returned to displaying the track number. □#F-10: Clear the count value of timer 1.

#F-11 The setting value of the Ni-track feed speed is single (once recorded or played back, the head is shifted by 1 track in field mode, and 2 tracks in frame mode)
Detect whether the head is shifted by a track and stop), and if it is a single, go to 11#F-12, and if it is not a single, go to #F-13.
The flow continues.

As described above, when the flow reaches this step after the power switch 41 is turned on, the track feed speed is preset at 2 screens per second in #1.

#F-12: If the l-rack feed speed setting value is single, change the setting value to 2 screens per second, return to #F-1, display the changed track feed speed, and repeat the above-mentioned #F-1. Execute steps 3 to #F-7.

#F-13: t-rack feed speed setting value is 2 per second
Detect whether it is a screen, and if there are 2 screens per second, #F-1
If the screen is not 2 screens per second, the flow advances to #F-15.

#F-14:) Change the rack feed speed setting value to 5 screens per second, return to #F-1, display the changed track feed speed, and execute the above steps #F-3 to #F-7. .

#F-15 - Detect whether the track feed speed setting value is 5 screens per second. If it is 5 screens per second, go to #F-16. If it is not 5 screens per second, that is, if 10 screens per second is set. Then the flow advances to #F-17.

#F-16 Determine whether the 2PB mode flag is set. #F-1 if the PB mode flag is set, that is, if the playback mode is set.
If the PB mode flag is reset to #8, that is, if the recording mode is set, the flow advances to #F-19.

#F-17: Change the track feed speed setting value to single, return to #F-1, display the changed track feed speed, and execute the above-mentioned steps #F-3 to #F-7.

#F-18 In the reproduction mode, field reproduction is performed during continuous track feeding, regardless of whether the video signal recorded on the track of the magnetic sheet 1 is a field video signal or a frame video signal. Therefore, in such a case, change the track feed speed setting value to 10 screens per second and the flow will be #
Return to F-1.

#F-19: Detects whether or not the field flag is set, and if the field flag is set, that is, if track advance is set at 5 screens per second in recording mode and in field mode, #F is detected. The flow branches to -18.

Also, if the field flag is not set, that is, the track feed speed setting value of 5 screens per second is set in recording mode, and in frame mode, #F-17
The flow advances to change the track feed speed setting to single.

Therefore, in the above-mentioned subroutine [F], when the track feed speed setting switch 56 is turned on, the track feed speed is displayed on the two-digit 7-segment LED 25 shown in FIG. 3 for a predetermined period of time (2 seconds). The track advance speed is changed by turning on the switch 56 again within the time.

In addition, the range of changes is single, 2 screens per second, and 5 screens per second when in frame recording mode, and single, 2 screens per second, and 5 screens per second when in other than frame recording mode.
There are 4 types of screens, 10 screens per second.

The scope of this change is head 3-1.3-2 shown in FIG.
This is related to the track shifting ability of the moving mechanism, etc., and is set in advance to an appropriate range depending on the track shifting ability.

Next, using FIG. 8, while executing the subroutine (2) shown in FIG. 6, the track UP switch 54. TRACK DOWN
The subroutines ① and ② that are called when the switch 55 is turned on will be explained. First, a flow called when the track UP switch 54 is turned on will be explained.

#I)-1: When the flow reaches this step, detect whether the track being accessed by the head 3-1 is the innermost track by checking whether the register N is 50. Distinguish by this.

As a result, if N is not 50, go to #D-2;
If it is 0, the flow advances to #D-34, which will be described later.

#D-2: Determine whether the PB mode flag is set. When the PB mode flag is set, that is, in playback mode, #D-8; when the PB mode flag is not set, that is, in recording mode, #D-8
The flow advances to 3.

#D-3: Detect whether the N+1 address of the memory is "oooo", that is, the N+1 track is unrecorded. If it is unrecorded, it is stored in #D-4. If it is already recorded, it is #D-7. Flow branches.

#D-/l: If it is determined in #D-3 that the N+1th track has not been recorded, it is determined in this step whether or not the field flag is set, and when it is set, goes to #D-6, if not set #
The flow advances to D-5.

@D-5: When it is determined that the field flag is not set in #D-4 and the mode is frame mode, this step is reached. In this step, it is detected whether the N+2nd content of the memory is 0000'', and if it is "0000", that is, if the N+2nd track is unrecorded, the process goes to #D-6. MO00
0'', that is, if the N+2 track has been recorded, the flow advances to #D-7.

By executing Steplap from #D-3 to #D-5, if both consecutive two tracks are unrecorded in frame mode, the step will be changed to #D-6, and the step number ( If both have already been recorded, #D-
The flow advances to 7.

#D-6: In the field mode, the track that the head 3-1 is accessing; in the frame mode, the track that the head 3-1 is accessing, and the track that is being accessed! If the track being accessed by the head 3-2 on the inner track side is unrecorded, that is, if it is recordable, the flow reaches this step, and the RECLED shown in FIG.
44B lights up.

#D-7: Head 3-1.3-2 opposite to #D-6
If the track to be accessed and recorded has already been recorded, a warning is displayed by blinking the RECLED 44B shown in Figure 3 to make the user aware that recording is not possible. I do.

#D-8: If the PB mode flag is set in #D-2, the flow reaches this step and the field flag is set.

For the meaning of this step, see #D-9゜#D-10.
#D=13 will be explained.

#D-9: Memory address N is “001”, that is, as explained in #13, whether the track that the head 3-1 is accessing is the outer track of the two tracks that make up the frame video signal. If the track is on the outer circumferential side of the two tracks, the flow proceeds to #D-10, and if the track is not on the outer circumferential side, the flow proceeds to #D-13.

#D-10: Memory address N+1 is 001O", i.e.
It is detected whether the track that the head 3-2 is accessing is the inner track of the two tracks that make up the frame video signal, and if it is the inner track of the two tracks, # is detected. If the track is not on the outer circumferential side, the flow proceeds to #D-13.

That is, if the inner track of the two tracks making up the frame video signal is erased or a new video signal is recorded after erasing, the track accessed by the head 3-1 will make up the frame video signal. Even if it is the outer track of the two tracks, the head 3
It happens that the track being accessed by -2 is not the inner track of the two tracks. Therefore, in this case, when shifting the head 3-1, 3-2 to the inner circumferential side, it is necessary to shift only one track and reproduce the erased or track on which the video signal is newly recorded after the erased.

However, in such a case, if the head 3-1°3-2 is
When only the track is shifted to the inner circumferential side, the head 3
-1.3 The frame video signal is not necessarily recorded on the track that is being accessed by 3-2.

In some cases, completely different field video signals are recorded. In this case, if the field flag is reset, a problem arises in that two separate field video signals are reproduced as frame video signals. By providing step #D-8 mentioned above, in this embodiment, when the head is shifted to the inner circumferential side, the field mode is set by setting the field flag in advance in this step, and the above case is performed. Also, it is possible to solve the problem that a completely different field video signal is reproduced as a frame video signal.

#D-11, register N is 49 in this step
If N is 49, #D-
If N is not 49, the flow branches to #D-12.

#D-12; The flow reaches this step when frame video signals are being recorded on the two tracks accessed by heads 3-1 and 3-2. If such a recording is made, track U
When the P switch is turned on, the driver 23 is driven to shift the heads 3-1, 3-2 by one track in this step, and then in #D-13, the driver 23 is driven to shift the heads 3-1, 3-2 by one track. -Shift 2. Further, as described above, N is updated by l each time the heads 3-1, 3-2 are shifted.

#D-13; Similar to #D-12, head 3-1.3
-2 by l tracks.

#D-+4; Similarly to #23, display N on the 2-digit 7-segment LED 25 shown in FIG.

In this embodiment, these steps are #D-12 and #D-13.
Heads 3-1 and 3-
When a frame video signal is recorded on the accessed track 2, the track number displayed on the LED 25 is updated by 2, and when a field video signal is recorded, the track number displayed on the LED 25 is updated. The number is updated by l, and it is possible to display whether a field video signal or a frame video signal is recorded on the magnetic sheet l.

Additionally, if this step is also provided between #D-12 and #D-13, if frame video signals are recorded on the two tracks accessed by heads 3-1 and 3-2, Even if there is, when the track UP switch 54 is turned on, the track number displayed on the LED 25 will be updated one by one.

#D-15, determine whether the PB mode flag is set. If set, go to #D-16,
If it is not set, the flow branches to #D-19.

If set, branch to #D-15-1.

#D-15-1; Here, the CPU 40 stores the reproduced ID signal output from the data demodulator 12 in FIG.
Incorporate into 27. The flow advances to #D-15-2.

#D-15-2; Here, it is determined whether the mode is one in which [) is superimposed on the video signal and monitored. Details of this mode will be explained using FIG. 20. If it is in this mode, proceed to #D-15-3; otherwise, proceed to #D-15-4.

#D-15-3; When the flow reaches this step, the mode is in which the ID is superimposed on the video signal and monitored, so the CPU reads the reproduced ID signal from the RAM 27,
A character pattern is generated by controlling the character generator 40 and superimposed on the reproduced video signal on the monitor. Flow proceeds to @D-15-4. That is, at this point, the ID DATA signal recorded in the currently accessed track is displayed on the monitor.

#D-15-4; If the automatic track feed flag is not set, the flow branches to @D-20, and if it is, the flow branches to #D-16.

#D-16; Address N of the memory is "0011" Determine whether or not the track being accessed by the head 3-1 is a track toward the outer circumference of the tracks on which frame video signals are recorded. Here, N corresponds to the number of the track that the head 3-1 is accessing after the head 3-L3-2 has already been moved, as repeated above. Here, the content at address N of the memory is “0011”
If it is, the flow branches to #D-17, and if it is not "0011", the flow branches to #D-19.

#D-17; The contents of memory address N+1 are “00”
10'', that is, the track being accessed by head-3-1 is determined to be the inner track of the two tracks on which the frame video signal is recorded.

Here, if address N+1 of the memory is "00IO", the flow branches to #D-18, and if not "001O", the flow branches to #D-19.

#D-18: When the flow reaches this step via #D-16 and #D-17, heads 3-1 and 9-2
Since frame video signals are recorded in the two tracks accessed after moving, the field flag set in #D-8 is cleared and the frame playback mode is entered. Note that this step is executed only if the automatic track advance flag is set. (
If the automatic track feed flag is not set, the flow branches from #D-15-4 to #D-20, so the field flag remains set in #D-8, and field playback is performed. ) #D-+9; In this step, it is determined whether or not the automatic track feed flag is set, and if it is set, the process returns to #D-20, and if it is set, the process returns from this subroutine ( RTS).

The automatic track advance flag is a flag that is set in the subroutine ■ described later, and when calling the subroutine ■ or ■ described later while running a program that repeats playback while automatically advancing tracks, the automatic track advance flag is set by the subroutine ■, which will be described later. , ■ is provided for extraction.

#D-20, Load the track feed speed setting value from memory.

#I)-2]; ) Determine whether the rack feed speed setting value is single or not, and if it is single, set #D
-34, and if it is not single, the flow branches to #D-22.

#D-22: ) Determine whether the rack feed speed setting value is 2 screens per second, and if it is 2 screens per second, check #
D-23, and #D-24 if it is not 2 screens per second.
The flow branches.

#D-23; WAIT TI in CPU 40
Set the MER register to 28.

#D-24; l- Determine whether the rack feed speed setting value is 5 screens per second, and if it is 5 screens per second, @D-
If there are not 5 screens per second, the flow branches to #D-26.

#D-25; Set WAIT TIMER register to 1
Set to 0.

#D-26; If 10 screens per second is set as the track feed speed setting value, the flow reaches this step and the WIT TIMER register is set to 4.

Note that the WAIT TIMER registers set in #D-23, #D-25, and #D-26 are used to control the track feed speed, and are set in #D-3, which will be described later.
1. In #D-32, the value is subtracted every time the magnetic sheet 1 rotates once by the DC motor 2.

#D-27; Determine whether or not the REC execution flag is set, and if it is set, #D-28;
If not set, the flow branches to #D-31. Here, the REC execution flag is a flag that is set in subroutine ■, and is a WAIT flag that is set when subroutine ■ is called during the execution of a program that repeats recording while automatically sending tracks.
This is provided to obtain the time equivalent to the time required for recording by subtracting 2 or 5 from the TIMER register in #D-29 and #D-30. That is, in the recording mode, the rotation state of the magnetic sheet l is detected from the PG coil 21 to determine the timing for recording the signal to be recorded from a predetermined position on the magnetic sheet, and the signal is recorded on the magnetic sheet l. It is set up for the purpose of

Subtract 2 from the TIMER register, and if not set, subtract 5 from the WAIT TIMER register. Here, if 10 screens per second is set as the track feed speed, the WAIT TIMER register is set to 4, but such a setting is possible only in field mode, so in this case, the WAIT TIMER register is set to 4.
Five is never subtracted from the TTMER register.

#D-31; Detects whether or not there is a pulse from the reference signal generator 19 shown in FIG. Repeat the flow.

#D-32, subtract 1 from the contents of the WAIT TIMER register.

#D-33; Determine whether the content of the WAIT TIMER register has become 0, and if it is O, #D-3
4, and if it is not 0, branches to #D-31.

In steps #D-32 and #D-33, the timer for controlling the track feed speed is set to WAIT1'.
An IMER register and a reference signal generator 19 were used. Therefore, the content of the WAIT TIMER register is used by the waveform shaping circuit 22 that shapes the output of the PG coil 21.
Compared to the method of configuring a timer by subtracting according to the exit of the timer, stable and more accurate clock operation can be performed.

That is, although the output of the PG coil 21 may include errors due to causes such as uneven rotation of the magnetic sheet 1, the output of the reference signal generator 19 has substantially no such errors. Also,
When performing interval recording, it is desirable to stop the rotation of the DC motor 2 during the interval time in order to save power consumption.

When performing such an operation, the method of subtracting the WAIT TIMER register according to the output of the waveform shaping circuit 22 is as follows.
Although it is not possible to elapse the interval time, according to the method of this embodiment, even when such an operation is performed, a stable #1 operation can be performed.

#D-34; Determine whether or not the REC execution flag is set, and if it is set, return (RTS) to the original program that called the subroutine ■; if it is not set, # Branch to D-35.

#D-35; Determine whether or not the track UP switch 54 is on, and if it is on, further shift the track accessed by the heads 3-1 and 3-2 to the inner circumferential side. Therefore, the flow branches to #D-1, and when it is off, the flow branches to #D-36.

#D-36; To determine whether or not the track DOWN switch 55 is on, and when it is on, shift the track accessed by the heads 3-1 and 3-2 to the outer circumferential side. Then, it branches to #E-1 of subroutine (2), and when it is off, it branches to #D-37.

#D-37; If the PB mode flag is set, go to #D-38; otherwise, go back to ProGuerra 4 that called the subroutine ◎.

Clear. Then the subroutine Return to Polodharam where you called ■.

In the above example, #D-23 is passed regardless of whether it passes through #D-12 in PB mode or not.
, 25, and 26, the value set in WAIT TIMEH is not changed, and if #D-12 is passed by the time required to perform one track feed, the track feed speed will be delayed. However, in order to match this, in #D-27, #D-12
If the head passes through , the track feed speed can be adjusted without any problem by subtracting the time required to feed the head for one track from WATE TIMER.

Next, subroutine (2) executed when the track down switch 55 is turned on will be explained.

Steps #E-1 to #E-13 of subroutine (2) are similar to steps #D-1 to #D-13 of subroutine (2), so a detailed explanation will be omitted.

However, subroutine ■ is track DOWN switch 55.
For example, #E-1 is used to shift the track that the head 3-33-2 is accessing to the outer circumferential side when the head 3-33-2 is turned on.
In #E-9, it is detected whether N=1, and in #E-9, the memory (N-1) battery is "0010", that is, the (N-th)
1)! - Detects whether the rack is the inner track of the two tracks constituting the frame video signal, and #E-10
In this case, the memory address (N-2) is "001 bit", that is, the (N-2)th track constitutes the frame video signal.
It detects whether the track is outside the tracks, and also detects whether N=2 in #E-11, and #E-11 detects whether N=2.
12. For #E-13, head 3-1.3- for one track.
2 to the outer circumference.

Next, subroutines ① and ② that are called when the field/frame changeover switch 59 and the RIEC mode setting switch 51 are turned on will be explained using FIG.

#J-1: When it is detected in #A-10 shown in FIG. 6 that the field/frame changeover switch 59 is turned on, the flow advances to this step, and in this step, the field flag is set. If it is set, go to #J-2, if it is not set, go to #J-4
The flow branches.

#J-2: When the field flag is set in #J-1, the field flag is cleared in this step.

#J-3, it is determined whether the FB mode flag is set, and if it is set, the flow branches to #J-8; if not, the flow branches to #J-5.

#J-4; When it is detected in #J-1 that the field flag is not set, the field flag is set in this step.

If the PB mode is not set, that is, in recording mode, and the field flag is cleared in #J-2, frame recording mode is entered, and as explained in subroutines ■, ■, and [F], every second 10
Continuous recording of the screen is not possible. Therefore, the subroutine■
When switching from field mode to frame mode, if the track feed speed is set to 10 screens per second,
Such switching should be prohibited.

Therefore, according to this embodiment, #J-6 and #
When a track feed speed of 10 screens per second is set by J-7, the track feed speed setting value is automatically changed to a track feed of 5 screens per second.

#J-5; I-Rack feed speed setting value from CPU
Incorporate into 40.

#J-6; If the track feed speed setting value imported in #J-5 is 10 screens per second, #J
-7, and if it is not 10 screens per second, the flow branches to #J-8.

#J-7; Change the track feed speed setting value to 5 screens per second.

#J-8: Field/frame setting switch 51
If the switch continues to be turned on, this step is repeated, and only when the switch turns from on to off does it return to the step shown in #Δ-1 in FIG.

Next, subroutine (2) called when the REC mode setting switch 51 is turned on will be explained.

#B-1; REC in #A-1 shown in Figure 6
When it is detected that the mode setting switch 51 is turned on, the flow branches to this step, and the PB shown in FIG.
The SLED 44A turns off and the PB mode flag is cleared.

#13-5-1; This step uses CPU40
controls the character generator 84 to temporarily stop character generation.

#B-5-2: Determine whether or not it is the ID setting mode. If it is the setting mode, proceed to #B-5-3; otherwise, proceed to #B-6'.

#l3-5-3; The CPU 40 reads the set ID from the RAM 27 and controls the character generator 84 to generate a character pattern. Therefore, l is displayed on the monitor 13 superimposed on the video signal input from the video signal input terminal I8. The flow then proceeds to #B-6'.

#I'3-6'; This step is repeated while the REC mode setting switch 51 continues to be turned on, and when the switch is turned off, the flow branches to #B-7.

#13-7, When the REC mode setting switch 51 is turned off, it is determined in this step whether the field flag is set, and if the field flag is set, the process goes to #A-1 in FIG. The flow returns to the step shown, and if the field flag is not set, jumps to #J-5 of subroutine ■, and #
By executing steps J-6 to #J-8, when the track feed speed setting value is 10 screens per second, it is automatically corrected to 5 screens per m second. Therefore, when the REC mode is set by the REC mode setting switch 51 and the frame mode is set, the track feed speed setting value is limited to a maximum of 5 screens per second.Next, the PB mode is set using Figure 1'0. switch 53
We will explain the subroutine ◎ that is called when is turned on.

#Cl; I in #A-3 shown in Figure 6
'When it is detected that the B mode setting switch 53 is turned on, the flow branches to this step, the RECLED is turned off, and the field flag is temporarily set. That is, separate field video signals are recorded on the two tracks accessed by the heads 3-1 and 3-2, and the PB
Frame record j:i! with mode flag cleared and field flag reset! When the mode is set, when it is detected that the P13 mode setting switch 53 is turned on and the track being accessed by the head 3-1.3-2 is immediately played back, the separate field video signals are interlaced and played back. In order to prevent this from happening, a field flag is temporarily set in this step.

:C-2, the memory address is "001bi, ie spatula 1;' :(Detects whether the track being accessed by -1 is the outer circumferential side of the two tracks where the frame video signal is recorded, #C when it is “0011”
-3 If it is not "0011", the flow branches to #C-51, "4C:3 + Memory address N+1 is "001O"
That is, it is detected whether the track being accessed by the head 3-2 is the inner track of the two tracks on which the frame video signal is recorded, and if it is "ooto", #C-
4. If the value is not "0010", the flow branches to #C-5.

#C-4; Head 3-11 in #C-2 and #C-3
When it is detected that frame video signals are recorded in the two tracks that are being accessed by 3-2, the flow reaches this step, the field flag is cleared, and the frame mode is set.

#C-5: PI3, L I:, I) shown in Figure 3
ll ll A lights up, I) [3 mode flag is set, and playback operation starts.

#C-5-1; In this step, the CPU 40 controls the character generator 84 to temporarily stop generating characters. Further, the CPU 40 stores the ID DATA demodulated by the data demodulator 12 in the RAM 27.

#l3-5-2; Determine whether or not it is in ID display mode. If it is in display mode, proceed to #C-5-3; otherwise, proceed to #C-6'.

#C-5-3. The CPU 40 reads the ID demodulated by the data demodulator 12 from the RAM 27 and sends it to the character generator 8.
4 to generate a character pattern. Therefore monitor! 3, the ID is displayed superimposed on the video signal reproduced from the magnetic sheet. Then the flow is #C
-Proceed to 6.

#(, -6, If the Pn mode setting switch 53 continues to be turned on, this step is repeated, and when it is turned off, the #/l-
Return to 1.

Next, using Fig. 11, set the interval time setting switch 5.
The subroutine ① that is called when 7 is turned on will be explained. First, in the subroutine O#G-0, the timer 1'' is initialized to 0, and the 7-segment LED 25 displays the interval time 1''.

#G-1: In #A-7 of FIG. 6, when it is detected that the interval time setting switch 57 is turned on, the timer T' is initialized to 0, and then the flow reaches this step, Furthermore, when the 10 key switches 63 to 72 are turned on, the signal goes to #G-2, and the 10 key switches 63 to 72 are turned on.
When 72 is not turned on, the flow branches to #G-3.

#G-2, change interval time 1'i to interval time Ti set by lO main key switches 63-72.

HC knee: ', ; 10 key switch 63-72
Determine whether the other switches are on or not, and if they are on, #G-4; if not, #G-4.
Branch to G-5.

#G-4; Detects whether or not the interval time setting switch 57 is turned on, and when it is turned on, #G-4;
When G-1 is not turned on, #A- shown in Figure 6
The flow branches to 1.

#G-5: Increase the aforementioned T' by 1. The flow moves to #G-6 every second.

However, T' is a timer that is incremented by 1 every second, and no addition is made if less than one second has elapsed.

#G-6; Determine whether 'r' is 10 or not, T
When ' is 10, T' is #/l-1 shown in FIG.
is not 10, branches to #G-1 and returns to # above.
G-1, #G-3.

Repeat the loop of #G-5 and #G-6 until '1'' is 10
When it becomes, it returns to #Δ-1.

Therefore, in the above-mentioned subroutine ◎, if the pond switch is not turned on within 10 seconds after the interval time setting switch 57 is turned on, #A shown in FIG.
The value returns to -1 and the interval time setting is canceled. Of course, the interval time while executing the subroutine ■゛i
is displayed in the two-digit 7-segment LED 25, but the display of the interval time 'ri required when returning to #A-1 at #G-6 stops.

Also, in this subroutine ■, 1 at the interval;
When 1 dollar l'1 is set to "0", an external trigger mode is set which causes an operation to be performed when connecting to a printer, for example, as described in subroutine (3) as a reproduction operation.

Next, subroutine (2) called when the RFC switch is turned on will be explained using FIG. 12.

#N-1; When it is detected in the sixth step #A-2 that the REC switch 52 is turned on, the flow reaches this step, and ■) checks whether the I3 mode flag is cleared or not. If it is not cleared, the flow returns to #A-14 shown in FIG. 6 (RTS) because it is in the playback mode, and if it is cleared, the flow branches to #N-2.

Therefore, if the REC mode is not set, no recording will be performed even if the REC switch 52 is turned on.

#N-2; It is determined whether the N address of the memory is "0000", that is, whether the track being accessed by the head 3-1 is unrecorded or not. If it is not unrecorded, the process shown in FIG. 6 is performed. The flow returns to #A-14, and if it is unrecorded, the flow branches to #N-3.

#N-3; It is determined whether the field flag is set, and if it is set, the flow branches to #N-5; if it is not set, the flow branches to #N-7+.

#N-11: This step has a frame + 2 pieces of h,
This will occur when the A mode is set, but the N+1 address of the memory is “oooo”, that is, head 3.
It is determined whether or not the accessed track of -2 is unrecorded, and if it is not unrecorded, #Δ-1 shown in FIG.
The flow returns to 4. In addition, in such a case, REC, I
, ID44B is blinking.

This track was also unrecorded. In this case, the flow branches to #N-6.

8N-5, a video signal for one field is recorded on one track on the magnetic sheet 1 by the head 3-1. At this time, the SW 6 shown in FIG. 1 is turned off and the output of the character generator 84 is no longer output to the monitor. Also, 0001 is set in the memory address N.

#N-6, when the flow reaches this step, frame recording mode is set, so 2 on the magnetic channel l is set.
Video signals for one field are recorded on each of the two tracks by heads 3-1 and 3-2. 0011. at memory address N. 0010 is set at address N+i and S Vy' 6 is turned off similarly to #N-5. Next, the step motor 24 is driven to shift the head 3-1, 3-2 inward by one track.

Note that when #N-5 and #N-6 are executed, SW2 to SW5 are driven as explained in FIG. Also #N-6
When recording is executed in
The set ID is read from the A M 27, and by outputting it to the data modulator 14, the ID modulated into a DPSK signal from the data modulator 14 is input to the recording amplifier 16, where it is converted into a video signal. ID recording is performed by superimposing them. However, the ID display mode is
In the case of Figure 0C), no ID is recorded even if data is set. However, DA indicating whether it is the inner track, outer track, or field recording of the frame.
TA is simply recorded together with the video signal. Also, even in the display mode of Fig. 20 a) and b), #N-5.
By executing #N-6, the ID DATA signal will not be displayed on the monitor unless SW6 is turned off during recording.

#N-7: The REC execution flag is set and SW6 in FIG. 1 is turned on.

By executing #N-1 to #N-7, when the set ID is generated by the character generator 84, superimposed on the video signal, and output to the monitor, the REC
The character signal that is generated only during execution is SW in Figure 1.
6 will turn it off and the characters will disappear. At #N-7, SW6 is turned on again, so ID DATA is displayed again.

#N-8: Call subroutine ■, head 3-
If 1 is accessing a track other than the 50th track, #
The flow moves from D-1 and #D-2 to #D-3. Next, steps #D-3 to #D-14 are executed to move the head 3-1, 3-2 to the inner circumferential side by one track. In the frame recording mode, the heads 3-1 and 3-2 have been moved to the inner circumferential side by one track in advance at #N-6, so even in the frame recording mode, the head 3-1 is #D-6. The track adjacent to the track recorded in step 14 is accessed. Further, when the track recorded by the head 3-1.3-2 has been recorded, the REC and LED 44B shown in FIG. 3 blink to warn the user.

The flow then branches from #D-15 to #D-19 and #
The flows shown in #D-20 to #D-34 are executed via D-19.

That is, if the track feed speed setting value is single, the flow branches from #D-21 to #D-34, and returns to #N-9 according to the REC execution flag set in advance in #N-7. .

If 2 screens or 5 screens per second are set, subtract the WAIT TIMER register by the time necessary for recording in #D-28, and then
Count down the TIMER Regis evening and WΔIT
'I'1 When the MER register becomes O, the flow is #
From D-33; 1) #N- via -34 as above
The process returns to #N-9 according to the REC execution flag set in step 7.

#? 19; Clear the REC execution flag.

';: NIO; Such step is #D-2
This is the same step as step 0, and the set value of the track feed speed is imported from memory.

#N-II; If the set value of l-rack feed speed is single, go to #N-12; if not single, go back to #A-14 shown in FIG.

#N-12; When the track feed speed is set to single, this step is repeated as long as the REC switch 52 is on, and subroutine (2) is executed again to control so that no recording is performed.

When the track feed speed is set to other than single and the REC switch 52 is turned on, #N-
11 through #A -1'I:, \-11#A
The subroutine (2) is called from -2 and the aforementioned flow is executed, and recording is performed continuously at the set track feed speed while the RI', C switch 52 is on. If the REC switch 52 is turned off, the flow is #A-
14, the process proceeds to #A-1 and #A-2, but the continuous recording ends without calling subroutine (2) at #l\-2.

Next, the subroutine (2) called when the program setting switch 58 is turned on will be explained using FIG.

#11-1; When it is detected that the program setting switch 58 is turned on in #Δ-8 of FIG. 6, this step is reached, and it is determined whether or not the PB mode flag is set, and When it is set, it is set to #H-2, when it is not set, it is set to #6.
#A-11, shown in the figure: Return (R'rS).

This step is provided to prohibit program settings in the recording mode. That is, in this embodiment, when setting a program, by selecting the second playback mode, the program is set while checking the video recorded on the magnetic notebook 1 on a monitor, for example.

Further, by automatically setting the 1)+3 mode flag when the program setting switch 58 is turned on, the operation to the reproduction mode can be performed automatically.

In this case, a CALLC may be provided to call the subroutine ◎ as a step similar to the step shown in the subroutine ◎, that is, in place of the step shown in #H-1.

#11-2, the first one where the program is stored
4 When executing program playback in the program track memory shown in Figure 4, the next track number to be played is 8.
Set the ■register indicating the self-memorized address to O.

3 I+-3, sets the program playback mode flag indicating the program playback mode and returns to #l\-1.

Next, the subroutine (2) called when the program track setting switch 62 is turned on after the program reproduction mode is set by the subroutine (C) will be explained with reference to FIG.

#I-1, determine whether the program playback mode flag is set, and if it is set, go to #I-2;
When not set, the flow branches to HA-1.

Therefore, when the program playback mode is not set by the program setting switch 58, no program setting operation is performed even if the program track setting switch 62 is turned on.

#I-2, register S (
In #l, the same contents as those of S-0 (initialized as S-0 when the power is turned on) are written to register M.

#I-3: The data in the program track memory at the address stored in register M is
stored at a larger address. In other words, the data indicating the track number stored in the program track memory is stored at an address larger by l than the address where the data is stored.

#I-4; Write the value obtained by adding 1 to the contents of register M to register I.

Lr-5; Subtract 1 from the contents of register M.

#r-6, it is determined whether the contents of register M are 0 or not, and if it is 0, the flow branches to #I-7, and if it is not 0, the flow branches to #I-3.

The flow from #I-3 to #I-6 is repeated, and when the contents of register M become O, all data stored at each address in the program track memory is transferred to an address larger by l. Therefore, when this flow is repeatedly executed and the flow branches from #I-6 to #I-7, no data is stored at address l of the program track memory.

#I-7; The number of the track that the head 3-1 is accessing is stored at address l of the program track memory. Therefore, by turning on the program track setting switch 62, the number of the track where the video being accessed by the head 3-1 and being reproduced is recorded is programmed.

' #I-8; Add 1 to the contents of register S.

By executing this step, the start address (largest address) where the program track memory data moved by executing the flow of #■-3 to #■-6 is stored is always stored in register S. It turns out.

#I-9: If the program track setting switch 62 is turned on, repeat this step, and if it is turned off, return to #A-1.

If the user wants to continue setting the program, turn on the track UP switch 54 or the track DOWN switch 55 to set the head 3-1.3-.
Program settings can be made by changing the track being accessed in No. 2 and turning on the program setting switch 62 while checking the reproduced video when the desired track has been reproduced.

Note that each time the program setting switch 62 is turned on, the 14th
The data stored at each address of the program track memory shown in the figure is stored at an address larger by l. Also, during program setting, register S1 and register ■ all have the same contents.

Next, program playback is performed to play back the program set by turning on the program setting switch 58 and the program track setting switch 62, and the head 3-1
The first part about the program executed when performing interval playback, which plays recorded tracks sequentially at a set interval time, starting from the track being accessed.
This will be explained using FIGS. 6 to 18.

First, the subroutine (2) called when the start switch 60 is turned on will be explained with reference to FIG.

-i; In #A-11 of Fig. 6, when it is detected that the start switch 60 is turned on, the flow reaches this step, and it is detected whether the PB mode flag is set or not. When the PB mode flag is not set, the flow branches to #A-1, and when the PI3 mode flag is set, the flow branches to #K-2. Therefore, in this embodiment, if the playback mode is not set in advance, interval playback and program playback cannot be performed, so even if the start switch 60 is turned on by mistake during the recording mode, interval playback and program playback will start. It is possible to prevent this from happening.

Also, if a step similar to the step shown in subroutine O is provided in place of -1 in #, it is possible to immediately start playing the interval playback program by simply turning on the start switch 60 without having to set the playback mode in advance. .

-2 to #; It is determined whether or not the program reproduction mode flag is set, and if it is set, the flow branches to #-13. If not set, the flow branches to #-4.

Here, the flow will be described when the program playback mode flag is not set, that is, when interval playback is performed.

#-4; Determine whether the memory address N is "oooo-1, that is, the track being accessed by head 3-1, is unrecorded. If it is unrecorded, #K-6 must be unrecorded. The flow branches to #■ (-5. First, the flow from #1 to #16 will be explained assuming that the track being accessed by the head 3-1 is unrecorded.

According to this embodiment described below, when the track being accessed by the head 3-1 is other than the 49th or 50th track, the interval playback is performed from the track to the track being accessed by the head 3-1. When it is the 49th or 50th track, only the tracks that have been recorded sequentially from the 1st track will be played back, but if the head 3-1 is moved to the 1st track between #-2 and #-4, If a step of driving the step motor 24 is inserted to access the tracks, only the tracks that have been recorded sequentially from the first track are always reproduced.

Therefore, when the head 3-1 is not accessing the first track but is accessing another track, it is extremely effective for automatically performing interval playback sequentially from the first track to perform a search.

#, -6; Set the automatic track advance flag indicating that interval playback is in progress.

-7 to #: It is determined whether or not the field flag is set, and if it is set, the flow branches to #K-8. If it is set, the flow branches to #■(-9).

#-8; It is determined whether the track that the head 3-1 is accessing is the innermost track by detecting whether N is 50, and it is detected that N is 50. In this case, the flow branches to #K-10, and if 50 is not detected, the flow branches to #K-11.

-9 to #; Indicates whether the track that the head 3-1 is accessing is one track outside the innermost circumference.
The determination is made by detecting whether or not 49.
When 9 is detected, the flow branches to #-10 and when 48 is not detected, the flow branches to #-11.

-10 in #, and in this step, it is determined whether or not the interval time Ti set by executing the subroutine ⊚ is "O". As will be described later, when the interval time Ti is "0", the head 3-1 is programmed in advance according to an external trigger signal.
In this mode, when the interval time Ti is set to "0" for such a mode, the flow is #A-1, and when it is not set to "0", the flow is #A-1.
The flow branches to K-12.

-11 to #; Call subroutine 0, #D-1
The flow shown in ~#D-18 is executed.

When subroutine O is called in subroutine ■, the PB mode flag is set, so the flow branches from #D-2 to #D-9, and at #-4, the track accessed by head 3-1 is determined. When it is determined that a track on the outer circumference side of the frame and one track inner circumference than this track is the inner track of the two tracks on which the frame video signal is recorded, and that the head 3-1 is not accessing the 49th track. Heads 3-1 and 3-2 are #D-
12, #D-13 shifts the head 3-1, 3-2 to the inner circumference by two tracks, and when no determination is made, the head 3-1, 3-2 is shifted inward by one track by #D-13. Further, if a frame video signal is recorded in the track being accessed by the head 3-1, 3-2, the field flag is cleared and the flow moves from #D-19 to #D-14.

#-12; Call subroutine ■#E-1~
The flows shown in #E-13 and #D-14 to #D-19 are executed, and the tracks on the outer circumference side adjacent to the track accessed by the head 3-1 at -4 in # and the outer circumference side by one more track are executed. If frame video signals are recorded on two of the tracks, head 3-1.3-2 is #E-
12, #E-13 shifts the track by two tracks toward the outer circumference; otherwise, #E-13 shifts the track by one track toward the outer circumference.

Also, if a frame video signal is recorded in the accessed track <3-1.3-2, which is the same as -11 in @, the field flag is cleared and the flow moves from #D-19 to #K-13. .

-13 to #; It is determined whether the track that the head 3-1 is accessing is the outermost track by detecting whether the content of register N is 1, and it is detected that it is ■. When it is detected, the flow branches to #-14, and when l is not detected, the flow branches to #-12. Therefore, if the flow branches to #K-12 at #K-8 or #K-9, that is, head 3-1
When the head 3-1 is accessing the 49th track or the 50th track, the head 3-1 is controlled to access the first track by repeating steps of -12 to # and -13 to #.

#1+4; Clears the automatic track feed flag.

As explained above, the flow from #14 to #K-14 is executed, and when the flow branches from #K-4 to #-5, the head 3-1 tracks the track where the video signal is recorded. Tracks on which no video signals are recorded are essentially skipped without being played back.

Furthermore, by executing the flow from #K-4 to #-14, when the flow branches from #-4 to #-5, the two tracks being accessed by heads 3-1 and 3-2 are #I)-1 if a frame video signal is recorded
Since the field flag is cleared in 8,
Frame playback mode is automatically set. Further, when a field video signal is recorded on the track being accessed by the heads 3-1 and 3-2, the field playback mode is automatically set. Therefore, during interval playback, the most appropriate playback mode is automatically set according to the recording method of the video signal.

-5 to #: The interval time Ti set in the subroutine ◎ is fetched from the memory into the register T' of the CPU 40.

-15 to #; Interval time T in the same way as -10 to #
Detects whether i is “0” and if it is “0”, -
If it is not "0", the flow branches to #K-16. Here, the following explanation will be given on the assumption that the external trigger mode is not set.

-16 at #, timer l starts timing operation, and #■(-
Proceed to 18.

-18 to #; It is detected whether or not the timer 1 has clocked for 1 second. If the timer 1 is being counted, the flow branches to -19 to #, and if it is in the middle of counting, the flow branches to #K-20.

-20 to #; It is detected whether the stop switch 61 is turned on, and if it is turned on, the flow branches to #A-1; if it is not turned on, the flow branches to #A-21. Here, when the flow branches to #A-1, steps #A-1 to #A-12 are executed again, so when the stop switch 61 is turned on in the normal state, the flow is #A-1.
The subroutine ■ will be called from step 12.

Below, subroutine (2) will be explained using FIG. 17.

#M-1, detect whether the program playback mode flag is set and if it is not set, #A-1
If set, the flow branches to #M-2.

8M-2; It is detected whether or not the program playback execution flag is set. If it is set, the flow branches to 4M-3; if it is not set, the flow branches to #M-4.

4M-3. Make the contents of register I the same as the contents of register S.

#M-4; Set register S to O and then execute 4M-3.

This subroutine [phase] will be described in more detail in the program playback mode. Below, #K-21 and later will be explained in detail.

#-21,) It is detected whether the rack UP switch 54 is on, and when it is detected that it is on, subroutine (2) is called and the head 3-1.3-2 is shifted to the inner circumferential side. When it is not detected that it is on, the flow branches to #-22.

-22 to #: Detects whether the track DOWN switch 55 is on, and when it is detected that it is on, calls subroutine ■, shifts the heads 3-1 and 3-2 to the outer circumferential side, and turns it on. If it is not detected, the flow branches to #-18.

-19 to #, subtract 1 from T'.

-23 to #; When 1" is 0", -24 to #, T
When ' is not "0", the flow branches to #-16.

Therefore, by executing steps #15 to #K-23 mentioned above, you can update the track during interval playback.
By turning on the switch 54 and the track down switch 55, it is possible to reproduce the video recorded on the track adjacent to the track being reproduced.

In that case, switch 54 or switch 55
By keeping it on, the tracks being played can be automatically updated sequentially according to the track advance speed set in subroutine [F], and it is also possible to easily play back the video several screens earlier during interval playback. I can do it.

Furthermore, in this embodiment, before turning on the switches 54 and 55, when playing back a video recorded on a track adjacent to the track being played back by turning on the track UP switch 54 and the track DOWN switch 55, When the remaining time of the interval time Ti of the track being played in is played back, the flow moves from # -23 to # -24 and is updated to play a new track. As shown by the dotted line,
By jumping the flow to -5 at #, it is possible to reset the interval time T' so that the image updated by the switches 54 and 55 can be reliably observed for a certain period of time.

-24 to #; When updating the track to be played after the interval time T' ends, it is detected whether or not the program playback mode is set, and if it is set, it changes to -3 to #. If not, the flow branches to #-6.

Next, about the routine ◎ that branches when the program playback mode flag is set at -2 in #, the 18th
This will be explained using figures.

#O-1; Detects whether the contents of register S is “0” and when “0” is detected, transfers “0” to #A-1.
When it is detected that this is not the case, the flow branches to #0-2.

As mentioned above, register S stores the start address of the program in the program track memory, and the fact that the contents of register S is "O" means that no program is stored in the program track memory. When the value is 0'', the process returns to A in FIG.

#O-2, detects whether the contents of register I are "O" and when "0" is detected, goes to #O-3; when it is detected that it is not "O" The flow branches to #O-3.

As mentioned above, register I stores the address of the track memory where the track number to be played next is stored when program playback is executed.
When executing program playback, as shown in #0-14 below, 1 is subtracted every time one step program playback is executed.

Therefore, the reason why the flow branches to #0-2 and register I is detected as "O" is because the program is set and register S is not "0", and the program playback steps have been executed. It shows that In other words, when the program playback is executed in - way, #o
-3, the flow branches to #o-5 while the program playback is executed one way.

#0-37 Takes the interval time Ti set in subroutine ■ and sets the interval time Ti to “0”
If it is "0", the flow returns from routine ◎ to #A-1 and ends the program playback operation.

Therefore, in the external trigger mode set by setting the interval time to "O", the program playback operation is stopped after the program playback has been executed one time.

Also, during normal program playback when interval time T1 is set to something other than "o", #
The flow moves to O-4.

#O-4; Write the contents of register S to register I.

Program operation is started again.

#O-5; Enter the data (■) at the address of the program track memory set in register I (the data written to the address set in register I of the program track memory is shown in parentheses). read out.

#O-6; If data (I) is subtracted from N indicating the track number currently being accessed by head 3-1 and is less than "0", then #O-7
If it is smaller, the flow branches to #0-8.

#O-7; Clear the field flag. This set is for prohibiting head feeding in the frame mode like #D-8.

#0-8. Heads 3-1 and 3-2 are shifted by one track in the outer circumferential direction.

#O-9; Detects whether the data (1) is equal to N indicating the track number that the head 3-1 is accessing. If they are equal, the data is changed to #0-10. If not, the data is smaller than N indicating the track number. If (I) is larger, the flow branches to #0-11.

#0-10. Head 3-1.3-2 in the inner circumferential direction 1
Frame playback and field playback are automatically performed depending on whether the video signal recorded from the start is a frame video signal or a field video signal.

Furthermore, by repeating #O-6 to #0-10, Herad 3
-1 is controlled to access the track programmed in the program track memory.

#0-14; Subtract 1 from Leinster ■.

#O-+5; The program playback execution flag is set. With this step, the flow can be branched by determining whether the program reproduction mode flag is set at -24 in #.

The flow then jumps to #-15.

Therefore, when #K-3 branches to routine ◎, it is first determined whether or not a playback program is actually set, and then it is determined whether or not the external trigger mode is set, and the external trigger mode is set. When the program is running, the program is executed only one way, and at other times the program is played repeatedly.

Next, a flow when the external trigger mode is set will be explained. When the external trigger mode is set, the flow branches from #K715 to #K-17.

#K-17'; Detects whether the printer connected as an external device is busy (executing a print operation) or not, and if it is busy, sends a message to #A-1; if it is not busy, sends a message to #. The flow branches at 18'.

#K-18'; Sends a print start signal to the printer as an external device. The print start signal is executed by setting the signal level of a terminal connected to the printer to H level.

#19'; Waiting for 150m5ec #K-2
0'; When the printer is busy, the flow branches to #-21', and when it is not busy, the flow branches to #-24.

#K-21'; It is detected whether the stop switch 61 is turned on or not. If it is not turned on, the flow goes to #-20', and when it is turned on, the flow returns to #A-1.

If the printer connected as an external device is busy when executing steps #K-17' to #K-21' above, the flow returns to #A-1 as described above, and other switches are activated again. The flow shown in FIG. 16 is repeated until the switch is turned on. If the start switch 60 is turned on again while repeating the flow shown in FIG. 16, the above-described flow will be repeated and step 117' will be executed again.

In addition, when a printer is not connected as an external device, the printer 13' shown in FIG.
The terminal into which the signal from the busy signal output terminal is input becomes an oven and becomes H level. Therefore, if a device such as a printer is not connected even though external 1 to rigging mode is set, the track being accessed by head 3-1.3-2 will continue to be played. Tracks are not updated.

7 Also, if a printer is connected as an external device and the printer is not busy, #K-17' to #
When the flow advances to K -18', send the print start signal to the printer and then change # to 1 shown in -19.
If printer operation is started after waiting for 50m5pc and the printer becomes busy, repeat #120' and #121' until printer operation ends or the stop switch 60 is turned on. , when the printer operation is finished the flow goes from # to 20' to #
The program branches to -24 and determines whether program playback is set by detecting whether the program playback mode flag is set. If program playback is set here, the flow branches to #-3 mentioned above, and if program playback is not set, #
Branch to K-6. Further, when the stop switch 60 is turned on, the flow is as described above.

Further, if the external trigger mode is selected when program playback is set, the program playback operation is stopped after the program playback has been executed three times as described in #O-3.

Further, according to this embodiment, even if the external trigger mode is selected and program playback is not set, since -10 is set in #, the head 3 -
1. When the playback is performed sequentially from the accessed track 3-2 to the final track, the playback operation is stopped.

Therefore, in external trigger mode, regardless of whether programmed playback is set or not, the playback operation stops after the normal playback is performed, so the printer is used as a device that performs external triggers. When using , only −-way printing is performed.

On the other hand, in modes other than external trigger mode, even if program playback is set or not, playback starts again from the beginning after playback is performed in a predetermined order. will be held. Therefore, when such a playback device is used in a mode other than the external trigger mode, so-called endless playback can be performed because playback is performed repeatedly in a predetermined order.

Further, although a printer is shown as the external trigger device in this embodiment, it may be a device having an electric transmission function, or any other device as long as it processes a reproduced signal.

Next, the case of setting an ID will be explained.

When the 10 key switches 63 to 72 are turned on in the flow (2), the flow branches to the subroutine (2) shown in FIG.

#R-1, #R if the PB mode flag is set
The process branches to -10 and returns to the flowchart (2). Therefore, in a mode other than the recording mode, even if the 10 key is turned on, virtually nothing is executed in this subroutine. If the PB mode flag is not set, that is, if it is in recording mode, the flow branches from #R-1 to #R-2.

#R-2; Here, it is determined whether the ID setting mode, that is, the ID is superimposed on the video signal and the mode is being monitored. The method for setting this mode will be described in detail with reference to FIG. 20. If this mode is not selected, the process branches to #R-10 and returns to #A-1 in the flowchart shown in FIG. If this mode is selected, the process branches to #R-3.

#R-3: The CPU 40 retrieves the set position from the register P of the RAM 27 for storing the set position indicating where on the monitor the ID set here is to be displayed.
is read, and data corresponding to the switch turned on among the 10 key switches 63 to 72 is written to an address in the RAM 27 corresponding to the set position. Then the CPU
40 controls the character generator 84 to display the data on the monitor B according to the read set position.

#R-4: Here, wait until the 10 key switches 63 to 72 are turned off once. If the switches that were turned on are turned off, the flow advances to #R-5.

#R-5, here, the setting positions of data other than the date in the ID are 11 points from O to 10 as shown in Fig. 21, so if register P is equal to 10, then Branch to #R-6, otherwise branch to #R-7.

#R-6; Here, register P is set to 0, and D
The setting position of ATA is initialized.

#R-7; Here, 1 is added to the value of register P and D
The ATA setting position moves to the next setting position.

#R-7-1; Data at the position stored in register P blinks (blinks).

#R-8; In this step, it is determined whether the 10 key switches 63 to 72 are turned on, and if they are turned on, the process branches to #R-3 and the settings are made using the 10 key switches according to the flow described above. I was
D is displayed on the motor 13.

If it is not turned on, the process branches to #R-9.

#R-9; Here, it is determined whether any switches other than the 10 key switches 63 to 72 are turned on, and if they are not turned on, the process branches to R-8. If it is turned on, it branches to #R-11.

#R-9-1; Stop blinking the ID displayed on the monitor. Flow proceeds to #R-10.

#R-11; Here, register P at the ID setting position
Set 0 to #R-9-1 and initialize the ID setting position.
Proceed to.

#R-10; Return to the flow of ■.

As explained above, when the PB mode flag is not set and the ID setting mode, that is, the mode in which the set ID can be monitored, the lo key switch 6
Each time a switch 3 to 72 is turned on, the CPU 40 controls the character generator 84 to generate data at a position determined by the register P.

Next, the ID switch 73 will be explained.

When the switch 73 is turned on, the subroutine ◎ shown in FIG. 20 is called from the flow shown in . Here, subroutine ◎ will be explained.

#Q-1; Here, determine whether or not the PB mode flag is set, and if it is set, #Q-2
Otherwise, the process branches to #Q-7.

#Q-2; Here, check whether it is in ID display mode or not.
That is, it is determined whether the mode is such that the ID is output on the monitor superimposed on the video signal. If you are in ID display mode, go to #Q-4, otherwise go to #Q-4.
Branch to Q-3.

#Q-3: Here, the CPU 4Q controls the character generator 84 to stop displaying I[ outputted from the generator 84. From here, the flow advances to #Q-6.

#Q-4, here, the CPU 40 imports the reproduced ID from the RAM 27, and the flow is #Q-5.
Proceed to.

#Q-5; Here, the CPU 40 controls the character generator 84 based on the reproduced TD, and causes the character generator 84 to output the reproduction ID as a character pattern as shown in FIG. 21(a). The flow then proceeds to #Q-6.

#Q-6; Here, if the switch 73 is turned on, the process waits; if it is turned off, the flow proceeds to the next step and returns to the flow of (2).

#Q-7; When the PB mode flag is not set and the recording mode is selected, it is determined whether the mode is the ID setting mode or not. That is, if the ID is in a mode in which the character generator 84 outputs a character pattern superimposed on the video signal, the flow advances to #Q-9. Otherwise, the flow advances to #Q-8.

#Q-8; Here, if it is likely to be determined whether or not the mode in which the character "ID" is output by the character generator 84 is determined, go to #Q-10; otherwise, go to #Q-
The flow advances to step 11.

#Q-9; In this step, the CPU 40 controls the character generator 84 to stop displaying the ID, and generates a two-character pattern "ID" by the character generator 84 as shown in FIG. 21(b). to enter the “ID” character display mode. The flow then proceeds to #Q-6. That is, when the ID switch 73 is turned on in the ID setting mode, the "ID" character display mode is set.

#Q-10; - In this step, the CPU 40 controls the character generator 84 to stop displaying all character patterns as shown in FIG. 21(c). Then the flow is #Q-6
Proceed to.

#Q-11: If the flow reaches this step, ID
Neither setting mode nor "ID" character display mode,
That is, since the mode is set to stop displaying the ID on the monitor, the CPU 40 takes in the set ID from the RAM 27, controls the character generator 84, and uses the set ID as a character pattern as shown in FIG. 21(a). character generator 84
Make more output. That is, the ID setting mode is set by this step. The flow then proceeds to #Q-6.

As explained above, each time the ID switch 73 is turned on, the I
The display format of D will be rewritten.

In other words, in the playback mode, the [) switch 73
ID display mode in which the playback ID DAT is superimposed on the video signal and monitored every time the playback ID DAT is turned on, and the playback ID
The ID non-display mode in which no data is output will be repeated. Specifically, I shown in FIG. 21(a)
The ID non-display mode shown in D display mode (C) is repeated. In addition, when in recording mode, there is an ID setting mode that displays all IDs to be set, and an “ID setting mode” that displays all IDs to be set.
Each time the ID switch 73 is turned on, the "ID" character display mode in which only characters are displayed and the mode in which the ID is not displayed on the monitor are switched repeatedly. Specifically, as shown in FIG. (a).

The modes shown in (b) and (C) will be switched repeatedly. The ID display in the recording mode will be further described below. FIG. 21(a) in recording mode.

When recording a video signal in the mode shown in (b), the ID is modulated with the video signal in #N-5 and #N-6 in FIG. 12, is modulated into DPS, and is further frequency-multiplexed with the video signal and recorded. It turns out. Also, Figure 20 (C)
When recording a video signal in this mode, I
D data is not recorded. However, DATA indicating whether it is inside or outside the frame or field recording is always sent together with the video signal.

That is, in this embodiment, depending on the number of times the ID switch is pressed, the monitor 1 is
It is possible to switch the display related to ID 3.

In addition, in this embodiment, in the recording mode in which the ID is recorded together with the video signal, there is an ID setting mode in which the display shown in FIG. 21(a) is performed, and in the ID setting mode in which the display shown in FIG.
The reason for providing these two display modes will be explained below.
Although it is possible to set the year, month, day, and 11-digit number, if you try to display all of the rD information as shown in Figure 21(a), it will occupy a considerable area on the screen of the monitor 13. Therefore, there is a problem that the viewing of the image may be obstructed, so a display mode as shown in FIG. 21(b) is provided to solve this problem.

Next, a method of displaying the reproduced ID in the reproduction mode will be explained. That is, in the recording mode, the image shown in FIG. 21 (
A display method for reproducing the ID recorded together with the video signal when the modes shown in a) and (b) are set by the ID switch 73 will be described. In the playback mode, when the head is moved to a new track, the ID recorded on that track is displayed on the monitor 13.
will be played on. This is done by demodulating the ID reproduced by the data demodulator 12 shown in FIG. 1, reading this output by the CPU 40, and further driving the character generator 84. The ID read by the CPU 40 is held in the RAM 27 by the CPU 40. Regarding the display of such ID, see Figure 21 Ca'
), but in this embodiment, the RAM 27
The following I) and II) are the display modes for characters held in
It has two modes shown below.

I) A first display mode that is displayed when an ID recorded in which only the year, month, and date are set as ID data and no other data is set is played back.

n) When playing back an ID in which the year, month, date and other numerical data are set as ID DATA, the second
Display mode - mode.

FIG. 22(a) shows the ID display in (2).

The iD display in (2) is shown in FIG. 22(b).

That is, for ■), only the year, month, and day are displayed at the bottom right of the monitor, and for ■), the year, month, date and other data are displayed at the bottom right of the monitor. Therefore, the ID information is always displayed in the lower right corner of the monitor screen, so that it can be prevented from interfering with the video signal as much as possible. Further, in this embodiment, the display is displayed in the lower right corner of the screen, but it may be displayed anywhere as long as it is in the corner of the screen.

In order to execute this operation, after reading the output signal of the data demodulator 12 shown in FIG.
All you have to do is generate the characters after confirming that all days and evenings outside the daily income are not set. In other words, above I), n
), the CPU 40
controls character generator 84.

Also, if it is determined that data other than the date is not the DATA recorded by this device, the 22nd
The display shown in Figure (b) is performed.

This is ok (known check code ID DATA
Things that can be determined by recording them as follows:
The case where the year, month, and day are set as D will be explained.

In the flow (2), when the year setting switch 74 is turned on, the flow jumps to the subroutine (2) shown in FIG.

#S-1; If the PB mode flag is set here, the flow advances to #5-14 and returns to the flow of (2). If not set, proceed to #S-2.

#S-2; At this point, enter ID setting mode, that is, video (1
? It is determined whether the mode is to superimpose ID data on a signal and output it to a monitor or printer. If it is not in this mode, proceed to #5-14 and return to the flow of (2). If you are in this mode, #S-3
Proceed to.

#S-3, Here, the number in the tenth digit of the year setting position on the monitor 13 blinks. The blinking of the number in the tenth digit of the year setting position is the character in the position shown in ■ in Figure 24 (a). This is accomplished by CPU 40 controlling character generator 84 to generate or not generate a character at this location.

This is done by well-known interrupt processing. The flow then proceeds to #S-4.

#S-4; At this point, wait until the switch 74 is turned off. When switch 74 is turned off, the flow is #S-
Proceed to step 5.

#S-5; Here, it is determined whether the 10 key switches 63 to 72 are turned on. If the 10 key switch is on, the flow advances to #S-6. If not, proceed to #5-12.

#S-6; Here, the CPU 40 writes the input data from the lO main key switch to the RAM 27, and controls the character generator 84 to generate a character pattern at the year setting position shown as ■ in FIG. 24(a). generate. The flow then proceeds to #S-7.

@S-7; Blink the first digit of the year setting position. This means that the characters at the position shown in Figure 24 (■) blink.

Blinking is performed by CPU 40 controlling character generator 84. The flow proceeds to #S-8.

#S-8: Wait until the 10 key switch is turned off. When the 10 key switch is turned off, the flow is #S
Proceed to -9.

#S-9: It is determined whether the 10 key switch is turned on or not. If turned on, the flow is #5
-10, otherwise go to #5-13.

#5-10; C if the 10 key switch is turned on
The PU 40 writes the data inputted by the 10-key switch to the RAM 27, and controls the character generator 84 to generate a character pattern at the position shown in ■ in FIG. 24(a), which is the first digit of the year setting position. let Then the flow is #
Proceed to 5-11.

#5-11; The CPU 40 controls the character generator 84 to stop the character from blinking at the year setting position. This allows the user to know that the year setting has been completed. Flow proceeds to #5-14.

#5-12. If the 10 key switch is not turned on in #S-5, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, F17- branches to #S-5 and #S-5゜#
Repeat steps 5-12, and if switches other than the 10 key are turned on, proceed to #5-11.

#5-13; Here, it is determined whether any switches other than the 10 key are turned on. If it is not turned on, the flow branches to #S-9, and if it is turned on, the flow branches to #5-11. Therefore, until a switch other than the 10 key is turned on, #S-9. By repeating steps #5-13, the characters at the year setting position continue to blink, prompting the user to set the year using the 10-key switch.

#5-14; If the PB mode flag is set, if the ID setting mode is selected, and if the blinking is stopped by #S-11, the flow returns to ① by this step.

As explained above, when the year setting switch 74 is turned on, the number in the 10th digit 1flr of the year setting position starts blinking, thereby informing the operator of the position where the data is to be set. Here, by inputting numbers using the 10-key switch, the data input at the blinking position is generated as a character pattern by the character generator 84, and the CPU holds the data in the RAM 27. When the setting of the IO place digit is completed, the number in the first digit position will start blinking, and in the same way, D will be set at this position.
ATA settings are performed. Here, when the setting of the first digit is completed, the year setting mode ends and the process returns to the flow shown in ■, but it is also possible to proceed to the flow shown in ■ and enter the month setting mode.

Next, the setting of the month's DATA will be described in detail with reference to subroutine (2) shown in FIG.

In the flow of (2), when the switch 75 is turned on, subroutine (2) is called and the month DATA setting mode is entered.

#T-1; If the PB mode flag is set here, the flow advances to #T-16 and returns to the flow of (2).

If the PB mode flag is not set, the flow advances to #T-2.

#T-2; Here, it is determined whether the mode is an ID setting mode, that is, a mode in which ID data is superimposed on a video signal and output to a monitor or printer. If it is not in this mode, proceed to #T-16 and return to the flow of (2). If this mode is selected, proceed to #1'-3.

#T-3: Now blink the 10th digit number at the column setting position on the monitor. The blinking of the 10th digit number at the column setting position means that the character at the position shown by ■ in FIG. 24(a) blinks. This is accomplished by the CPU 40 controlling the character generator 84 to generate or not generate characters. The flow then proceeds to #T-4.

#T-4; 'Here, wait until the row setting switch 75 is turned off. When the switch 75 is turned off, the flow advances to #T-5.

#T-5; Here, it is determined whether the lO key switches 63 to 72 are turned on. If the 10 key switch is on, the flow proceeds to #T-6; otherwise, the flow proceeds to #T-13.

#T-6; Here, it is determined whether the data input by the lO main key switch is 2 or more. If the number is 2 or more, the flow proceeds to #T-14, otherwise the flow proceeds to #T-7. In other words, in the case of column settings, the flow is branched according to the number set in this step in order to accept the first digit number only when the first number input is "1" or "0". .

#T-7; Here, the CPU 40 stores the input data in the RAM.
27 and controls the character generator 84 to write the character pattern to the position shown in ■ in FIG. 24(a), that is, #.
It is generated at the position blinked at T-3. ``The flow advances to #T-8.

#T-8; Here, blink the first digit number at the month setting position. This means that the characters in the place indicated by ■ in FIG. 24(a) blink. The flow is #T-
Proceed to step 9.

#T-9: Wait until the 10 key switch is turned off. When the 10 key switch is turned off, the flow advances to #T-10.

#T-10; Here, it is determined whether the 10 key switch is turned on. If it is turned on, the flow advances to #T-11; otherwise, the flow advances to #T-15.

, #T-11: Here, the CPU 40 writes the data input by the 10 key switch in #T-5 or #T-10 to the RAM 27, and writes it to the position shown in Fig. 24 (■), which is the first digit of the month setting position. The character generator 84 is controlled to generate a character pattern, and then the flow is #T-12.
Go ahead. In addition, when branching to this step from #T-14, by executing #T-14゜#T-11,
At T-5, the data input by the lO key switch is displayed in the first digit, and "0" is displayed in the tenth digit.

#T-12, stop blinking the data at the month setting position,
Displays that month setting is completed.

Flow proceeds to #T-16.

#T-13; This step includes 1 in #T-5.
Branches if the 0 key switch is not turned on. Here, it is determined whether a switch other than the IO primary key is turned on. If it is not turned on, it branches to #T-5, and if it is turned on, it branches to #T-12. That is 10
#T-5. until the key switch or other switch is turned on. #T
-13 is repeated, and if the 10th key switch is turned on, the flow branches to #T-6, and if any other than the 10th key switch is turned on, the flow branches to #T-12.

#T-14; The process branches to this step when it is determined in #T-6 that the input data is "2" or more. Here, the CPU 40 stores data “0” in the RAM 27.
” and enter the character generator 8 in the 10th digit of the month setting position.
4 to generate a character pattern "0". The flow advances to #T-11.

#T-15, here it is determined whether a switch other than the lO primary key is turned on. # if not turned on
Branches to T-10, #T-12 if turned on
Branch into.

@T-16: Return to the flow of ■.

As explained above, when the switch 75 is turned on, the 10th digit at the month setting position first blinks, thereby first indicating the position at which data to be input using the 10 key switch is to be set. If two or more pieces of data are input here, "0" is automatically set in the 10th digit and the input data is automatically set in the 1st digit. Of course, if there is an input of 1 or less, 10
Needless to say, the next blink position that is input to the first digit moves to the first digit, and the data input next by the IO primary key is set to the first digit. Therefore, according to this embodiment, when setting the month, it is possible to easily set the month by taking advantage of the fact that 2 or more is never set in the 10th digit.

Further, in #T-3, only the 10th digit is blinked here, but the 10th digit and the 1st digit may be blinked together.

Furthermore, when the setting of the next first digit is completed, the process returns to the flow shown in (2) in this example, but it is also possible to proceed to the subroutine (2) shown in FIG. 26 and enter the day setting mode.

Next, the day data setting will be described in detail with reference to FIG. When the switch 76 is turned on in the flow (2), the day data setting mode is called and the flow jumps to (2).

#U-1; If the PB mode flag is set here, the flow advances to #U-16 and returns to the flow of (2). #U if the PB mode flag is not set
Proceed to -2.

#U-2; Here, ID data SET mode,
That is, it is determined whether the mode is such that ID data is superimposed on a video signal and output to a monitor or printer. If it is not in this mode, proceed to #U-16 and return to the flow of (2). If this mode is selected, proceed to #U-3.

#U-3, Here, blinking the number in the 10th digit of the old setting position on the monitor. Blinking the number in the 10th digit of the column setting position means that the character in the position shown in ■ in Figure 24 (a) It means to blink. This is accomplished by the CPU 40 controlling the character generator 84 to generate or not generate characters.

The flow then proceeds to #U-4.

#U-4; At this point, wait until the date setting switch 76 is turned off. When switch 76 is turned off, the flow advances to #U-5.

#U-5; Here, it is determined whether the 10 key switches 63 to 72 are turned on. If the 10 key switch is on, the flow advances to #U-6; otherwise, the flow advances to #U-13.

#U-6; Here, it is determined by the 10 key switch whether the input data is 4 or more. If it is 4 or more, the flow goes to #U-14, otherwise it goes to #U-14.
Proceed to U-7. In other words, in the case of column settings, it will be 1 only if the first number entered is “3”, “2”, “1”, or “0”.
The flow is branched according to the number set in this step in order to add the number in the digit.

#U-7; Here, the CPU 40 sends the input data to RA
M27 is written and the character generator 84 is controlled to generate a character pattern at the position shown at .largecircle. in FIG. 21(a), that is, at the blinking position at #U-3.

The flow proceeds to #U-8.

#U-8; Here, blink the first digit number at the old setting position. This means that the characters at the positions indicated by ■ in FIG. 24(a) blink. Flow is #U-9
Proceed to.

#U-9: At this point, wait until the lO main key switch is turned off. When the IO primary key switch is turned off, the flow advances to #U-10.

#U-10; Here, it is determined whether the IO main key switch is turned on. If it is turned on, the flow advances to #U-11; otherwise, the flow advances to #U-15.

#U-11; At this, the CPU 40 writes the data inputted by the 10 key switch at #U-5 or #-10 into the RAM 27, and writes a character at the position shown in Figure 24 ■, which is the first digit of the old setting position. The generator 84 is controlled to generate a character pattern, and then the flow is #U-12
Proceed to. In addition, when branching to this step from #U-14, by executing #[J-14° #U-11, the data input by the lO main key switch in #U-5 will be changed to the first digit. is displayed, and “0” is displayed in the 10th digit.

#U-12: Stops blinking of the data at the old setting position and displays that the mill setting is completed.

Flow proceeds to #U-16.

#U-13; This step includes 1 in #U-5.
．． Branches if the 0 key switch is not turned on.

Here, it is determined whether any switches other than the IO key are turned on.

If it is not turned on, it branches to #U-5, and if it is turned on, it branches to #U-12. That is, # until the IO main key switch or other switch is turned on.
U-5. The flow of #U-13 is repeated, and if the IO main key switch is turned on, the flow branches to #'r-6, and if any other than the 10 key switch is turned on, the flow branches to #U-12.

#U-14, . The process branches to this step when it is determined in #U-6 that the input data is "4" or more. Here, the CPU 40 stores data in the RAM 27.
0" is written, and the character generator 84 is controlled to generate a character pattern "0" in the 10th digit of the column setting position. The flow advances to #U-11.

#U-+s; Here, it is determined whether a switch other than the lO primary key is turned on. If it is not turned on, branch to #U-10; if it is turned on, it branches to #U-10.
Branches into 12.

#U-1-6; Return to the flow of ■.

As explained above, when the switch 76 is turned on, the 10th digit at the date setting position first blinks, thereby first indicating the position where the data to be input using the 10 key switch is to be set. If 4 or more data is entered here, "0" will be automatically set in the 10th digit and the input data will be set in the 1st digit. Of course, if 3 or less is entered 10 for
Needless to say, the next blinking position that is input in the 1st digit moves to the 1st digit, and the next data input using the 1O key is set to the 1st digit. Therefore, according to this embodiment, when setting the day, it is possible to easily set the day by taking advantage of the fact that 4 or more is never set in the 10th digit.

Further, in #U-3, only the 10th digit is blinked here, but the 10th digit and the 1st digit may be blinked together.

In the embodiment described above, the display is blinked to indicate the setting position, but the setting position may be indicated by other methods such as changing the brightness or changing the color.

Next, the erase sequence will be explained. When erasing data, the erase execution switch 78 and erase standby switch 77 shown in FIG. 1 are used. That is, when erasing is to be executed, the switch 77 is used to put the data into an erase standby state in advance, and then the erasure is executed only when the erase execution switch 78 is turned on. Furthermore, there are two modes for erasing: a mode in which a plurality of tracks are continuously erased, and a mode in which only a single track is erased. Hereinafter, the above operation will be described in detail based on the flowchart (2) shown in FIG. In the flowchart A in FIG. 1, when the switch 77 is turned on, the flow calls subroutine (2) and proceeds to #V-1. At this point, the standby state for erasing is set, but at this time, the buffer memory E for storing the number of erased tracks contains “
FF" is set. Also, the track number accessed by the head 3-1 on the two-digit 7-segment LED 25 that displays the track number is approximately 2.
It performs a blinking operation that repeatedly turns on and off at a frequency of Hz. In other words, the track number display LED blinks (2
Hz period) allows the operator to confirm that the erase standby mode has been set.

In other words, compared to a method that uses a dedicated display element to indicate that the erase standby state is in effect, the method of this embodiment not only eliminates the need to use such a dedicated display element, but also displays the track number. By changing the display format of the display, the standby state for erasing is displayed, making it easier to recognize the track number that is about to be erased. In addition, in this embodiment, 7 segments L
Although the standby state for erasure is indicated by blinking the display of the ED25, it is of course possible to use other liquid crystals as the display element, and in addition to blinking, the color and brightness of the display may be changed. Various methods are possible, such as changing the form of displayed characters.

In addition, if there is a display that displays other information than the track number, such as the number of free tracks, the display format of the display can be changed as described above to enable the erase standby state. It may be possible to display a certain thing.

The flow then proceeds to #v-2.

#V-2; Here, it is determined whether or not the PB mode flag is set, and if it is set, the flow advances to #■-4; otherwise, it is determined that the switch 77 is turned off. After confirmation, the flow advances to #v-3.

#V-3; Here, the subroutine ◎ for setting the playback mode described above is called, the playback mode is set, and the flow advances to #v-4. Therefore, when the erase standby switch 77 is turned on, #V- 2. By executing #V-3, the playback mode is set and the erase standby state is set.

#V-4; Here, it is determined whether the switch 78, that is, the erase execution switch is turned on. $V-4-1 if it is on, #V-1 if not
The flow advances to step 5.

#V-4-1; Here, the branch destination of this step is determined by a switch that is prepared in advance in the case (not shown) of the magnetic sheet 1 and that determines the presence or absence of a claw. In other words, this claw has the function of preventing accidental erasure, and if it is broken off, it is promised in advance not to erase the data. Therefore, if the accidental erasure prevention is set, the flow advances to #V-18. If not set, the flow advances to #■-5.

#V-5: In this step, it is determined whether the value set in the buffer memory E (hereinafter referred to as E) for storing the number of erased tracks is "O". The buffer memory E is previously set to "FF" in #V-1, but the setting value can be changed in #V-15, which will be described later. Here, if the value set in buffer memory E is "O", the flow is #V-1
If not, the flow proceeds to #V-5-1. Next, #v-5-1 will be explained.

#V-5-1; In this step, it is determined whether the value set in the buffer memory E is "FF". If it is "FF", the flow proceeds to #v-6, and if not "FF", the flow proceeds to #V-5-2.

@V-5-2; Set the field flag and set the field playback mode.

The flow proceeds to #U-6.

#V-6, here, the blinking of the 7-segment LED 25 that displays the track number is set in #V-1.
Hz to a fast cycle of 5 Hz. In addition, when performing continuous track erasure, the set track number is displayed on the 7-segment LED 25 instead of the track number being accessed by the head 3-1 in #V-17 described later. Even #V
By executing -6, the 7-segment LED 25 is automatically switched to display the track number. Therefore, the user can confirm which track is currently being erased during continuous track erasing.

#V-7; , :: Here, the CPU 40 controls the erase signal generator 85 to generate an erase signal, and erase is executed. In addition, when performing erasing, switch 2 shown in Fig. 1 is pressed.
, the switch 3 is controlled to connect at least one of the heads 3-1, 3-2 to a recording amplifier. Here, if the field flag is set, that is, in the field playback mode, the erase current flows only to the head 3-1 shown in FIG. 1 that is playing, and l tracks are erased. When the field flag is cleared, that is, when frame playback is selected, an erase current flows simultaneously to both heads 3-1 and 3-2 shown in Figure 1.
The video signal for one frame's worth of tracks, in other words, for two adjacent tracks, is erased.

Note that in this embodiment, erasure in frame mode is executed only when the flow advances from #V-5-1 to #v-6 without passing through #V-5-2. There is. In other words, in #V-5-1, the value of buffer memory E is “FF”.
”, that is, when the continuous erase mode, which will be described later, is not selected.

#V-8; Wait until erasing is completed.

When erasing is completed, the flow advances to #V-8-1.

#V-8-1; Here, it is determined whether E is equal to "FF". If it is equal to “FF”, it is single erase mode, so the flow goes to #V-18, otherwise, continuous track erase is set, so #V-
Proceed to step 9.

#V-9; Here, the value of buffer memory E is subtracted by 1. Flow proceeds to #V-10.

#V-xo+ In this step, it is determined whether the value of the buffer memory E is greater than 0 or not.

That is, the number of tracks to be erased when continuous track erasure is set is detected, and if it is greater than 0, the flow proceeds to #V-11; otherwise, it is assumed that continuous track erasure has ended. Proceed to #V-18.

#V-11; In this step, it is determined whether the stop switch 61 is turned on. If it is turned on, the flow branches to #V-18, and if it is not turned on, the flow proceeds to #V-12. That is, the continuous erasing mode, which will be described later, is selected, and if the stop switch 61 is operated while this mode is being executed, the continuous erasing can be interrupted. Flow then proceeds to #V-12.

#V-12: In this step, it is determined whether the track number N in the buffer memory is 50 or more, that is, whether the track being accessed by the head 3-1 is the final track. If so, the flow is #V
If it is not likely to proceed to -18 and end the erase operation, #
Proceed to V-13.

@V-13; By executing this step, the track position accessed by the heads 3-1, 3-2 moves one track toward the inner circumference. Also head 3-
1. With the movement of 3-2, N+1 is set to N in the track number memory. Then the flow is #V-5-
Branches into 2.

Therefore, when continuously erasing tracks, #V-5-2 to #V-1 are used until the stop switch 61 is turned on or until the innermost track is erased.
3 (7) 70- until the value of the buffer memory E becomes O, that is, until erasing of the set number of tracks is completed (repeat).

Next, the flow after #V-15 for setting the continuous erase mode executed as described above will be explained.

#V-15; 10 shown in 63 to 72 in Figure 1
It is determined whether any of the key switches is turned on or not. If it is turned on, the flow proceeds to #V-16; if not, the flow proceeds to #V-15-1.

#V-16; In this step, the continuous track erase mode will be set. In other words, the number input using the 10 key switches 63 to 72 becomes the number of tracks on which continuous erasure is to be performed. In the erase track number buffer E, the numerical value of the turned-on 10 key is set in the 1's digit. Flow then proceeds to #V-17.

#V-17; 7 segment L in this step
The value of E is displayed on ED25. This situation will be explained with reference to FIG. 28. In #V-15, the value of the first 10 key switch turned on is set to the 1 digit of E (#V-15).
16) and is displayed at the 1's digit of the LED 25 in this step, as shown in FIG. 25(a). Here, before reaching the display shown in FIG. 22(a), the track number is displayed on the display and is blinking.

Further, F set to E is displayed as "0". In addition, the value displayed on the display is 2Hz in #V-1.
Since the blinking operation continues to be repeated, the display "C/" shown in FIG. 25(a) will blink. The flow then proceeds to #V-17-1.

@V-17-1; At this point, wait until the 10 key switch is turned off. When turned off, the flow is @V-15
Proceed to -1.

#V-15-1; Erase standby switch 7 here
7 is turned on. If it is turned on, the flow proceeds to #V-18, and if it is not turned on, the flow proceeds to @V-15-2.

That is, by turning on the erase standby switch 77, the erase standby state set in #V-1 is automatically canceled by turning on the switch 77 again and in the steps after #V-18. Therefore, there is no need to provide a dedicated release switch.

#V-15-2; : Iron, switch 78 and io
Determine whether any switch other than the key is turned on. If it is turned on, the flow branches to #V-18, and if it is not turned on, the flow branches to #v-4.

In other words, the erase standby state is automatically canceled by turning on any switch other than the 10 key in steps #V-18 and subsequent steps. Therefore, there is no need to provide a dedicated release switch. Therefore, there is no need to go out of your way to provide a separate switch. Above #V-
If you pass steps 15-1 and #V-15-2 with No, you will have to repeat the steps described above from #v-4 onwards, but the 7-segment LED 25 will already indicate "DI" as shown in FIG. The operation when executing steps after #v-4 while displaying will be explained.

When the IO main key switch is turned on in #V-15, the numerical value input by the switch in #V-16 is set to the 1st place in the buffer memory E, and the number that was previously set in the 1st place is stored in the buffer memory E. The number set in the 10th place disappears.

For example, if the "5" key of the 10 key switches is turned on, #V-16. #V
-17, the display shown in FIG. 28(b) is displayed on the 7-segment LED 25. Of course, the value set in the buffer memory E in this case is 15.

Next, when a good number "2" is input to the 10-key switch, the display shown in FIG. 25(C) is displayed. The above table shows the display performed by the LED 25 when 1, 5.2 of the 10 key switches are turned on in order in the erase standby state. Furthermore, the displayed numerical value matches the value set in E as it is. In other words, if a value of "2" or more is set using the lO key switch, this is equivalent to selecting the continuous erase mode.
Further, the set value becomes the number of tracks on which continuous erasing is performed. This situation can be seen in #V in the flow description above.
If the value of the buffer memory E is greater than O at -10, the flow proceeds to #V-11, otherwise branches to #V-18, and if the track number N is smaller than 50, the flow proceeds to #V-11. UP L the track at 13
Step #V-5-2+: Branching and executing steps #V-6 and subsequent steps perform continuous erasure.

In other words, in #V-II, unless the stop switch 61 is turned on, until the value of E becomes equal to 0 or the innermost track No. 50 is erased,
Erasing will be performed continuously.

Then after performing the steps described above run #
V-18 to #V-20 will be explained.

#V-18; , :, , :, 7 segment LED
25 will stop blinking and track No. N will be displayed on the display. The flow then reaches #V-19. In other words, this step erase standby state is released.

#V-19; If the switch 77 is turned on, the process waits; if the switch 77 is turned off, the process proceeds to #■-20.

#v-zo; At this point, the flow returns to the flow shown in A of FIG.

As explained above, when performing erasing, in this embodiment there are two modes: a mode in which erasing is performed only once, a mode in which it is performed continuously, and a mode in which erasing is performed after specifying the number of tracks to be erased consecutively in advance. However, for erasing when the number of erase tracks is not set using the 10-key switch, the value of E in #V-5-1 is set to "F" in advance.
F”, it moves to #v-6 without going through #V-5-2. Therefore, if the field flag is cleared in the erase standby state, it is set in frame mode. In other words, if the field flag is set, erasure of one track will be performed in field mode.In other words, if the field flag is set, erasure of one track will be performed. If the two tracks used for playback were played in field mode, one playback track will be erased.However, the number of erased tracks can be set using the IO key switch. If "0" is set from the 10 key switch, erasure in field mode is always executed via #V-5-2.However, if "0" is set from the 10 key switch, Erasing is not executed because the branch is to "B". Also, if "B" is set, the field flag is set in #v-5-2, so even if the frame was being played up to that point, the frame will not be erased. Of the two tracks that make up the picture, only the outer track is erased by one track.

Therefore, it is possible to erase only the signal recorded on one of the two tracks constituting a frame image.

Furthermore, when performing continuous track erasing, it is generally assumed in many cases that new information, such as a video signal, is recorded on the erased track. In the above embodiment, when continuous track erasing is completed, the head 3-1 is located on the last erased track, so when recording new information, the user must press the track UP switch 54. Operate the down switch 55 to place head 3 on the track where you started recording.
-1 needs to be accessed.

Therefore, the next step is to execute continuous track erasing, and when this is completed, the flow for realizing a function that is extremely effective in terms of operability is to have the head 3-1 automatically access the track where continuous erasing has started. is shown in FIG. The flow shown in FIG. 29 is similar to #V-18 shown in FIG.
#V-19(7) This is a flow inserted between each step.

First, when subroutine V is executed, the track number N that is being accessed at that time in #V-1 is stored in memory N'. After the erasure is executed according to the flow described above and reaches #V-18, the flow shown in FIG. 29 is executed. That is, in #V-18-1, it is determined whether the number of the i-rack that the head 3-1 is accessing at that time matches the number of the track stored in the memory N' in #v-1;
If they do not match, #V-18-2. #VlB-3
is executed, the head 3-1 is controlled to access one track on the outer periphery, N is set to N-1, and the memory N is displayed on the 7-segment LED 25. The flow then returns to #V-18-1 and #V-18-2 . until the number of the track being accessed by the head 3-1 matches the number of the track stored in the memory N'. #When repeating V-18-3 and accessing the track where head 3-1 started erasing, #
The flow branches from V18-1 to #V-19, and the steps after #V-19 described above are executed. Therefore, by executing the flow shown in FIG. 29, the head 3-1 automatically accesses the track where erasing started when erasing is completed, thereby omitting the operation of manually searching for the position where erasing started at the time of next recording. You can.

Furthermore, when performing continuous erasing, the video to be erased is played back for a certain period of time, the operator is made to confirm this, and after determining whether or not the stop switch 61 is turned on, the erasing operation for that track is started. is extremely effective in preventing accidental erasure.

To realize this function, one track is UP in #V-13 of subroutine V shown in FIG.

Preferably, a step for a delay of about 1 second is provided in the step immediately after #v-6 after N+1 is executed until #v-7 is executed, and furthermore, during this delay, the stop switch 61 is Determine whether or not is turned on,
If it is not turned on, go to #v-7, if it is turned on, go to #V-
What is necessary is to provide a step that branches to 18.

By providing such a step, it is possible to check the video signal to be erased, so if the video signal that is not erased is played back, the continuous erasure can be interrupted by turning on the stop switch 61. Therefore, the probability of mistaken erasure is dramatically reduced.

In addition, when performing continuous erasing, in the above-mentioned embodiment, the flow branches from #V5-1 to #V5-2 in subroutine ■, and by executing #V5-2, all tracks are erased one track at a time in field mode. However, in order to shorten the execution time of continuous erasing, it is necessary to erase two tracks at least once during continuous track erasing by sending an erasing signal to two heads simultaneously in frame mode. is valid. An example in this case will be described below.

First, in FIG. 30, the flow shown in FIG. 30(a) is changed to #V-6 shown in FIG. This step is inserted between the step #V-7, and the flow shown in FIG. 30(b) is the step #V-11. #V-[This is a step inserted between the steps of [2]. Next, the flow will be explained.

After subroutine ① shown in FIG. 27 is executed up to @V-6, @V-6-1 is executed following #v-6. In this step, it is determined whether the number of erased track buffers E is two or more, that is, whether continuous track erasure is being performed.

If it is 2 or more here, the flow is #V-6-2
If not, proceed to #V-7. #V-6-
2, set E to E-1 and clear the field flag. The flow reaches #v-7. Here, an erase signal is generated at #v-7 shown in FIG.
In this case, if the field flag is set, an erase signal is supplied to one of the heads 3-1 and 3-2, that is, the head that is performing field playback, and the field flag is cleared. In this case, the erase signal will be supplied to both heads 3-1 and 3-2 at the same time. After the erasure is completed, #v-8 to #V-11 are executed as described above, and if the continuous erasure operation is not completed, Flow = reaches #V-11-1 from #V-11, Determine whether the field flag is set.

If continuous track erasure is not set and the field flag is set, the flow advances to #V-12 and follows the flow described above. Also, if continuous track erasure is set in #V-11-1 and the field flag is not set, as described above, #V-
Since two tracks have been erased in step 7, the flow reaches #V-11-2, N and +1 are set in N, and the head 3-1°3-2 moves toward the inner circumference of the l track. do. After that, the flow reaches #V-13, and the head moves one track further to the inner circumferential side according to the above-described flow.

By doing so, when performing continuous erasing, erasing is performed in frame mode until the number of remaining tracks for continuous erasing becomes 1, so that the execution speed of continuous erasing can be increased. However, in this case, if you want to check the video to be erased before executing the erase, following #v-6,
When the field flag is set, it is necessary to select heads 3-1 and 3-2 in FIG. 1 for a certain period of time so that head 3-1 performs field reproduction and head 3-2 performs field reproduction. be. Also #V-
2. #Skip step V-3 and switch to PB mode, RE
In particular, by switching between the C mode and the C mode, a mode in which the reproduced video to be erased during continuous erasing is confirmed or a mode in which the reproduced video is not confirmed may be selected. In other words, select a mode in which the images to be erased are not confirmed when performing continuous erasure, and perform the flow shown in FIGS. 30(a) and (b) in the second
When added to the flow shown in FIG. 7, the time for continuous erasing becomes the shortest, and this is an extremely effective means when erasing all tracks.

Next, subroutine (2) executed when the all-track erase standby switch 79 is turned on will be explained with reference to FIG.

#W-1 The near segment LED 25 flashes "j:;E" (ALL-ERASE) at 2 Hz, indicating the all-track erase standby state.

#W-2: Determine whether or not the PB mode flag is set, and if it is not set and the flow branches to #W-4 if the flow goes to #W-3.

#W-3-1: Clear the PB mode flag to prohibit reproduction of the magnetic sheet I.

#W-3-2: Detects that the switch 79 is turned off and proceeds to #W-4.

#W-4: Determine whether the erase switch 78 is on or not. If it is on, the flow branches to #W-9; if not, the flow branches to #W-5.

#W-5: All track erase standby switch 79
Determine whether or not is turned on. If it is on, #W-7
If it is not on, the flow branches to #W-6.

#W-6: Determine whether any switches other than switch 79 are turned on. If it is on, the flow branches to #W-7, and if it is not on, the flow branches to #W-4.

#W-7: Stop the blinking of LED25, and
5 to display N, that is, the track number accessed by the head 3-1.

#W-8: If the switch 79 is turned off at the same time, the process returns to ■.

#W-9: When the erase switch 78 is turned on in #W-4, the flow branches to this step. In this step, it is determined whether or not there is an erroneous erasure prevention claw (not shown). If there is, the flow branches to #W-10; if not, the flow branches to #W-7.

#W-10: Determine whether N is "l", that is, the track number accessed by the head 3-1 is "l", and if it is "l", go to #W212 with "l". If not #
The flow branches to W-11.

#W-ii. Move the heads 3-1, 3-2 to the outer circumference side by one track, and then subtract 1 from N to change the flow to #
Return to W-10. Therefore #W-10. The flow branches to #W-12 only when the number of the track being accessed by the head 3-1 reaches 1 by repeatedly executing #W-11.

#W-12: Flashing N on LED25 (5Hz)
let This allows the user to know which tracks have been erased when all tracks are erased.

#W-13=Field flag is cleared and frame mode is set. Therefore, head 3-1.
3-2 is used to erase the track.

#W-14: These two steps are #V-7. #V-
Same as 88W-15.

#W-16: Since both heads 3-1 and 3-2 are used and two tracks are erased without moving the head, in this step the head is moved two tracks to the outer circumferential side and further N is erased. Add 2 to .

#W-17: Determine whether or not N is 50. If N is 50, the flow branches to #W-7; if not, the flow branches to #W-12, and erasing of all tracks is completed. Until #W-
Steps 12 to #W-17 are repeated.

As explained above, in the all-track erase mode, which is executed by turning on the erase switch after turning on the all-track erase standby switch, the PB mode flag is cleared before erasing, and the video to be erased is not confirmed. In addition, the magnetic head 3-1. Since erasing is performed two tracks at a time using both 3-2, the time required to erase all tracks is extremely short compared to the method of erasing one track at a time. The head is moved to the end of the track (in this example, the outermost circumference) and then all the tracks are sequentially erased toward the opposite end. Even if the head 3-1 is accessing the position, all tracks can be surely erased.

Further, during erasing, the number of the track being accessed by the head 3-1 is displayed on the LED 25, so that the user can recognize how much erasing is being performed.

In the embodiments described above, the magnetic sheet 1 is used as the recording medium, but an optical recording medium may be used. A magneto-optical recording medium or other recording medium may also be used. The recording means is a means depending on the recording medium, for example, in the case of an optical disc, an optical head is used.As explained above, according to this embodiment, the mode in which the set ID can be recorded together with the video signal is set as shown in FIG. There is a mode shown in (a) in which the contents of the set ID are recorded while being monitored, and a mode shown in Figure 2 (b) in which the contents of the set ID can be recorded together with the video signal without being monitored. It has a recording mode in which it is displayed. Therefore, if the mode shown in FIG. 21(a) is selected, 1. The area for monitoring the DC contents is expanded, and the I
If the display of D becomes an eyesore, please refer to Figure 21 (b).
) If you select the mode shown in ) and record the video signal, the ID
recording is now possible, and there is no obtrusiveness on the monitor for the video signal to be recorded.
This has the effect of improving operability.

Further, according to this embodiment, when a character signal is superimposed on a video signal to be recorded and monitored, the video signal is recorded, and the character signal being monitored blinks, thereby causing the recording operation. You can confirm that this has been done.

Therefore, it is not necessary to provide a dedicated display means to indicate that a recording operation has been performed, and the user can confirm whether or not a recording operation has actually been performed simply by observing the monitor.

<Effects of the Invention> As explained above, according to the present invention, only the video signal is displayed without displaying the data signal recorded together with the video signal on the monitor. This can prevent it from being hidden.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing combinations of switching states of SW2 to SW5 shown in FIG. 1, and FIG. 3 is a front view of the device of this embodiment. Figure, S
Figure 4 is a front view of the remote control device used with the device, Figures 5 to 20, Figures 23 and 25.
Figures 27 to 27 and 29 to 31 are C shown in Figure 1.
Flowchart of PU40, Fig. 21, Fig. 22, Fig. 2
Figure 4 is a diagram for explaining the ID signal displayed on the monitor, Figure 28 is a diagram for explaining the flow of Figure 27,
FIG. 32 is a diagram for explaining signals generated from the erase signal generator 85 shown in FIG. 1. 1-m-Magnetic sheet 3-1.3-2---Head 4O---CPU

Claims (2)

[Claims] (1) A recording device that records both a video signal and a data signal related to the video signal on a recording medium, comprising: a first means for superimposing the data signal on the video signal and outputting it to a monitor; and converting the data signal into a video signal. A recording device characterized by comprising: a second means for outputting to a monitor without superimposing. (2) The recording apparatus according to claim 1, wherein the first means is an addition means for adding the data signal and the video signal.