JPH0746403B2 - Erasing device - Google Patents

Description

The present invention relates to an erasing device for erasing information recorded on a recording medium.

<Prior Art> Conventionally, a recording / reproducing apparatus has been considered in which a recording / reproducing head is provided separately from the erasing head or is also used.
Conventionally, when performing an erase operation in such a device,
The recording / reproducing head is moved to the track to be erased from the recording medium, and the erasing operation is performed immediately by pressing the erasing button regardless of the recording mode or the reproducing mode at that time.

<Problems to be Solved by the Invention> However, in the above-mentioned apparatus, since the erase operation is performed only by a single erase command, there is a problem that another track may be erased by mistake. .

There is also known a device capable of erasing when both the erasing switch and the safety switch are operated in advance in the reproduction mode.

However, even in such a device, erasing cannot be performed unless the reproduction mode is set in advance, so that the operability deteriorates.

Therefore, an object of the present invention is to provide an erasing device that improves operability and prevents erroneous erasing.

In order to achieve such an object, the present invention provides a first detecting means (corresponding to the switch 77 of FIG. 1 in the embodiment described below) for detecting an erase designation input, and a second detecting means for detecting a reproduction command input. Means (also switch 53), reproducing means for reproducing information recorded on the recording medium (also heads 3-1, 3-2, amplifier 6 and thereafter), and display means for displaying the operating state of the reproducing means. (Similarly to LED 25) and a control means for operating the reproducing means in response to the erasing command input or the reproducing command input and controlling the display means in conjunction with the operation of the reproducing means (also the first
27 # V-3, CPU 40 which executes FIG. 6 # A-3), and the control means operates when the reproducing means operates in response to the erase command input and when in response to the reproducing command input. The display mode is variably set depending on whether the operation is performed (when operating in response to a playback command input, the shift number is displayed on LED25, and when operating in response to an erase command input, this LED25 is displayed in blinking). An erasing device characterized by the above.

<Embodiment> The present invention will be described in detail below with reference to the drawings. In the embodiment of the present invention described below, a still image video signal is applied to a disk-shaped recording medium, specifically a disk-shaped magnetic sheet. A recording / reproducing apparatus for recording or reproducing a recorded still image video signal will be described.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, reference numeral 1 designates a recording / reproducing track of a video signal, a track pitch, and a magnetic sheet on which the positions of the tracks are defined in advance. The track is concentrically formed, and one track of a video signal corresponds to one field. In the case of the recorded frame video signal, a video signal of one field is recorded in two adjacent tracks to form a frame video signal. The magnetic sheet 1 is previously put in a jacket (not shown), and an erroneous erasure prevention claw is provided in the jacket, and the erasing operation is prohibited by folding the claw in advance like the audio cassette. . Two
Is a DC motor for rotating the magnetic sheet 1 at a constant speed, 3-
Reference numerals 1 and 3-2 are in-line heads that access two adjacent tracks, 3-1 is an outer peripheral side, and 3-2 is an inner peripheral side. 4 is a magnetic head moving mechanism for moving the magnetic heads 3-1 and 3-2 so as to access the tracks formed on the magnetic sheet 1, and 5 is a magnetic head moving mechanism 4
When the magnetic head 3-1 accesses the innermost track on the magnetic sheet 1, the state is switched from off to on, and an L level signal is output to a micro computer (hereinafter referred to as CPU) 40 described later. The innermost circumference detection switch, 6 is a reproduction amplifier for amplifying the signals detected by the magnetic heads 3-1 and 3-2, 7 is a level detector for detecting the average value of the output signals from the reproduction amplifier 6, and 8 Is a comparator for detecting whether the output of the level detector 7 is higher than a threshold value set by a reference voltage source (not shown), 9 is a demodulation circuit for demodulating the output signal of the reproduction amplifier 6, and 10 is 1/2 A 1 / 2H delay circuit that delays the output of the demodulation circuit 9 by a horizontal scanning period (hereinafter referred to as 1 / 2H), 11 separates synchronization signals such as a horizontal synchronization signal Hsync and a vertical synchronization signal Vsync from the output of the demodulation circuit 9. Sync signal separation circuit, 12 is a sync signal Detecting a predetermined data signal from an output of the reproduction amplifier 6 in accordance with the timing of the synchronizing signal separated from the release circuit 11 is a data demodulator for demodulating the data signal. Incidentally, the data signal is a signal for discriminating what kind of information the information recorded in the track is, for example, a field video signal or a frame video signal, and a date signal set by the user. , Which is a signal indicating an 11-digit number freely set by the user and which is recorded in a frequency band lower than that of the video signal at a position having a predetermined relationship with the portion where the track synchronization signal is recorded. The reason why the demodulation circuit 9 and the data demodulation circuit 12 are provided separately is as follows.
That is, the video signal recorded on the magnetic sheet 1 is FM-modulated, but the data signal other than the video signal is different from FM modulation DPSK modulation method (Defferatial Phase Shft Keying)
Is taken. Therefore, the demodulation circuit 9 described above is an FM demodulation circuit, and the data demodulation circuit 12 is a DPSK demodulation circuit.

13 is a monitor for reproducing and observing video signals,
13 'is a printer connected to print the video signal. The printer 13 'starts its operation when the signal at the start signal input terminal becomes H level, and makes the busy signal output terminal L level during operation. 14 is a data demodulator
Contrary to 12, the data output from the CPU 40 described later is DPSK
Hsyn, V which is a modulator for modulating and which is separated from the video signal input from the video input terminal 18 by the sync signal separation circuit 17.
The data modulated at the timing according to sync is output to the recording amplifier 16.

Reference numeral 15 is a recording amplifier for processing the video signal input from the video signal input terminal 18 for recording such as FM modulation and outputting the processed signal to the recording amplifier 16. Reference numeral 19 is a reference signal generator, which generates an accurate reference pulse (60 Hz) for rotating the magnetic sheet 1 and an erase crossover signal.

Reference numeral 20 is a magnetic piece provided on the above-mentioned magnetic sheet 1, and is a DC signal synchronized with the reference signal generated by the reference signal generator 19 using a signal from the magnetic piece 20 as described later.
The rotation control of the motor 2 is performed. 21 is DC magnetic sheet 1
It is a PG coil for detecting a signal from the magnetic piece 20 when it is rotated by the motor 2.

Reference numeral 22 is a waveform shaping circuit that shapes the waveform of the signal output from the PG coil 21, and the output of the waveform shaping circuit 22 will be described later.
Input to the CPU 40 and the motor control circuit 23.

Reference numeral 23 is a control circuit for controlling the rotation of the DC motor 2. The sync signal separating circuit 17 outputs Vsync or the output signal of the reference signal generator 19 and the output of the waveform shaping circuit 22, that is, the magnetic sheet 1. The rotation of the DC motor 2 is controlled so that the phase relationship with the signal from the magnetic piece provided above is in a predetermined relationship, for example, the phase of the two is always shifted by 7H. Here, when the recording operation is performed by the magnetic heads 3-1 and 3-2, SW1 is switched to the side of the sync signal separation circuit 17 in advance, and Vsync and the signal input from the waveform shaping circuit 22, that is, the magnetic sheet 1 The rotation of the DC motor 2 is controlled based on the signal from the magnetic piece 20 provided above, and the magnetic head 3-
When the reproduction operation is performed by 1, 3-2, SW1 is switched to the reference signal generator 19 side, and the reference signal from the reference signal generator 19 and the signal input from the waveform shaping circuit 22, that is, the magnetic The rotation of the DC motor 2 is controlled based on a signal from the magnetic piece 20 provided on the seat 1.

23 'is a head 3- based on a signal from the CPU 40 described later.
It is a driver that drives a step motor 24 for controlling the positions of 1, 3-2, and the step motor 24 moves the heads 3-1, 3-2 via the head moving mechanism 4.

Reference numeral 25 'is a display circuit driven by a signal from the CPU 40. As a display element, as shown in FIG. 3 which will be described later, heads 3-1, 3-2 are accessing track NO and head 3-. Display the 7-segment display element that displays the feed speed of 1,3-2 in 2 digits, and that it is in the playback mode. P
B.LED, REC.LED that indicates the recording mode, FRAME.LED that displays the frame mode, FIELD.LED that displays the field mode.

26 is a ROM in which the program of the CPU 40 is stored, and 27 is a RAM in which the data of the CPU 40 is temporarily stored. 28 is a timer driven by the CPU 40, and 29 is a crystal oscillator that generates the reference clock of the CPU 40. Reference numeral 80 is a detection circuit connected to photo couplers 81 and 82 which form a detection switch for detecting whether or not the magnetic sheet 1 is inserted.

83, 84 and SW6 are data signals such as signals of year, month and day, signals freely set by the user (hereinafter referred to as ID)
Circuit for displaying on the monitor 13 and the printer 13 '.
Is a sync separation circuit that separates Vsync and Hsync of the video signal input via SW5 for adjusting the timing of the generated data characters, and has the same configuration as the sync separation circuit shown as 17. Reference numeral 84 is a character generator for generating a character corresponding to the data signal in synchronization with Vsync and Hsync separated by the sync separation circuit 83. monitor
When the ID signal is superimposed on the video signal and displayed on the printer 13 and the printer 13 ', SW6 to which the control signal is given from the cpu40
In the ON state, the sync signal and the data signal are added by the adder shown as in FIG.
It is displayed in a specific position at 3 '. Details will be described later.

Reference numeral 85 is an erasing signal generator for erasing a signal on an arbitrary track of the magnetic sheet 1. The erasing AC signal is given from the reference signal derivation device 19.

Here, the erasing signal generator 85 generates an attenuation signal formed by a period T _{1 of} constant amplitude as shown in FIG. 29 and an attenuation period T ₂ following it, and is connected to the recording amplifier 16.

SW1 is a control circuit 30 driven based on a signal from the CPU 40
Is a switch whose state is switched by a signal from, the video signal is input from the video signal input terminal 18, the Hsync is output from the sync signal separation circuit 17, and the CPU is in the recording mode. When the signal indicating that is input, the sync signal separation circuit 17 and the motor control circuit 23 are connected, and Hsync is not output from the sync signal separation circuit 17, or the signal indicating that the playback mode is input from the CPU 40. Alternatively, the reference signal generator 19 and the motor control circuit 23 are connected in the erase mode.

SW2 is a switch whose state is switched based on a signal from the CPU 40. The state in which the head 3-1 is connected to the recording amplifier 16, the state in which the head 3-1 is connected to the reproducing amplifier 6, and the recording amplifier 16,
It switches between an intermediate state in which it is not connected to any of the reproduction amplifiers 6.

SW3 is a switch whose state is switched based on a signal from the CPU 40 like SW2, and the head 3-2 is connected to the recording amplifier 16
, A state in which the reproducing amplifier 6 is connected, and an intermediate state in which neither the recording amplifier 16 nor the reproducing amplifier 6 is connected.

SW4 is in the state of being switched to the upper side in FIG. 1 when reproducing the video signal from the magnetic sheet 1 and when reproducing the frame video signal by using the heads 3-1 and 3-2 together, that is, in the demodulation circuit 9. When the field video signal is reproduced by using only the head 3-1 in the connected state, it is switched to the upper side and the lower side in FIG. 1, that is, connected to the demodulation circuit 9. The switch is driven by the CPU 40 so that the state and the state connected to the 1 / 2H delay circuit are alternately switched for each field.

SW5 is a switch driven by the CPU 40 so as to connect the monitor 13 to the video signal input terminal 18 during recording and connect the monitor 13 to SW4 during reproduction.

By the way, as described above, the video signal recorded on or reproduced from the magnetic sheet 1 may be a field video signal of only one field or a frame video signal composed of a pair of two fields. However, switching of the states of SW2, SW3, SW4, and SW5 in such a case will be described with reference to FIG.

FIG. 2 is a diagram showing combinations of switching states of SW2, SW3, SW4, and SW5.

In the field reproduction, SW2 connects the head 3-1 to the reproduction amplifier 6 and SW3 is in the intermediate state, that is, the head 3-2.
Is connected to neither the reproduction amplifier 6 nor the recording amplifier 16, and SW4 outputs the signal directly from the demodulation circuit 9 to the monitor 13 in the odd field and the 1 / 2H delay circuit in the even field.
The output is switched alternately for each field so that a signal is output to the monitor 13 via 10, and skew distortion is prevented.

Next, in frame reproduction, SW2 connects the head 3-1 to the reproduction amplifier 6 in the odd field, the intermediate state in the even field, the SW3 becomes the intermediate state in the odd field, and the head 3-2 in the even field. Connect to. Therefore, at the time of frame reproduction, one of the heads 3-1 and 3-2 is alternately output to the reproduction amplifier 6 for each field.

In this case, SW4 is switched to the upper side in FIG. 1, and the signal from the demodulation circuit 9 is directly output to the monitor 13.

Note that SW5 is driven so that the monitor 13 is connected to SW4 in any of the above-mentioned field reproduction frame reproduction states.

Next, in the field recording, SW2 connects the head 3-1 to the recording app 16 and SW3 becomes the intermediate state.

Therefore, at the time of field recording, recording is performed by the head 3-1.

Further, in frame recording, SW2 connects the head 3-1 to the recording amplifier 16 in the odd field, the intermediate state in the even field, the SW3 becomes the intermediate state in the odd field, and the head 3-2 to the recording amplifier 16 in the even field. Connecting. In frame recording, head 3
The combination of 1,3-2 can be reversed.

Further, in both field recording and frame recording, the SW5 is switched so that the video signal to be recorded can be observed on the monitor 13 by connecting the monitor 13 to the video signal input terminal 18 during recording. In such a case, SW4 may be in any state.

Next, the erase mode will be described. In the erase standby state, which will be described later, SW1 is connected to the reference signal generator side, and SW5 is connected to the upper side in FIG. 1, that is, the same state as the reproduction mode. At this time, the field erase, for example, the case where only the track reproduced by the magnetic head 3-1 is erased will be described. In this case, SW2 should be in the recording amplifier side and SW3 should be in the intermediate state at the same time when erasing starts
The control signal is sent from the cpu40 and the erase signal generator 85
At the same time, an erase signal trigger pulse is sent from the cpu 40 so that the erase signal is sent only to the head 3-1.

Next, the frame erasing will be described in which the tracks being accessed by the heads 3-1 and 3-2 are simultaneously erased. When erasing a frame, an erasing signal is sent to the heads 3-1 and 3-2 at the same time, so that a control signal is sent from the cpu 40 so that both SW2 and SW3 are on the recording amplifier side. Then, an erase signal is generated by the trigger pulse from the cpu 40, and the erase signal flows to both heads through the recording amplifier.

Further, in the present embodiment, when the field erasing is performed, the erasing is performed by the head 3-1. However, when the field erasing is performed by using the head 3-2, SW2 is in the intermediate state and SW3 is on the recording amplifier side. It should be controlled like this.

Next, the switches 51 to 78 shown in FIG. 1 will be described.

In making such a description, the appearance of the apparatus of this embodiment shown in FIGS. 3 to 4 will also be described.

FIG. 3 is a front view of the device of this embodiment, and FIG. 4 is a front view of the remote control device used in the device of this embodiment.

Switches 51 to 79 and 72 shown in FIG. 1 are switches provided in the device shown in FIG. 3, switches provided in the remote control device shown in FIG. 4, and shown in FIG. Of the remote control device shown in FIG. 4 and the switch group provided in both of the remote control devices shown in FIG.
The same reference numerals are given in FIGS. The switch provided in the apparatus shown in FIG. 3, which is provided only in the remote control apparatus shown in FIG. 4 in FIG. 1, is connected to the CPU 40 through a line. Although shown for the sake of convenience, the signal generated by operating the switch provided only in the remote control device shown in FIG. 4 is converted into infrared light by the remote control device. Input is made to the CPU 40 of the device via a remote control light receiving unit 45 provided in the device of FIG.

It should be noted that various other modified examples of the present embodiment can be considered as a method of arranging the switches 51 to 79, and the present invention is not limited to this embodiment.

1 to 4, 41 is a power switch, 42 is a slot for inserting the magnetic sheet 1, and an eject button when the magnetic sheet 1 is inserted in the slot 42.
When 43 is turned on, it automatically opens and the magnetic sheet 1 is ejected. 43 is the above-mentioned eject button, 44A, 44B
PB.LED, REC.LED, and 45 are remote control light-receiving parts that receive signals from the remote control device shown in FIG. 4, 46 is an interval mode display LED that lights when interval playback is executed, and 48 Is a display LED that indicates whether field playback or recording, frame playback or recording is set, and 25 is the 2-digit 7 described above.
The segment LEDs, 50A, 50B, and 50C are the program playback setting switch 58, interval time setting switch 57, and
This is an LED that displays the operating state of the program track setting switch 62.

Reference numeral 51 is a REC mode switch for setting the recording mode and for confirming whether the track being accessed by the head in the recording mode has been recorded or not, and the head is accessed when the switch is turned on. If the track being recorded is already recorded (when recording the field, the head 3
If the track that 1 is accessing has already been recorded, or if one of the tracks accessed by heads 3-1 and 3-2 has been recorded during frame recording, the REC.LED will blink and the head will be displayed. Indicates that the track being accessed is not recordable, and if it has not been recorded, the control circuit 30
When it is determined that the video signal is not input, the REC.LED lights up, indicating that recording is possible.

Reference numeral 52 denotes a REC switch that determines the timing for performing the recording operation, in the case where the recording mode is set by the REC mode setting switch 51, and when the switch 51 is turned on, recording is performed on the magnetic sheet 1. . If continuous recording is set in advance by the track feed speed setting switch 56, which will be described later, continuous recording is performed while the heads 3-1 and 3-2 are automatically shifted while the switch 51 is on. Be seen.

Reference numeral 53 is a PB mode setting switch for setting the reproduction mode, and when the switch 53 is turned on, the PB.LED indicating the reproduction mode is turned on.

Reference numeral 54 is a track UP switch. By operating the switch 54, the driver 23 'is controlled to control the step motor 24.
And the head moving mechanism 4 rotates the heads 3-1, 3
By moving -2, the heads 3-1 and 3-2 are shifted, and the track accessed by the head is changed to the inner circumferential direction. Also, when recording is performed in frames by the field / frame setting switch 59, which will be described later, the process advances by two tracks. When the track UP switch 54 is turned on while the playback is set, the heads 3-1 and 3-2 are shifted by 2 tracks, and the 7-segment LED 25 is also shifted by 1 track, not by the track number. One track number shifted by one track is displayed. When field recording or playback is set and the track UP switch 54 is turned on, the head 3-1 and 3-2 are set to 1.
7 segment LE by shifting inward by truck
The shift number shifted by one track is also displayed on D25.

When the recording mode is set and the heads 3-1 and 3-2 are shifted by operating the track UP switch 54, the tracks accessed by the heads 3-1 and 3-2 are recorded. If it has been completed, REC.RED44B blinks. The 55 is a head up 3-1 as opposed to the track UP switch 54.
It is a track DOWN switch for changing the access of 3-2 to the outer peripheral direction.

When the frame reproduction is set in the switch 55 as well as the track UP switch 54, when the switch 55 is operated and the track around the track 1 and the track around the track 2 are frame-recorded. The 7-segment LED 25 displays the track number that is shifted by 2 tracks instead of the track number that is shifted by 1 track. When field recording or playback is set, one track is operated when the switch 55 is operated. The track numbers that have been shifted one by one are displayed.

Further, when the recording mode is set in advance similarly to the case of the track UP switch 54 described above, the head 3-1 and the head 3-1 are operated by operating the track DOWN switch 55.
If the track accessed when the 3-2 is shifted is already recorded, the REC.LED 44B blinks.

Reference numeral 56 indicates whether to perform such an operation automatically and continuously while performing a head shift when recording or reproducing, and how many times per second the operation is performed in the case of continuous operation. This is a track feed speed setting switch for setting the track feed speed.

When the switch 56 is pushed once and turned on, 7 segments
The track feed speed is displayed on the LED 25 instead of the track number, and when the track feed speed setting switch 56 is turned on again within a predetermined time by the timer 28 shown in FIG. 1 in such a state, the switch 56 is turned on. 7-segment LED 25 for each 2 seconds
Indicates continuous screen recording or playback Indicates continuous recording or playback of 5 screens per second Indicates that 10 screens are continuously recorded or played back per second. Indicates that recording or playback will be performed on a one-off basis Is displayed on the cycle. When the switch 56 is not turned on again after the track feed speed is displayed instead of the track number on the 7-segment LED 25 by turning on the switch 56 and then turning it off, when the timer 28 completes the measurement of the predetermined time. The LED 25 returns from the state where the track feed speed is displayed to the state where the normal track number is displayed.

Further, when the track feed speed is changed by the switch 56, when the frame video recording is set by the field / frame setting switch 59 and the REC mode setting switch 51 in advance, continuous recording of 10 screens per second is not set. .

57 is an interval time setting switch. That is, the interval time setting switch for setting the interval time of the track feed in the case of performing the interval reproduction which is the continuous reproduction but the reproduction interval time is relatively long or the program reproduction is set by the program track setting switch 58 described later. The interval time is set by the 10-key switch shown at 63 to 72 within 10 seconds after the switch is turned on.

When the switches other than the 10-key switches 62 to 72 are turned on after the interval time setting switch 57 is turned on, the interval time setting is automatically canceled. 58
Is a program reproduction setting switch for setting the sequence of reproduction tracks in advance and setting a program reproduction mode in which the reproduction operation is continuously performed at the interval time intervals set by the interval time setting switch 57.

To specify the order of the reproduction tracks, first set the program reproduction mode by turning on the switch 58, and then by operating the track UP switch 54 and the track DOWN switch 55, the tracks accessed by the heads 3-1, 3-2 are selected. This is performed by reproducing the video of the desired track by changing it and checking it on the monitor 13 to turn on a program track setting switch 62, which will be described later, to store the track number confirmed on the monitor 13. 59
Is the above-mentioned field / frame setting switch, and the field recording or reproduction mode and the frame recording or reproduction mode are switched alternately every time the switch is turned on.

If the REC mode setting switch 51 and the track feed speed setting switch 56 are set to the continuous recording mode of 10 screens per second in advance and the frame recording is selected by the field / frame setting switch 59, the track feeding is performed. The speed is automatically changed to the continuous recording mode of 5 screens per second.

That is, as compared with the field recording, the heads 3-1 and 3-2 must be shifted by 2 tracks at a time when the frame recording is performed, and therefore, when recording 10 screens, 20 times a second are recorded.
A head shift of the track is required. That is, in consideration of the time for recording the video signal, the head shift of 2 tracks must be performed in 4/60 seconds, but since such a high speed head shift is difficult, in the present embodiment. The continuous recording of 10 frames per second is prohibited.

Reference numeral 60 denotes a start switch for performing interval continuous reproduction or program reproduction. When the start switch is turned on, when the interval reproduction is set, reproduction of the recorded tracks sequentially from the first track is performed at the interval time. Setting switch 57, numeric keypad switch 63
The interval reproduction is started according to the interval time set by ˜72, and the program reproduction is started when the program reproduction is set. Reference numeral 61 is a stop switch for stopping the reproduction operation started by the start switch 60. When the switch 61 is turned on during the program reproduction, the reproduction being stopped by the program while the track being reproduced at that time is reproduced.

Reference numeral 62 is the above-mentioned program track setting switch.

Reference numeral 73 is a switch for starting the ID setting in the recording mode and for switching whether to display the contents of the ID in the reproduction mode. That is, when the switch 73 is turned on in the recording mode, the ID setting mode is set, and when the switch 73 is turned on in the playback mode.
It is possible to switch whether to display the contents of the ID or not. 74, 75, and 76 are switches that turn on when setting the year as an ID when the switch 73 enters the ID setting mode, a switch that turns on when setting the month, and a switch that turns on when setting the day. Is. In FIG. 1, switches 74, 75, 76 are shown for convenience.
Further, the switches 57, 58, 62 described above are shown as independent switches, but in this embodiment, the switches 74, 75, 76 are also used as the switches 58, 57, 62 as shown in the remote control device of FIG. Has been done. That is, the interval time setting by the switch 57, the program setting by the switch 58,
Since the operation of the program track setting by the switch 62 is performed independently of the ID year, month, and day setting, in the present embodiment, the number of switch members is reduced by using the switch also as a switch, thereby improving operability and reliability. Is improving.

Various other combinations are conceivable when the switch is also used.

Reference numeral 77 is an erase standby switch for putting the apparatus into an erase standby state once when the information recorded on the magnetic sheet 1 is erased, and 78 is an erase standby switch 77
Is an erase switch for executing an erase operation in the erase standby state set by. Reference numeral 79 is an all-track erasing standby switch that sets a mode for erasing all tracks.

When erasing the information recorded on the sheet 1, the switch 77 is first turned on to set the erasing standby state. Since the reproduction mode is automatically set in this state, the monitor 13 or the printer 13 'can confirm the image recorded in the erase standby state, that is, the track to be erased before executing the erase. In the standby state, 10 key switches 63 to 72
You can specify the number of tracks to be erased continuously by operating. Then, by turning on the erasing switch 78, at least one of the heads 3-1 and 3-2 is connected to the recording amplifier 16 and the information recorded in the track by the erasing signal shown in FIG. 32 generated from the erasing signal generator 85. Is erased. Also, erase all tracks standby switch
If 79 is turned on and then the erase switch 78 is turned on, all tracks are automatically erased.

Next, the operation of the embodiment of the present invention will be described using the flow charts of FIGS. 5 to 20, 23, and 25 to 27.

First, when the power switch 41 shown in FIG. 3 is pushed in, the power of the apparatus shown in FIG.

# 1: Then, the register S, which will be described later in FIG. 5, is reset to "0", the PB mode flag is set, the track feed speed is initialized to 2 screens per second, and the interval time is initialized to 3 seconds. Therefore, when the power is turned on, the continuous reproduction mode is automatically set in advance.

# 2: It is detected whether or not the jacket having the magnetic sheet 1 is pushed in. When the jacket is pushed in, the flow branches to # 3, and when it is not pushed in, the flow skips # 3 and branches to # 4.

# 3: In # 2, the DC motor 3 is driven when the jacket having the magnetic sheet 1 is pushed in.

# 4: It is detected whether or not the head 3-1 is accessing the 50th track by detecting whether or not the switch 5 shown in FIG. 1 is turned on, and the head is accessed to the 50th track. When the flow is
When the head 3-1 does not access 50 tracks, the flow branches to # 5, and the step motor shown in FIG.
Drive 24 and repeat the loop of # 4 and # 5 so that the head 3-1 accesses the 50th track.

# 6: When the head 3-1 accesses the 50th track, the flow reaches this step, and the register N for accessing the memory (RAM27) is set to 5 at this step.
Set to 0.

# 7: In this step, it is detected whether or not the DC motor 2 is driven. When the jacket with the above-mentioned magnetic sheet 1 is inserted, the DC is executed by executing # 3.
Since the motor 2 is driving, the flow is this step # 8.
Proceed to and set the field flag. When the jacket is not inserted, the DC motor 2 is not driven because the flow proceeds without going through # 3. Therefore, the flow is # 2 to detect whether or not the jacket is inserted.
Return.

# 8: At # 7, the field flag is set when the DC motor 4 is driven. Therefore, the LED 44A indicating the field mode shown in FIG. 3 is turned on, and the display indicating the field is performed. That is, in this embodiment, the field mode is automatically set when the power is turned on and the jacket is inserted.

# 9: The output of the level detection circuit 7 shown in FIG. 1 is detected to determine whether the track being accessed by the head 3-1 is a recorded track. Here, since the track being accessed by the head 3-1 has already been recorded, when the output of the level detecting circuit 7 becomes H level, the flow proceeds to # 10 and the output of the level detecting circuit 7 becomes L level. If so, the flow proceeds to # 16.

First, # 16 will be described.

# 16: Set "0000" to N address of memory. Here, "0000" indicates that the track corresponding to the address of the memory is unrecorded.

Next, the flow from # 10 onward will be described.

# 10: When the output of the level detection circuit 7 is at H level in # 9, the signal recorded in the track is reproduced and the ID signal is fetched from the data demodulator 12.

# 11: The contents of the ID signal are detected to determine whether the video signal recorded in the track is a field video signal or a frame video signal. Here, if it is a field video signal, the flow proceeds to # 15, and if it is a frame video signal, the flow proceeds to # 12.

# 12: In this step, it is determined whether the video signal of the track being accessed by the head 3-1 is an inner track or an outer track of the frame video signal. If it is an inner track, proceed to flow # 14. If it is an outer track, the flow proceeds to # 13.

# 13: If the video signal of the track being accessed by the head 3-1 is a track outside the frame video signal, the N address of the memory is set to "0011". If you proceed from # 1 to this step for the first time, N is 50 in # 6.
Has been set up.

# 14: In the case of the inner track of the frame video signal, the N address of the memory is set to "0010".

# 17: Here, when the head 3-1 is shifted to the first track and it is detected that N = 1, the flow proceeds to # 20, and when it is not N = 1, the flow proceeds to # 18.

# 18: When N = 1 is detected in # 17, the head 3-1 for one track is shifted to the outer peripheral side.

# 19: When the head 3-1 is even shifted to the outer peripheral side in # 18, N is subtracted from N.

# 20: When N = 1 is detected in # 17, that is, when the head 3-1 accesses the first track provided at the outermost circumference and the presence or absence of recording is set in the memory, the memory is stored here. The data of the Nth address of the memory, that is, the first address of the memory is read, and when it is "0011", specifically, when the first track is the outer track of the two tracks forming the frame video signal, the number is # 21. If so, the flow proceeds to # 23.

# 21: When it is detected in # 20 that the first track is a track outside the track forming the frame video signal, the flow proceeds to this step. In this step, when the data at the address N + 1 of the memory, that is, the data at the second address of the memory is read and is "0010", specifically, the second track is the inner track of the two tracks forming the frame video signal. Go to # 22.

# 22: The flow shifts to this step when the frame video signal is recorded in the two tracks of the first track and the second track. Therefore, the field flag set in # 8 is cleared and the field mode is changed to the frame mode. Therefore, the field frame display LED 48 shown in FIG. 3 is an LED indicating that it is in the frame mode.
Lights up.

# 23, # 24: The register N indicating the address of the above-mentioned memory is displayed on the 2-digit 7-segment LED 25 shown in FIGS.

With this display, the user can recognize the number of the track accessed by the head 3-1.

At the end of this flow, the jump to the flow shown in A is performed. The flowchart shown in FIG. 6 will be described below.

# A-1: Detects whether the REC mode setting switch 51 is turned on, and when the switch 51 is turned on, the flow calls a subroutine to set the recording mode, and when it is not turned on, #A. -2.

# A-2: It is detected whether or not the REC switch 57 is turned on, and when the switch 52 is turned on, a subroutine is called. When it is not turned on, the process proceeds to # A-3.

# A-3: It is detected whether or not the PB mode setting switch 53 is turned on, and when the switch 53 is turned on, a subroutine is called, and when it is not turned on, the process proceeds to # A-4.

# A-4: When the track UP switch 54 is turned on, the flow calls a subroutine, and when it is not turned on, the process proceeds to # A-5.

# A-5: When the track DOWN switch 55 is turned on, the flow calls a subroutine, and when it is not turned on, the flow proceeds to # A-6.

# A-6: When the track feed speed setting switch 56 is turned on, the flow calls a subroutine, and when it is not turned on, the flow proceeds to # A-7.

# A-7: When the interval time setting switch 57 is turned on, a subroutine is called. When it is not turned on, the process proceeds to # A-8.

# A-8: When the program setting switch 58 is turned on, a subroutine is called. When it is not turned on, the process proceeds to # A-9.

# A-9: When the program track setting switch 62 is turned on, a subroutine is called. When it is not turned on, the process proceeds to # A-10.

# A-10: A subroutine is called when the field frame setting switch 59 is turned on, and when it is not turned on, the process proceeds to # A-11.

# A-11: A subroutine is called when the start switch 60 is turned on and #A when it is not turned on.
Go to -12.

# A-12: Calls a subroutine when stop switch 16 is not turned on, and when it is not turned on #
Go to A-13.

# A-13: Jacket detection switch (detection circuit 8 in FIG. 1)
(Corresponding to 0) is turned on, the subroutine is jumped to, and when not turned on, the process proceeds to # A-14.

# A-14: The program reproduction mode flag and the program reproduction executing flag are cleared.

# A-15: 10 When any of the key switches 63 to 72 is turned on, the subroutine is called, and when it is turned on, the process proceeds to # A-16.

# A-16: When the ID switch 73 is turned on, the subroutine is called, and when it is turned on, the process proceeds to # A-17.

# A-17: Calls a subroutine when the year setting switch 74 is turned on, and # A- when it is turned on.
Proceed to 18.

# A-18: Call a subroutine when the month setting switch 75 is turned on, and # A- when it is turned on.
Proceed to 19.

# A-19: Call a subroutine when the day setting switch 76 is turned on, and # A- when it is turned on.
Go to 20.

# A-20: When the erase standby switch 77 is turned on, a subroutine is called, and when it is turned on, the process proceeds to # A-21.

# A-21: When the all-track erase standby switch 79 is turned on, a subroutine is called, and when it is turned on, the process proceeds to # A-13.

As described above, after the flow shown in FIG. 5 is executed to access the head 3-1 to the first track of the magnetic sheet, the head is jumped to the flow shown in FIG.
While detecting the state of each switch shown in FIG. 3, FIG. 3, and FIG. 4, the flow shown until the state of each switch is repeatedly executed, and the subroutine corresponding to the operated switch is called. .

The subroutine called when the track setting feed speed switch 56 is turned on will be described with reference to FIG.

FIG. 7 is a flow chart showing a subroutine executed when the switch 56 for changing the track setting feed speed is turned on.

# F-1 and # F-2: The set value of the track feed speed is read from the memory, and the set value is set in a track number display buffer (not shown).

Therefore, the 2-digit 7-segment LED 25 shown in FIG.
The track feed speed is displayed on. When the flow comes to this step for the first time, the track feed speed of 2 screens per second is set in # 1. Is displayed.

# F-3: When the track feed speed setting switch 56 is on, the flow repeats # F-3, and the switch 56
When is turned off, the flow moves to # F-4.

As described above, once the track feed speed setting switch 56 is turned on, the 2-digit 7-segment LED 25 shown in FIG. 3 is switched from the track number display to the track feed speed display, and then again. By turning on the switch 56, the track feed speed is switched. # F-
3 is provided so that the track feed speed is switched only when the switch 56 is once turned on, once turned off, and then turned on again.

# F-4, # F-5, # F-6, # F-7: In these steps, the track feed speed setting switch 56 is turned on and the third
The switch 56 or another switch is not turned on within a predetermined time (2 seconds) after the display of the 2-digit 7-segment LED 25 shown in the figure is switched from the track number display to the track feed speed display. In this case, it is a step provided to cancel the setting of the track feed speed.

A predetermined time (2 seconds) after the timer 1 starts counting
When the track feed speed setting switch 56 is turned on during the period, the flow advances from # F-7 to # F-10 and when the timing of the timer 1 is completed or when another switch is turned on. The flow proceeds from -6 to # F-8.

# F-8: Clear the count value of the timer.

# F-9: Contrary to # F-1, the display of the 2-digit 7-segment LED 25 shown in FIG. 3 is restored to the display of the track number.

# F-10: Clear the count value of timer 1.

# F-11: The track feed speed is set to a single value (once recorded or played back, it is head-shifted by one track in field mode and 2 in frame mode).
It is detected whether or not it is a head shift for the track and then stopped). If it is single, the flow proceeds to # F-12, and if it is not single, the flow proceeds to # F-13.

As described above, when the flow reaches this step after the power switch 41 is turned on, 2 screens per second are preset as the track feed speed in # 1.

# F-12: If the track feed speed setting is single, change the setting to 2 screens per second and return to # F-1.
The changed track feed speed is displayed and the above-mentioned #F is displayed.
-3 to # F-7 are executed.

# F-13: It is detected whether the track feed speed setting value is 2 screens per second, and if it is 2 screens per second, the flow proceeds to # F-14, and if it is not 2 screens per second, the flow proceeds to # F-15.

# F-14: The track feed speed set value is changed to 5 screens per second, the process returns to # F-1, the changed track feed speed is displayed, and the above # F-3 to # F-7 are executed.

# F-15: Detects whether the track feed speed setting value is 5 screens per second. If it is 5 screens per second, go to # F-16. If it is not 5 screens per second, that is, 10 screens per second is set. The flow proceeds to # F-17.

# F-16: It is determined whether or not the PB mode flag is set. If the PB mode flag is set, that is, if the reproduction mode is set, then go to # F-18. If the PB mode flag is reset, that is, if the recording mode is set, # F-19. The flow proceeds to.

# F-17: The track feed speed setting value is changed to single, the process returns to # F-1, the changed track feed speed is displayed, and the above # F-3 to # F-7 are executed.

# F-18: In the reproduction mode, whether the video signal recorded on the track of the magnetic sheet 1 is a field video signal or a frame video signal, field reproduction is performed during continuous track feeding. Therefore, in such a case, the track feed speed setting value is changed to 10 screens per second, and the flow returns to # F-1.

# F-19: Detects whether the field flag has been set. If the field flag has been set,
That is, in the recording mode, the track feed of 5 screens per second is set, and in the case of the field mode, the flow branches to # F-18.

If the field flag is not set, that is, if the track feed speed setting value of 5 screens per second is set in the recording mode and the frame mode is set, the flow advances to # F-17 to set the track feed speed setting value to single. Change to.

Therefore, in the above-mentioned subroutine, when the track feed speed setting switch 56 is turned on, the third
The track feed speed is displayed on the 2-digit 7-segment LED 25 shown in the figure, and the track feed speed is changed by turning on the switch 56 again within a predetermined time (2 seconds).

Further, there are three kinds of change ranges, that is, single, 2 screens per second, and 5 screens per second in the frame recording mode, and single, 2 screens per second, 5 screens per second in other than the frame recording mode.
There are 4 screens, 10 screens per second.

The change range is related to the track shift capability of the moving mechanism of the heads 3-1 and 3-2 shown in FIG. 1, and is set in advance to an appropriate range according to the track shift capability. is there.

Next, while the subroutine shown in FIG. 6 is being executed using FIG. 8, the track UP switch 54 and the track DOWN switch 5 are switched.
The subroutine called when 5 is turned on will be described. First, the flow called when the track UP switch 54 is turned on will be described.

# D-1: When the flow reaches this step, head 3
-1 determines whether the track being accessed is the innermost track by detecting whether the register N is 50 or not.

As a result, if N is not 50, the flow proceeds to # D-2, and if N is 50, the flow proceeds to # D-34 described later.

# D-2: It is determined whether or not the PB mode flag is set. When the PB mode flag is set, that is, in the reproducing mode, the flow proceeds to # D-8. When the PB mode flag is not set, that is, in the recording mode, the flow proceeds to # D-3.

# D-3: N + 1 address of memory is "0000", that is, N + 1th
Whether or not the track is unrecorded is detected, and if it is not recorded, the flow branches to # D-4 if it has been recorded.

# D-4: The fact that the N + 1th track has not been recorded is #D
If it is determined in step -3, it is determined in this step whether or not the field flag is set, and if it is set, it goes to # D-6. If it is not set, it goes to # D-.
The flow proceeds to 5.

This step is reached when it is determined in # D-5: # D-4 that the field flag has not been set and the frame mode has been entered. In this step, it is detected whether or not the (N + 2) th content of the memory is "0000", and when it is "0000", that is, when the (N + 2) th track is unrecorded, the procedure goes to # D-6. , "0000", that is, when the N + 2th track has been recorded, the flow proceeds to # D-7.

By executing the steps # D-3 to # D-5, in the frame mode, if both consecutive two tracks are unrecorded, go to # D-6 and at least one of the consecutive two tracks. Is recorded, # D-
The flow proceeds to 7.

# D-6: The track being accessed by the head 3-1 in the field mode, the track being accessed by the head 3-1 in the frame mode, and the track on the inner circumference side of the track one track from the track 3-1. When the track accessed by the head 3-2 is unrecorded, that is, when the track is recordable, the flow reaches this step, and the REC LED 44B shown in FIG. 3 is turned on.

# D-7: Contrary to # D-6, when the tracks to be accessed and recorded by the heads 3-1 and 3-2 have already been recorded, the REC LED 44B shown in FIG. 3 is blinked. (Blinking)
By doing so, a warning is displayed so that the user can recognize that recording is not possible.

If the PB mode flag is set in # D-8: # D-2, the flow reaches this step and the field flag is set.

The meaning of this step is # D-9, # D-10, #D
= 13.

# D-9: Whether or not the track accessed by the head 3-1 is the track on the outer peripheral side of the two tracks constituting the frame video signal as the address N of the memory is "0011", that is, as explained in # 13. If it is the outer track of the two tracks, the flow proceeds to # D-10, and if it is not the outer track, the flow proceeds to # D-13.

# D-10: It is detected whether the address N + 1 of the memory is "0010", that is, whether the track accessed by the head 3-2 is the inner track among the two tracks forming the frame video signal, If the track is the inner track of the two tracks, go to # D-11. If it is not the outer track, # D-11.
The flow proceeds to -13.

That is, of the two tracks forming the frame video signal, the track on the inner circumference side is erased, or when a new video signal is recorded after the erase, the track accessed by the head 3-1 constitutes the frame video signal. Even if the track is on the outer peripheral side of the two tracks, the track accessed by the head 3-2 may not be the track on the inner peripheral side of the two tracks. Therefore, in this case head 3
When -1,3-2 is shifted to the inner circumference side, it is necessary to shift only one track to erase or reproduce a track in which a video signal is newly recorded after erasing.

However, in such a case, if only one track of the heads 3-1 and 3-2 is shifted to the inner peripheral side, the head 3-
The frame video signal is not always recorded in the tracks that 1 and 3-2 are accessing, and there are cases where completely different field video signals are recorded. In this case, if the field flag is reset, there arises a problem that two separate field video signals are reproduced as frame video signals. Therefore, by providing the step # D-8 described above, in the present embodiment, when the head is shifted to the inner peripheral side, the field mode is set by setting the field flag in advance in the step, and the above-mentioned case is set. In the above, it is possible to solve the problem that a completely different field video signal is reproduced as a frame video signal.

# D-11; In this step, it is detected whether or not the register N is 49, and if N is 49, go to # D-13,
If N is not 49, the flow branches to # D-12.

# D-12; Heads 3-1 and 3-2 are accessing 2
When the frame video signal is recorded in one track, the flow reaches this step. When such a record is made, when the track UP switch is turned on, the driver 23 is driven so as to shift the heads 3-1, 3-2 by one track at this step, and then # D-13.
In 1 further shifts one track head 3-1, 3-2. As described above, N is updated by 1 each time the heads 3-1 and 3-2 are shifted.

# D-13; Heads 3-1 and 3-2 are set to 1 as in # D-12.
Shift by the amount of track.

Similar to # D-14 and # 23, N is displayed on the 2-digit 7-segment LED 25 shown in FIG.

In this embodiment, since such a step is provided in the flow after # D-12 and # D-13, when the frame video signal is recorded in the track accessed by the heads 3-1 and 3-2. The track number displayed on the LED25 will be updated by two, and the track number displayed on the LED25 will be updated by one when the field image signal is recorded. It is possible to display whether the signal or the frame video signal is recorded.

When this step is also provided between # D-12 and # D-13, the heads 3-1 and 3-2 are accessing 2
Even if the frame video signal is recorded in one track, when the track UP switch 54 is turned on, the track number displayed on the LED 25 is updated by one.

# D-15; It is determined whether or not the PB mode flag is set. If it has been set, the flow branches to # D-16, and if it has not been set, it branches to # D-19.
If it is set, the process branches to # D-15-1.

# D-15-1; here, the CPU 40 is the data demodulator 1 in FIG.
The reproduction ID signal output from 2 is loaded into RAM27. The flow proceeds to # D-15-2.

# D-15-2: Here, it is determined whether or not the ID is in a mode in which the ID signal is superimposed on the video signal and monitored. Details of this mode will be described with reference to FIG. If it is in this mode, proceed to # D-15-3, otherwise proceed to # D-15-4.

# D-15-3; When the flow reaches this step, the CPU superimposes the ID on the video signal and monitors it.
A reproduction ID signal is read from AM27, a character pattern is generated by controlling the character generator 40, and the character pattern is superimposed on the reproduction video signal on the monitor. The flow proceeds to # D-15-4.
In other words, at this time, the ID DATA signal recorded in the currently accessed track is displayed on the monitor.

# D-15-4: The flow branches to # D-20 when the automatic track forwarding flag is not set, and to # D-16 when it is set.

# D-16: The address N of the memory is "0011". It is determined whether the track accessed by the head 3-1 is a track to the outer peripheral side among the tracks in which the frame video signal is recorded. Here, N corresponds to the number of the track that the head 3-1 is accessing after the heads 3-1 and 3-2 have already been moved as described above. If the content at address N of the memory is "0011", the flow branches to # D-17. If not "0011", the flow branches to # D-19.

# D-17: It is determined whether the contents of the address N + 1 of the memory is "0010", that is, whether the track accessed by the head 3-1 is the inner track of the two tracks in which the frame video signal is recorded.

If the N + 1 address of the memory is "0010", the flow goes to # D-18, and if it is not "0010", # D-19.
Branch to.

When the flow reaches this step through # D-18; # D-16 and # D-17, the frame video signal is transmitted to the two tracks that are being accessed after the heads 3-1 and 3-2 have moved. Since it has been recorded, the field flag set in # D-8 is cleared to enter the frame reproduction mode. Incidentally, this step is executed only when the automatic track feed flag is set. (If the automatic track feed flag is not set, # D-15-
Since the flow branches from # 4 to # D-20, the field flag remains set in # D-8, and field reproduction is performed. # D-19; In this step, it is judged whether or not the automatic track feed flag is set, and if it is set, the routine returns to # D-20, and if it is set, this subroutine returns ( RTS).

The automatic track feed flag is a flag that is set in a subroutine to be described later, in order to get out of this routine when calling a subroutine or later described while executing a program that repeats playback while automatically sending a track. It is provided in.

# D-20: Load the track feed speed setting value from memory.

# D-21: It is determined whether or not the track feed speed setting value is single, and in the case of single, the procedure is # D-34.
If not single, the flow branches to # D-22.

# D-22: It is judged whether or not the track feed speed setting value is two screens per second, and if it is two screens per second, # D-23.
If the screen is not 2 screens per second, the flow branches to # D-24.

# D-23: Set WAIT TIMER register in CPU 40 to 28.

# D-24; It is judged whether or not the track feed speed setting value is 5 screens per second, and if it is 5 screens per second, # D-25.
If not 5 screens per second, the flow branches to # D-26.

# D-25; Set WAIT TIMER register to 10.

# D-26; When 10 screens per second is set as the track feed speed setting value, the flow reaches this step and the WAIT TIMER register is set to 4.

WAIT set in # D-23, # D-25, and # D-26
The TIMER register is used to control the track feed speed. In # D-31 and # D-32 described later,
It is subtracted every time the magnetic sheet 1 makes one revolution by the DC motor 2.

# D-27; It is judged whether or not the REC display flag is set. When it is set, the flow branches to # D-28, and when it is not set, the flow branches to # D-31. REC here
The execution flag is a flag that is set in the subroutine. It is set from the WAIT TIMER register that is set when the subroutine is called during the execution of a program that repeats recording while automatically sending tracks.
It is provided to make a time equivalent to the time required for recording by subtracting 2 or 5 at −29 and # D-30. That is, in the recording mode, the rotation state of the magnetic sheet 1 is detected from the PG coil 21, the timing for recording a signal to be recorded from a predetermined position on the magnetic sheet is determined, and the signal is recorded on the magnetic sheet 1. It is provided to do so.

; It is determined by these three steps whether or not the field flag is set, and if it is set, WA is set.
Subtract 2 from the IT TIMER register, and subtract 5 from the WAIT TIMER register if not set. If 10 screens per second is set as the track feed speed, the WAIT TIMER register is set to 4. However, since such setting is possible only in the field mode, in this case, the WAIT TIMER register is set to 5 Is never subtracted.

# D-31: It is detected whether or not there is a pulse from the reference signal generator 19 shown in FIG. 1, and if there is a pulse, # D-31.
If not branching to 32, the flow of # D-31 is repeated.

# D-32; 1 is subtracted from the contents of the WAIT TIMER register.

# D-33; It is determined whether or not the content of the WAIT TIMER register has become 0. If 0, the process branches to # D-34, and if not 0, the process branches to # D-31.

In the steps # D-32 to # D-33, the WAIT TIMER register and the reference signal generator 19 are used as the timer for controlling the track feed speed. Therefore, a stable and more accurate clock operation can be performed as compared with a method of forming a timer by subtracting the contents of the WAIT TIMER register according to the outlet of the waveform shaping circuit 22 that shapes the output of the PG coil 21. . That is, the output of the PG coil 21 may include an error due to a cause such as uneven rotation of the magnetic sheet 1, but the output of the reference signal generator 19 has substantially no error. When performing interval recording, it is desirable to stop the rotation of the DC motor 2 during the interval time in order to save power consumption. In the case of performing such an operation, the interval time cannot be elapsed by the method of subtracting the WAIT TIMER register according to the output of the waveform shaping circuit 22, but in the case of performing such operation by the method of the present embodiment Even then, stable clocking operation can be performed.

# D-34; It is judged whether or not the REC execution flag is set, and if it is set, the program that called the subroutine is returned (RTS). If it is not set, #D Branch to −35.

# D-35: It is determined whether the track UP switch 54 is on or not, and if it is on, the head 3-
# D-1 to shift the track being accessed by 1 and 3-2 to the inner circumference side, and #D when it is off.
The flow branches to −36.

# D-36; It is determined whether or not the track DOWN switch 55 is on, and if it is on, the head 3-
The routine branches to # E-1 of the subroutine to shift the track being accessed by 1 and 3-2 to the outer peripheral side, and to # D-37 when it is off.

# D-37; When the PB mode flag is set # D-38
Otherwise, return to the program that called the subroutine.

In the case of a video signal in which a frame is recorded in the same manner as D-6, 17, 18, the field flag is cleared for frame reproduction. After that, the process returns to the program that called the subroutine.

In the above-described example, # D-23, 25, 26 is used regardless of whether or not # D-12 is passed during PB mode.
Since the value set in WAIT TIMER is not changed, if # D-12 is passed for the time to execute one track feed, the track feed speed will be delayed. To match, use # D-
In 27, if you pass # D-12, you can adjust the track feed speed without any problem by subtracting the time required for head feed for one track from WAIT TIMER. Next, the track DOWN switch 55 is turned on. A subroutine that is executed at the time of the description will be described.

Since the steps # E-1 to # E-13 of the subroutine are the same as the steps # D-1 to # D-13 of the subroutine, detailed description thereof will be omitted.

However, since the subroutine shifts the track being accessed by the heads 3-1 and 3-2 to the outer peripheral side when the track DOWN switch 55 is turned on, for example, in # E-1, it is detected whether N = 1. Then, in # E-9, the memory (N-1) battery detects whether "0010", that is, the (N-1) th track is an inner track of the two tracks constituting the frame video signal, and # In E-10, it is detected whether or not the memory (N-2) address is "0011", that is, the (N-2) th track is an outer track of the two tracks constituting the frame video signal. -11 is N
= 2, it is detected whether or not # E-12 and # E-13 are 1
The heads 3-1 and 3-2 for the track are shifted to the outer peripheral side.

Next, referring to FIG. 9, a field / frame switching switch
59, a subroutine called when the REC mode setting switch 51 is turned on will be described.

# J-1; the field / # A-10 shown in FIG.
When it is detected that the frame switching switch 59 is turned on, the flow advances to this step. In this step, if the field flag is set, #J
-2, the flow branches to # J-4 when not set.

When the field flag is set in # J-2; # J-1, the field flag is cleared in this step.

# J-3; It is judged whether the PB mode flag is set or not. When it is set, the flow branches to # J-8, and when it is not set, the flow branches to # J-5.

When it is detected that the field flag is not set in # J-4; # J-1, the field flag is set in this step.

When the PB mode is not set, that is, in the recording mode, and the field flag is cleared in # J-2, the frame recording mode is set, and 10 screens per second are continuously recorded as described in the subroutine ,. I can't. Therefore, when switching from the field mode to the frame mode in the subroutine, if the track feed speed of 10 screens per second is set as the track feed speed, it is necessary to prohibit such switching.

Therefore, according to this embodiment, # J-6,
When the track feed speed of 10 screens per second is set by J-7, the track feed speed setting value is automatically changed to the track feed of 5 screens per second.

# J-5: Load the track feed speed setting value into CPU40.

# J-6; If the track feed speed setting value fetched in # J-5 is 10 screens per second, go to # J-7.
If it is not 10 screens per second, the flow branches to # J-8.

# J-7; Change the track feed speed setting value to 5 screens per second.

# J-8; If the field / frame setting switch 51 continues to be turned on, this switch is repeated, and only when the switch turns from on to off, the step returns to the step shown in # A-1 in FIG.

Next, a subroutine called when the REC mode setting switch 51 is turned on will be described.

# B-1; When it is detected that the REC mode setting switch 51 is turned on in # A-1 shown in FIG. 6, the flow branches to this step, and the PB and LED44A shown in FIG. 3 are turned off. However, the PB mode flag is cleared.

These five steps are # D-3 shown in FIG. 8, respectively.
The description is omitted because it is similar to # D-7.

# B-5-1; This step causes the CPU 40 to control the character generator 84 to temporarily stop the character generation.

# B-5-2: It is determined whether or not it is in the ID setting mode. If it is in the setting mode, the process proceeds to # B-5-3. If not, the process proceeds to # B-6 '.

# B-5-3: The CPU 40 reads the set ID from the RAM 27 and controls the character generator 84 to generate a character pattern. Therefore, the ID is displayed on the monitor 13 by being superimposed on the video signal input from the video signal input terminal 18. Then, the flow proceeds to # B-6 '.

# B-6 '; This step is repeated while the REC mode setting switch 51 is kept on, and when the switch is turned off, the flow branches to # B-7.

# B-7; When the REC mode setting switch 51 is turned off, it is determined whether or not the field flag is set in this step, and when the field flag is set, the process proceeds to # A-1 in FIG. The flow returns to the indicated switch, and when the field flag is not set, the subroutine # J-5 is jumped to # J-6 to # J-.
By executing step 8, when the track feed speed setting value is 10 screens per second, it is automatically corrected to 5 screens per second.
Therefore, when the REC mode is set by the REC mode setting switch 51 and the frame mode is set, the maximum track feed speed setting value is limited to 5 screens per second.

Next, a subroutine called when the PB mode setting switch 53 is turned on will be described with reference to FIG.

# C-1; When it is detected in # A-3 shown in FIG. 6 that the PB mode setting switch 53 is turned on, the flow branches to this step, the REC LED is turned off and the field flag is once set. It That is, different field video signals are recorded in the two tracks accessed by the heads 3-1, 3-2, the PB mode flag is cleared, and the field flag is reset. In this case, if the PB mode setting switch 53 is detected to be turned on and the track being accessed by the heads 3-1 and 3-2 is immediately reproduced, separate field video signals are prevented from being interlaced and reproduced. To do this, the field flag is once set in this step.

# C-2; It is detected whether the memory address is "0011", that is, the track accessed by the head 3-1 is the outer peripheral side of the two tracks in which the frame video signal is recorded. In some cases, the flow branches to # C-3, and when it is not “0011”, the flow branches to # C-5.

# C-3; Memory N + 1 is "0010", that is, head 3-2
It is detected whether the track being accessed is on the inner circumference side of the two tracks in which the frame video signal is recorded, and when it is "0010", it goes to # C-4 and when it is not "0010". The flow branches to # C-5.

Heads 3-1 and 3 in # C-4; # C-2 and # C-3
When it is detected that the frame video signal is recorded in the two tracks accessed by -2, the flow reaches this step, the field flag is cleared and the frame mode is set.

# C-5: The PB and LED 44A shown in FIG. 3 are turned on, the PB mode flag is set, and the reproducing operation is started.

# C-5-1; In this step, the CPU 40 controls the character generator 84 to temporarily stop the character generation. Further, the CPU 40 stores the ID DATA demodulated by the data demodulator 12 in the RAM 27.

# B-5-2: It is determined whether or not the display mode is the ID display mode. If the display mode is set, the process proceeds to # C-5-3. If not, the process proceeds to # C-6 '.

# C-5-3: The CPU 40 reads the ID demodulated by the data demodulator 12 from the RAM 27 and controls the character generator 84 to generate a character pattern. Therefore, the ID is displayed on the monitor 13 by being superimposed on the video signal reproduced from the magnetic sheet. Then, the flow proceeds to # C-6.

# C-6; When the PB mode setting switch 53 is continuously turned on, this step is repeated, and when it is turned off, the process returns to # A-1 via # A-14 shown in FIG.

Next, the subroutine called when the interval time setting switch 57 is turned on will be described with reference to FIG. First, in the subroutine # G-0, the timer T'is initialized to 0 and 7 segments
Interval time Ti is displayed on LED25.

# G-1; When it is detected that the interval time setting switch 57 is turned on in # A-7 of FIG. 6, the timer T'is initialized to 0, and then the flow reaches this step. Further, the flow branches to # G-2 when the 10-key switches 63 to 72 are turned on, and to # G-3 when the 10-key switches 63 to 72 are not turned on.

# G-2: The interval time Ti is changed to the interval time Ti set by the 10 key switches 63 to 72.

# G-3; 10 key switch It is judged whether or not the switches other than 63 to 72 are turned on. When the switches are turned on, # G-
When it is not turned on to 4, the process branches to # G-5.

# G-4: It is detected whether or not the interval time setting switch 57 is turned on, and when it is turned on, # G-1 is turned on, and when it is not turned on, # A-1 shown in FIG. The flow branches to.

# G-5: The above T'is incremented by 1. #G every second
The flow moves to -6.

However, T'is a timer that is incremented by 1 every second, or addition is not performed if 1 second has not passed.

# G-6; It is judged whether T'is 10 or not. If T'is 10, # A-1 shown in FIG. 6 is used. If T'is not 10, # G-1. Branch to # G-1, # G-3,
The loop of # G-5 and # G-6 is repeated, and when T ′ becomes 10, the process returns to # A-1.

Therefore, in the above-mentioned subroutine, when the other switches are not turned on within 10 seconds after the interval time setting switch 57 is turned on, # A-1 shown in FIG.
Return to and the interval time setting is canceled. While executing the subroutine, of course, the interval time Ti is displayed on the 2-digit 7-segment LED 25, but the display of the interval time Ti required when returning to # A-1 in # G-6 is stopped.

In such a subroutine, the interval time Ti
Is set to "0", an external trigger mode is set as the reproduction operation, which is described in the sub-routine and is operated when connecting to a printer, for example.

Next, the subroutine called when the REC switch is turned on will be described with reference to FIG.

# N-1; When it is detected in FIG. 6 # A-2 that the REC switch 52 is turned on, a flow arrives at this step, and it is detected whether or not the PB mode flag is cleared. When it is not cleared, it is in the reproduction mode, so the flow returns to # A-14 shown in FIG. 6 (RTS). When it is cleared, the flow branches to # N-2. Therefore REC
If the mode is not set, recording will not be performed even if the REC switch 52 is turned on.

# N-2: It is determined whether the address N of the memory is "0000", that is, whether the track accessed by the head 3-1 is unrecorded. If not, it is shown in FIG. #A
The flow returns to -14, and if it is unrecorded, # N-3
The flow branches to.

# N-3: The flow branches to # N-5 when it is set by determining whether the field flag is set or not, and to # N-4 when it is not set.

# N-4; This step will be moved when the frame recording mode is set, but if the memory N + 1 address is "0000", that is, the track accessed by the head 3-2 is not recorded. If it is not unrecorded, the flow returns to # A-14 shown in FIG. In such a case, REC and LED44B are blinking in advance.

If such a track has not been recorded, # N-6
The flow branches to.

# N-5: An image signal for one field is recorded on one track on the magnetic sheet 1 by the head 3-1.
At this time, SW6 shown in FIG. 1 is turned off and the output of the character generator 84 is not output to the monitor. In memory N address
0001 is set.

# N-6; When the flow arrives at this step, the frame recording mode is set, so that the video signals for one field are sent to the two tracks on the magnetic sheet 1 for the head 3 respectively.
-1, 3-2 are recorded. 00 at address N
0010 is set at address 11 and N + 1, and SW6
Is turned off. Then, the step motor 24 is driven to shift the heads 3-1 and 3-2 to the inner circumference side by one track.

When executing # N-5 and # N-6, SW2 to SW5 are driven as described in FIG. When recording is executed in # N-6, the CPU 40 reads the ID set from the RAM 27 and outputs it to the data modulator 14 to modulate it into a DPSK signal.
The ID is input to the recording amplifier 16, where it is superposed on the video signal to perform ID recording. However, in the case where the ID display mode is shown in FIG. 20 (c), which will be described later, the ID is not recorded even if data is set. However, DA that indicates inside track, outside track, or field record of the frame
TA is simply recorded together with the video signal. Again
20 # N-5, # N-6 even in the display mode of a) b)
By executing, the SW6 is turned off during recording and the ID DATA signal does not appear on the monitor.

# N-7; REC in progress flag is set and S in FIG.
W6 is turned on.

By executing # N-1 to # N-7, the set ID is generated by the character generator 84, superposed on the video signal, and output to the monitor. Only when REC is being executed. The character signal being made is turned off by SW6 in FIG. 1, and the character disappears. #N
Since SW6 is turned on again at -7, ID DATA is displayed again.

# N-8; The subroutine is called and the head 3-1 is the first
# D-1 when accessing other than 50 tracks,
The flow moves from # D-2 to # D-3. Then # D-3
To # D-14 to execute one track for head 3
Move -1, 3-2. If it is the frame recording mode, the head # 3 is previously set to # N-6 and the head 3-
Since 1 and 3-2 have been moved, even in the frame recording mode, the head 3-1 accesses the track adjacent to the track recorded in # D-14. See also Head 3
When the tracks recorded by -1, 3-2 have been recorded, the REC and LED 44B shown in FIG. 3 blink and display a warning to the user.

Next, the flow branches from # D-15 to # D-19, and # D-
The flow shown in # D-20 to # D-34 is executed via 19.

That is, when the set value of the track feed speed is single, the flow branches from # D-21 to # D-34 and returns to # N-9 according to the REC execution flag set in # N-7 in advance. .

If 2 or 5 screens are set per second, # D-28
The WAIT TIMER register is subtracted only for the time required to record at, and the WAIT TIMER register is down-counted to WA.
When the IT TIMER register becomes 0, the flow returns from # D-33 through # D-34 to # N-9 according to the REC execution flag set in # N-7 as described above.

# N-9: Clear the REC execution flag.

# N-10: This step is similar to # D-20, and the set value of the track feed speed is fetched from the memory.

# N-11: If the set value of the track feed speed is single, then go to # N-12. If not, return to # A-14 shown in FIG.

# N-12: When the track feed speed is set to single, as long as the REC switch 52 is turned on, this step is repeated and the subroutine is executed again so that recording is not performed.

When the track feed speed is set to other than single and the REC switch 52 is turned on, the subroutines are called from # A-1 and # A-2 via # N-11 to # A-14. Flow is executed REC switch 52
As long as is on, recording will continue at the set track feed speed. If the REC switch 52 is turned off, the flow proceeds to # A-14, # A-1, and # A-2, but # A-14
At -2, the subroutine is not called and the continuous recording ends.

Next, the subroutine called when the program setting switch 58 is turned on will be described with reference to FIG.

# H-1; When it is detected that the program setting switch 58 is turned on in # A-8 in FIG. 6, this step is reached and it is judged whether or not the PB mode flag is set. If it is set, the process returns to # H-2, and if it is not set, the process returns to # A-1 shown in FIG. 6 (RTS).
This step is provided to prohibit program setting in the recording mode. That is, in this embodiment, when the program is set, the reproduction mode is selected in advance so that the program is set while confirming the image recorded on the magnetic sheet 1 on the monitor, for example.

Further, by automatically setting the PB mode flag when the program setting switch 58 is turned on, it is possible to automatically perform the operation to the reproduction mode. In this case, a step similar to the one shown in the subroutine
That is, a CALLC for calling a subroutine may be provided instead of the step shown in # H-1.

# H-2: When the program is reproduced in the program track memory shown in FIG. 14 in which the program is stored, the I register indicating the address where the track number to be reproduced next is stored is set to 0.

# H-3: The program reproduction mode flag indicating the program reproduction mode is set and the process returns to # A-1.

Next, the subroutine called when the program track setting step 62 is turned on after the program reproduction mode is set by the subroutine will be described with reference to FIG.

# I-1: It is judged whether or not the program reproduction mode flag is set, and when it is set, the flow branches to # I-2, and when it is not set, the flow branches to # A-1.
Therefore, when the program reproduction mode is not set by the program setting switch 58, the program setting operation is not performed even if the program track setting switch 62 is turned on.

# I-2; register S (# indicating the start address where the program of the program track memory is stored
1 is initialized to S = 0 when the power is turned on (1) and the same content is written in the register M.

# I-3: The data in the program track memory at the address stored in the register M is stored at an address which is larger by 1 than the address. In other words, the data indicating the track number stored in the program track memory is stored at an address which is larger by 1 than the address where the data is stored.

# I-4; The value obtained by adding 1 to the content of the register M is written in the register I.

# I-5: Subtract 1 from the contents of register M.

# I-6; It is determined whether or not the content of the register M is 0. If it is 0, the flow branches to # I-7, and if it is not 0, the flow branches to # I-3.

When the flow of # I-3 to # I-6 is repeated and the content of the register M becomes 0, all the data stored in each address of the program track memory is transferred to the address which is larger by 1. Therefore, when this flow is repeatedly executed and the flow branches from # I-6 to # I-7, no data is stored at address 1 of the program track memory.

# I-7: The number of the track accessed by the head 3-1 is stored in the program track memory address 1. Therefore, the program track setting switch
Turning on 62 causes the head 3-1 to access and program the track number in which the video being reproduced is recorded.

# I-8; 1 is added to the contents of the register S. By executing this step, # I-3 ...
The head address (largest address) where the data of the program track memory moved by executing the flow of # I-6 is stored.

# I-9: If the program track setting switch 62 is on, this step is repeated, and if it is off, the process returns to # A-1.

When the user further sets the program, the track UP switch 54 or the track DOWN switch 55 is turned on to change the track being accessed by the heads 3-1 and 3-2, and the desired track is changed. The program can be set by turning on the program setting switch 62 while checking the reproduced image at the place where the program is reproduced.

Each time the program setting switch 62 is turned on, the data stored in each address of the program track memory shown in FIG. 14 is stored in a larger address by one. Also, during program setting, register S,
The register I has the same contents.

Next, the program setting switch 58 and the program setting for reproducing the program set by turning on the program track setting switch 62 are performed, and the recorded tracks are sequentially set from the track accessed by the head 3-1. A program executed at the time of performing interval reproduction for reproduction will be described with reference to FIGS. 16 to 18.

First, the subroutine called when the start switch 60 is turned on will be described with reference to FIG.

# K-1; When it is detected that the start switch 60 is turned on in # A-11 in FIG. 6, a flow comes to this step and it is detected whether or not the PB mode flag is set. If the mode flag is not set #
When the PB mode flag is set in A-1, #
The flow branches to K-2. Therefore, in this embodiment, if the reproduction mode is not set in advance, the interval reproduction and the program reproduction cannot be performed. Therefore, even if the start switch 60 is accidentally turned on in the recording mode, the interval reproduction and the program reproduction are started. It is possible to prevent being done. If a step similar to the step shown in the subroutine is provided instead of # K-1, the start switch 60 can be set without setting the reproduction mode in advance.
Interval playback program playback can be started immediately by turning on.

# K-2: It is judged whether or not the program reproduction mode flag is set. When it is set, the flow branches to # K-3 when it is not set.
Here, a flow when the program reproduction mode flag is not set, that is, when the interval reproduction is performed will be described.

# K-4; N address of memory is "0000", that is, head 3-
It is determined whether or not the track being accessed by No. 1 is unrecorded. If not recorded, # K-6 If not recorded, #K
The flow branches to -5. Here, first, head 3-1
#K because the track being accessed is unrecorded
-6 The following flow will be described.

According to the present embodiment described below, in the interval reproduction, if the track accessed by the head 3-1 is other than the 49th or 50th track, the head 3 is transferred from the track.
When the track accessed by -1 is the 49th or 50th track, only the tracks that have been recorded sequentially from the first track are reproduced, but between # K-2 and # K-4. If the head 3-1 is inserted with a step for driving the step motor 24 so as to access the first track, only the recorded tracks are reproduced sequentially from the first track.

Therefore, when the head 3-1 is not accessing the first track but is accessing another track, it is very effective to automatically perform interval reproduction from the first track and perform a search. .

# K-6; The automatic track feed flag indicating that interval reproduction is in progress is set.

# K-7: It is judged whether or not the field flag is set, and when it is set, the flow branches to # K-9 when it is set to # K-8.

# K-8; Whether the track being accessed by the head 3-1 is the innermost track or not is discriminated by detecting whether N is 50 or not, and it is detected that it is 50. In this case, the flow branches to # K-10, and when it is not detected as 50, the flow branches to # K-11.

# K-9; It is judged whether or not the track being accessed by the head 3-1 is a track outside by 1 from the innermost circumference by detecting whether N is 49 or not, and 49 is detected. If it is not detected that it is 48 to # K-10, the flow branches to # K-11.

# K-10; In this step, the interval time Ti set by executing the subroutine is "0".
Or not. As will be described later, when the interval time Ti is "0", it means a mode in which the head 3-1 is shifted by a program preset according to an external trigger signal, and the interval time Ti is " When set to 0 ", the flow is # A-1
When it is not set to "0", the flow branches to # K-12.

# K-11; Calls a subroutine, # D-1 to #D
The flow shown in -18 is executed. Since the PB mode flag is set when the subroutine is called in the subroutine, the flow is from # D-2 to # D-9.
The track accessed by the head 3-1 at # K-4, or the track on the outer peripheral side of the frame and the inner peripheral track of this track is the inner peripheral track of the two tracks for recording the frame video signal. And head 3-1 is the first
When it is determined that 49 tracks are not accessed, the heads 3-1 and 3-2 are shifted to the inner circumference side by two tracks by # D-12 and # D-13, and when it is not determined, # D- 13
As a result, the heads 3-1 and 3-2 are shifted to the inner peripheral side only for one track. If the frame video signal is recorded in the tracks accessed by the heads 3-1 and 3-2, the field flag is cleared and the flow moves from # D-19 to # K-14.

# K-12; Calls a subroutine # E-1 to # E-1
3 and the flow shown in # D-14 to # D-19 is executed,
If the frame video signal is recorded in two tracks, the outer track adjacent to the track accessed by the head 3-1 in # K-4 and the other track located on the outer track, the head 3-1 is recorded. 3-2 is # E-12, # E-13
Is shifted to the outer peripheral side by 2 tracks, and otherwise, only one track is shifted to the outer peripheral side by # E-13.

Similarly to # K-11, if the frame video signal is recorded in the track accessed by 3-1 and 3-2, the field flag is cleared and the flow proceeds from # D-19 to #K.
Move to -13.

# K-13: Whether or not the track being accessed by the head 3-1 is the outermost track is determined by detecting whether or not the content of the register N is 1, and it is detected that it is 1. When it is detected, the flow branches to # K-14, and when 1 is not detected, the flow branches to # K-12. Therefore, when the flow branches to # K-12 in # K-8 or # K-9, that is, when the head 3-1 is accessing the 49th track or the 50th track, # K-12, #
By repeating the steps of K-13, the head 3-1
Are controlled to access the first track.

# K-14: Clear the automatic track feed flag.

As described above, when the flow of # K-4 to # K-14 is executed and the flow branches from # K-4 to # K-5, the head 3-1 is the track on which the video signal is recorded. Is accessed, and a track in which no video signal is recorded is skipped without being substantially reproduced.

Further, by executing the flow of # K-4 to # K-14, when the flow branches from # K-4 to # K-5, the head 3
When the frame video signal is recorded in the two tracks accessed by -1, 3-2, the field reproduction mode is automatically set because the field flag is cleared in # D-18. . Also, head 3-1,
The field reproduction mode is automatically set when the field video signal is recorded in the track 3-2 being accessed. Therefore, during interval reproduction, the most appropriate reproduction mode is automatically set according to the recording method of the video signal.

# K-5; The interval time Ti set in the subroutine is fetched from the memory into the register T'of the CPU 40.

# K-15; The interval time Ti is "0" as in # K-10.
If it is "0", the flow branches to # K-17, and if it is not "0", the flow branches to # K-16. Here, assuming that the external trigger mode is not set, # K-16
The following description will be given.

# K-16: The timer 1 starts counting time and proceeds to # K-18.

# K-18: It is detected whether or not the timer 1 has timed for one second, and the flow branches to # K-19 when it is timed and to # K-20 when it is being timed.

# K-20: It is detected whether or not the step switch 61 is turned on, and when it is turned on, the flow branches to # A-1, and when it is not turned on, the flow branches to # K-21. When the flow branches to # A-1, the steps # A-1 to # A-12 are executed again. Therefore, when the step switch 61 is turned on in the normal state, the flow is # A-. The subroutine will be called from 12. The subroutine will be described below with reference to FIG.

# M-1: It is detected whether or not the program reproduction mode flag is set, and if it is not set, # A-14.
If it is set, the flow branches to # M-2.

# M-2: It is detected whether the program reproduction execution flag is set or not, and if it is set, the flow branches to # M-3, and if not set, the flow branches to # M-4.

# M-3: The contents of register I are made the same as the contents of register S.

# M-4: The register S is set to 0, and then # M-3 is executed.

This subroutine will be described in more detail in the program reproduction mode. The following will be described in detail after # K-21.

# K-21; It is detected whether the track UP switch 54 is on, and when it is detected that it is on, a subroutine is called and the heads 3-1 and 3-2 are shifted to the inner peripheral side and turned on. If it is not detected, the flow branches to # K-22.

# K-22: It is detected whether the track DOWN switch 55 is on, and when it is detected that it is on, a subroutine is called, and the heads 3-1 and 3-2 are shifted to the outer peripheral side and turned on. If it is not detected, the flow branches to # K-18.

# K-19: Subtract 1 from T '.

# K-23; The flow branches to # K-24 when T'is "0" and to # K-16 when T'is not "0".

Therefore, by executing the above # K-15 to # K-23, the track UP switch 5 is activated during the interval reproduction.
4. By turning on the track DOWN switch 55, it is possible to reproduce the image recorded on the track adjacent to the track being reproduced. In that case, by continuing to turn on the switch 54 or the switch 55, it is possible to automatically and sequentially update the tracks being played back in accordance with the track feed speed set in the subroutine. You can also easily play the video.

Also, track UP switch 54, track DOWN switch 55
When the video recorded on the track adjacent to the track being played by turning on the switch is turned on, in this embodiment, the interval time Ti of the track being played before the switches 54 and 55 are turned on. When the remaining time is reproduced, the flow is from # K-23 to #K.
It moved to −24 and was updated to the reproduction of a new track,
As shown by the dotted line in the figure, if the flow is jumped to # K-5, the interval time T'is reset and the image updated by the switches 54 and 55 can be surely observed for a certain period of time. You can also

# K-24: It is detected whether or not the program reproduction mode is set when updating the track to be reproduced after the end of the interval time T ', and when it is set, it is set to # K-3. If not, the flow branches to # K-6.

Next, the routine that branches when the program reproduction mode flag is set in # K-2 will be described with reference to FIG.

# O-1; It is detected whether or not the content of the register S is “0”, and when “0” is detected, # A-1 is detected. The flow branches to O-2. As described above, the register S stores the start address of the program in the program track memory and the content of the register S is "0" when no program is stored in the program track memory. Therefore, when the value is "0", the process returns to A in FIG.

# O-2; It is detected whether or not the content of the register I is "0", and if "0" is detected, go to # O-3. If it is detected that it is not "0", The flow branches to # O-3.

As described above, the register I stores the address of the track memory in which the track number to be reproduced next is stored when the program reproduction is executed. When the program reproduction is executed, it is also shown in # O-14 described later. Every time one step program reproduction is executed, 1 is subtracted. Therefore, the flow branches to # O-2, and the register I is detected as "0" because the program is set, the register S is not "0", and the program reproduction step is executed once. It shows that. In other words, when the program playback is executed normally, #O
-3, the flow branches to # O-5 while the program reproduction is generally executed.

# O-3; Interval time set by the subroutine
Ti is taken in and it is detected whether or not the interval time Ti is "0". If "0", the flow returns from the routine to # A-1 to end the program reproduction operation.

Therefore, in the external trigger mode set by setting the interval time to "0", the program reproduction operation is stopped when the program reproduction is executed once.

Further, the flow moves to # O-4 during normal program reproduction when the interval time Ti is set to a value other than "0".

# O-4: Write the contents of register S to register I.

The program operation is started again.

# O-5: The data (I) of the address of the program track memory set in the register I (the data written in the address set in the register I of the program track memory is shown in parentheses) read out.

# O-6; The data (I) is subtracted from N indicating the track number currently accessed by the head 3-1. If it is less than "0", go to # O-7. If it is less, go to # O-8. The flow branches.

# O-7: The field flag is set. This set is for prohibiting head feed in the frame mode as in # D-8.

# O-8: Heads 3-1 and 3-2 are shifted in the outer peripheral direction by one track.

# O-9: It is detected whether the data (I) is equal from N indicating the track number being accessed by the head 3-1. If they are equal, the data (I) is not equal to # O-10, that is, the data is more than N indicating the track number. If (I) is larger #
The flow branches to O-11.

# O-10: Heads 3-1 and 3-2 are shifted inward by one track.

; Steps similar to # D-16, # D-17, # D-18, and automatic frame reproduction and field reproduction depending on whether the video signal recorded by such a step is a frame video signal or a field video signal Is done.

By repeating # O-6 to # O-10, the head 3-
1 is controlled to access the track being programmed into the program track memory.

# O-14: Subtract I from register I.

# O-15; The program reproduction in-execution flag is set. By this step, the flow can be branched by determining whether or not the program reproduction mode flag is set at # K-24. Then the flow is #
Jump to K-5.

Therefore, when the routine branches to # K-3, it is first determined whether or not the reproduction program is actually set, and further it is determined whether or not the external trigger mode is set, and the external trigger mode is set. While the program is running, the program is executed only once, otherwise the program is repeatedly played.

Next, the flow when the external trigger mode is set will be described. When the external trigger mode is set, the flow branches from # K-15 to # K-17.

# K-17 '; It is detected whether or not the printer connected as an external device is busy (printing operation is being executed). If it is busy, it is # A-1. If it is not busy, # K- The flow branches to 18 '.

# K-18 '; A print start signal is sent to the printer as an external device. The print start signal is executed by setting the signal level of the terminal connected to the printer to H level.

# K-19 '; wait 150 msec # K-20'; go to # K-21 'when the printer is busy,
If it is not busy, the flow branches to # K-24.

# K-21 ': It is detected whether or not the stop switch 61 is turned on, and when it is not turned on, the flow returns to # K-20', and when it is turned on, the flow returns to # A-1.

If the printer connected as the external device is busy when executing the above # K-17 'to # K-21', the flow returns to # A-1 as described above, and another switch is restarted. The flow shown in FIG. 16 is repeated until it is turned on. If the start switch 60 is turned on again while repeating the flow shown in FIG. 16, the above-mentioned flow is repeated and # K-17 'is executed again.

When the printer is not connected as an external device, the terminal to which the signal from the busy signal output terminal of the printer 13 'shown in FIG. 1 is input at # K-17' is opened to the H level. Therefore, if the printer or other device is not connected even though the external trigger mode is set, the tracks accessed by the heads 3-1 and 3-2 continue to be reproduced, and the tracks being reproduced are reproduced. Is not updated.

Also, if a printer is connected as an external device and the printer is not busy, then # K-17 'to # K-18'
If the flow has proceeded to step 1, the printer operation is started after sending the print start signal to the printer and waiting for 150 mspc shown in # K-19. If the printer becomes busy, does the operation of the printer end? , # K-20 ', # K-21' until the stop switch 60 is turned on.
When the printer operation is completed, the flow branches from # K-20 'to # K-24, and it is determined whether program reproduction is set by detecting whether the program reproduction mode flag is set. Determine. If program playback is set, the flow branches to # K-3 described above, and if program playback is not set, the flow branches to # K-6. Also stop switch
When 60 is turned on, it is as described in the above flow.

If the external trigger mode is selected while the program reproduction is set, the program reproduction operation is stopped when the program reproduction is executed once as described in # O-3.

Further, according to the present embodiment, even when the external trigger mode is selected and the program reproduction is not set, the head # 3-1 is provided because the # K-10 is provided.
When the reproduction from the accessed track to the final track in 3-2 is sequentially performed, the reproduction operation is stopped.

Therefore, in the external trigger mode, the printer is used as an external trigger device because the playback operation is stopped after the normal playback is performed regardless of whether the program playback is set or not. When is used, only one printing is performed.

On the contrary, when the program is not set to the external trigger mode and the program is set to play, even if the program is not set to play, the playback is performed from the beginning again after the playback is performed in the predetermined order. Is done. Therefore, when the reproducing apparatus is used in a mode other than the external trigger mode, so-called endless reproduction can be performed because the reproduction is repeated in a predetermined order.

Further, although the printer is shown as the external trigger device in the present embodiment, for example, a device having an electric transmission function may be used, or another device may be used as long as it is a device that processes a reproduced signal.

Next, the case of setting the ID will be described.

When the 10-key switches 63 to 72 are turned on in the flow of, the flow branches to the subroutine shown in FIG.

# R-1; If the PB mode flag is set, the process branches to # R-10 and returns to the flow chart. Therefore, except in the recording mode, even if the 10 key is turned on, substantially nothing is executed in this subroutine. If the PB mode flag is not set, that is, if it is the recording mode, the flow is # R-
Branch from # 1 to # R-2.

# R-2; Here, the ID setting mode, that is, the ID is superimposed on the video signal, and it is determined whether or not it is the monitoring mode. The mode setting method will be described in detail with reference to FIG. If you are not in this mode #
Flow chart #A shown in FIG. 6 branched to R-10
Return to -1. Also, when in this mode,
Branch to # R-3.

# R-3; RAM 27 for memorizing a set position indicating where on the monitor the ID set here is to be displayed
The CPU 40 reads the set position from the register P, and the data corresponding to the ON switch of the 10 key switches 63 to 72 is written to the address corresponding to the set position of the RAM 27. Then, the CPU 40 displays the data on the monitor B according to the set position read in by the character generator.
Control 84.

# R-4; Here, the ten-key switches 63 to 72 are kept waiting until they are once turned off. If the turned on switch is turned off, the flow proceeds to # R-5.

# R-5; Here, the setting position of the data other than the date in the ID is 11 points from 0 to 10 as shown in FIG. 21, so if the register P is equal to 10 here. Branch to # R-6, otherwise branch to # R-7.

# R-6; Here, 0 is set in the register P and the setting position of DATA is initialized.

# R-7; Here, 1 is added to the value of the register P and the DATA setting position moves to the next setting position.

# R-7-1: The data at the position stored in the register P blinks (blinks).

# R-8; In this step, 10-key switch 63-72
Is turned on, and if it is turned on, the process branches to # R-3, and the ID set by the 10-key switch is displayed on the motor 13 according to the above-described flow. If it is not turned on, the process branches to # R-9.

# R-9: Here, it is determined whether or not the switches other than the 10-key switches 63 to 72 are turned on. If not, the process branches to R-8. #R if turned on
Branch to -11.

# R-9-1: Stop blinking of the ID displayed on the monitor. The flow proceeds to # R-10.

# R-11; Here, O is set in the register P at the ID setting position, the ID setting position is initialized, and the process proceeds to # R-9-1.

Return to the flow of # R-10 ;.

As described above, when the PB mode flag is not set and the ID setting mode, that is, the mode in which the set ID can be monitored, the data corresponding to that switch is turned on every time the 10 key switches 63 to 72 are turned on. CPU40
Control the character generator 84 to generate the character at a position defined by the register P.

Next, the ID switch 73 will be described.

The subroutine shown in FIG. 20 is called from the flow shown when the switch 73 is turned on. Here, the subroutine will be described.

# Q-1; Here, it is determined whether or not the PB mode flag is set. If it is set, the process branches to # Q-2, and if not, the process branches to # Q-7.

# Q-2; Here, whether or not the ID display mode is set, that is, I
It is determined whether or not D is a mode in which it is superimposed on the video signal and output on the monitor. If the display mode is the ID display mode, the process branches to # Q-4. If not, the process branches to # Q-3.

# Q-3; Here, the CPU 40 controls the character generator 84 to stop the display of the ID output from the generator 84. From here, the flow proceeds to # Q-6.

# Q-4; Here, the CPU 40 uses the RAM 27 as the CP for the reproduced ID.
Captured in U40, the flow proceeds to # Q-5.

# Q-5; Here, the CPU 40 controls the character generator 84 based on the reproduced ID, and outputs the reproduced ID as a character pattern from the character generator 84 as shown in FIG. 21 (a). Then, the flow proceeds to # Q-6.

# Q-6; Here, when the switch 73 is turned on, there is a wait, and when it is turned off, the flow proceeds to the next step and returns to the step.

# Q-7; When the PB mode flag is not set and the recording mode is set, it is determined whether or not the ID setting mode is set. That is, when the ID is in a mode in which the character generator 84 outputs the character pattern as a character pattern by superimposing it on the video signal,
The flow proceeds to Q-9. If not, the flow proceeds to # Q-8.

# Q-8; Here, if it is determined whether or not the character "ID" is in the mode output by the character generator 84, go to # Q-10. If not, go to # Q-11. The flow proceeds.

# Q-9; In this step, the CPU 40 controls the character generator 84 to stop the display of the ID, and the two-character pattern "ID" is generated by the character generator 84 as shown in FIG. 21 (b). Then switch to "ID" character display mode. Then the flow is #Q
Go to -6. That is, when the ID switch 73 is turned on in the ID setting mode, the "ID" character display mode is set.

# Q-10; In this step, the CPU 40 controls the character generator 84 to stop the display of all the character patterns as shown in FIG. 21 (c). Then, the flow proceeds to # Q-6.

# Q-11; When the flow reaches this step, neither the ID setting mode nor the "ID" character display mode, that is, the mode in which the monitor display of the ID is stopped, the CPU 40 reads R.
The set ID is taken in from AM27 and the character generator 84 is controlled, and the set ID is output from the character generator 84 as a character pattern as shown in FIG. 21 (a). That is, the ID setting mode is set by this step. Then, the flow proceeds to # Q-6.

As described above, every time the ID switch 73 is turned on, the ID display format is written. That is, each time the ID switch 73 is turned on in the playback mode, the playback ID DAT
The ID display mode in which A is superimposed on the video signal for monitoring and the ID non-display mode in which playback ID DATA is not output are repeated. That is, specifically, as shown in FIG. 21 (a).
The ID non-display mode shown in the ID display mode (c) is repeated. In the record mode, the ID switch 73 displays the ID setting mode that displays all the IDs to be set, the “ID” character display mode that displays only the “ID” character, and the mode that does not display the ID on the monitor. It will switch repeatedly each time it is turned on. That is, specifically, the modes shown in FIGS. 21 (a), (b), and (c) are repeatedly switched. The display of the ID in the recording mode will be further described below. FIG. 21 (a) in the recording mode,
When the video signal is recorded in the mode shown in (b), the video signal is recorded together with # N-5 and # N-6 in FIG.
The ID is modulated by the DPS, frequency-multiplexed with the video signal, and recorded. When the video signal is recorded in the mode shown in FIG. 20 (c), the ID data is not recorded. However, DATA indicating inside or outside of the frame or field recording is always blackened with the video signal.

That is, in the present embodiment, the monitor 13 is set in both the recording mode and the reproduction mode depending on the number of times the ID switch is pressed.
You can switch the display related to ID.

Further, in this embodiment, in the recording mode for recording the ID together with the video signal, there are an ID setting mode for performing the display shown in FIG. 21 (a) and an "ID" character display mode for performing the display shown in FIG. 21 (b). The reason why such two display modes are provided will be described. That is, as the ID, the date and 11-digit number can be set, but FIG. 21 (a)
If you try to display all of the ID information as shown in, it will occupy a considerable area on the screen of the monitor 13 and it may interfere with the observation of the image.
A display mode as shown in FIG. 21 (b) is provided to solve this problem.

Next, a method of displaying the reproduced ID in the reproduction mode will be described. That is, a display method in the case of reproducing the ID recorded together with the video signal such that the mode shown in FIGS. 21A and 21B in the recording mode is set by the ID switch 73 will be described. In the reproducing mode, when the head is moved to a new track, the ID recorded in the track is reproduced on the monitor 13. This is the data demodulator 12 shown in FIG.
The ID reproduced by is demodulated, the output is read by the CPU 40, and the character generator 84 is driven. The ID read by the CPU 40 here is RAM 27 by the CPU 40.
Will be held in. For the display of such ID, see
Although described with reference to FIG. 21 (a), in this embodiment, RA
The following I) and II) are displayed as the display mode of the characters stored in M27.
It has two modes shown in.

I) The first display mode in which only the date is set as the ID data, and the recorded ID is played back without setting any other data.

II) The second display mode when the recorded ID with both the date and other numerical data set as ID DATA is played back.

The display of ID in I) is shown in FIG. 22 (a).

The display of ID in II) is shown in FIG. 22 (b).

That is, the display for I) displays only the date in the lower right corner on the monitor, and for II), the date and other data are displayed in the lower right corner on the monitor. Therefore, the ID information is always displayed in the lower right corner of the monitor screen, and it can be prevented as much as it can interfere with the video signal. Further, in the present embodiment, the display is made in the lower right corner of the screen, but it may be displayed at any corner of the screen.

To perform this operation, the data demodulator of FIG.
After reading the 12 output signals with the CPU 40, it is only necessary to generate characters after confirming that all data other than the year, month, and day are not set. That is, the CPU 40 sets the character generator 8 so that the character generation position is different from that in the above I) and II).
Control 4

Further, even when it is determined that the data other than the date is not the data recorded by the apparatus, the display shown in FIG. 22 (b) is performed.

This can be identified by recording a well-known check code as ID DATA.

Next, the case of setting the date as the ID will be described. When the year setting switch 74 is turned on, the flow jumps to the subroutine shown in FIG.

# S-1; If the PB mode flag is set here, the flow advances to # S-14 and returns to the flow of. If not set, proceed to # S-2.

# S-2: Here, it is determined whether or not it is the ID setting mode, that is, the mode in which the ID data is superimposed on the video signal and output to the monitor or the printer. If it is not in this mode, the process proceeds to # S-14 and returns to the flow. If in this mode, the process proceeds to # S-3.

# S-3; Here, the 10-digit digit of the year-setting position on the monitor 13 blinks. Is the blinking of the 10-digit digit of the year-setting position the character at the position shown in Fig. 24 (a)? This means blinking, which is done by the CPU 40 controlling the character generator 84 to generate or not generate the character at this position. This is done by well-known interrupt processing. Then, the flow proceeds to # S-4.

# S-4; Here, there is a waiting period until the switch 74 is turned off.
When the switch 74 is turned off, the flow proceeds to # S-5.

# S-5; Here, it is determined whether or not the 10-key switches 63 to 72 are turned on. When the 10-key switch is turned on, the flow proceeds to # S-6. Otherwise #S
Go to -12.

# S-6; Here, the CPU 40 writes the input data by the 10-key switch to the RAM 27, and is the year setting position, FIG. 24 (a).
A character pattern is generated by controlling the character generator 84 at the position indicated by. Then the flow is #S
Go to -7.

# S-7: Blink the first digit of the year setting position. This means that the character at the position shown in FIG. 24 blinks. The blinking is executed by the CPU 40 controlling the character generator 84. The flow proceeds to # S-8.

# S-8; Here, wait until the 10-key switch is turned off. When the 10-key switch is turned off, the flow proceeds to # S-9.

# S-9; Here, it is determined whether or not the 10-key switch is turned on. If it is turned on, the flow is # S-10.
Otherwise, proceed to # S-13.

# S-10; CPU 40 when key switch is turned on
Is the 1st digit of the year setting position, which is the first digit of the year setting position.
The character generator 84 is controlled to generate a character pattern at the position indicated by. Then, the flow proceeds to # S-11.

# S-11: The character blinking at the year setting position is established by the CPU 40 controlling the character generator 84. This allows the user to know that the year setting has been completed. The flow proceeds to # S-14.

# S-12; If the 10-key switch is not turned on in # S-5, it is determined whether or not the switch other than the 10-key switch is turned on. If it is not turned on, the flow branches to # S-5 and the steps of # S-5 and # S-12 are repeated. If the switch other than the 10 key is turned on, the flow is changed to # S-11. move on.

# S-13; Here, it is determined whether or not the switches other than the 10 key are turned on. If it is not turned on, the flow branches to # S-9, and if it is turned on, # S-11.
Branch to. Therefore, the blinking of characters at the year setting position continues by repeating the steps # S-9 and # S-13 until the switches other than the 10-key switch are turned on, prompting the user to set the year by the 10-key switch.

# S-14; ID if the PB mode flag is set
In the setting mode, if the blinking is stopped by # S-11, the flow returns to by this step.

As described above, when the year setting switch 74 is turned on, the 10th digit of the year setting position starts blinking to notify the operator of the position where the data is set. Here, by inputting a number with the 10-key switch, the data input to the blinking position is generated by the character generator 84 as a character pattern, and the CPU holds the data in the RAM 27. When the setting of the 10th digit is completed, the number at the 1st digit starts blinking, and DATA is set at this position in the same manner. Here, when the setting of the first digit is completed, the year setting mode ends and the flow returns to the process shown in, but the process may proceed to the flow shown as it is to enter the month setting mode.

Next, referring to the subroutine shown in FIG. 25,
The setting of DATA is described in detail.

In the above flow, when the switch 75 is turned on, the subroutine is called to enter the month data setting mode.

# T-1; If the PB mode flag is set here, the flow advances to # T-16 to return to the flow. If the PB mode flag is not set, the flow proceeds to # T-2.

# T-2; Here, it is determined whether or not it is the ID setting mode, that is, the mode in which the ID data is superimposed on the video signal and output to the monitor or the printer. If it is not in this mode, the process proceeds to # T-16 and returns to the flow. In this mode, the process proceeds to # T-3.

# T-3: Here, the ten-digit number at the month setting position on the monitor is blinked. The 10-digit digit blinking at the month setting position means that the character at the position shown in Fig. 24 (a) blinks. This is done by the CPU 40 controlling the character generator 84 to cause or not to generate a character. Then, the flow proceeds to # T-4.

# T-4; Here, there is a waiting period until the month setting switch 75 is turned off. When the switch 75 is turned off, the flow proceeds to # T-5.

# T-5; Here, it is determined whether or not the 10-key switches 63 to 72 are turned on. If the 10-key switch is turned on, the flow proceeds to # T-6, and if not, proceeds to # T-13.

# T-6; Here, it is determined whether or not the data input by the 10-key switch is 2 or more. If it is 2 or more, the flow proceeds to # T-14, otherwise, #T.
Go to -7. That is, in the case of setting the month, the flow is branched according to the number set in this step in order to accept the one-digit number only when the first input number is "1" or "0".

# T-7; Here, the CPU 40 writes the input data to the RAM 27 and controls the character generator 84 to generate the character pattern at the position shown in (a) of FIG. 24, that is, at the position blinked in # T-3. Let The flow proceeds to # T-8.

# T-8; Here, blink the first digit of the month setting position. This means that the character at the position shown in FIG. 24 (a) blinks. The flow proceeds to # T-9.

# T-9; Here, wait until the 10-key switch is turned off. When the 10-key switch is turned off, the flow proceeds to # T-10.

# T-10; Here, it is determined whether or not the 10-key switch is turned on. If it is on, the flow is # T-
11. If not, proceed to # T-15.

# T-11; Here, the CPU 40 stores the data input by the 10-key switch in # T-5 or # T-10 in the RAM 27.
, And the character generator 84 is controlled to generate a character pattern at the position shown in FIG. 24, which is the first digit of the month setting position, and then the flow proceeds to # T-12. When # T-14 is branched to this step, by executing # T-14 and # T-11, the data input by the 10-key switch in # T-5 is displayed on the 1st digit and the 10th digit is displayed. "0" is displayed on the digit.

# T-12: The blinking of the data at the month setting position is stopped, and the completion of the month setting is displayed. The flow proceeds to # T-16.

# T-13; This step branches if the 10-key switch is not turned on in # T-5. Here, it is determined whether or not the switch other than the 10 key is turned on. If it is not turned on, it branches to # T-5, and if it is turned on, it branches to # T-12. That is, until the 10 key switch or other switches are turned on, # T-5, #
The flow of T-13 is repeated. The flow branches to # T-6 when the 10-key switch is turned on, and the flow branches to # T-12 when a switch other than the 10-key switch is turned on.

# T-14; This step is branched when it is determined in # T-6 that the input data is "2" or more.
Here, the CPU 40 writes the data “0” in the RAM 27 and controls the character generator 84 at the tenth digit at the month setting position to generate the character pattern “0”. The flow proceeds to # T-11.

# T-15; Here, it is determined whether or not any switch other than the 10 key is turned on. If not turned on, # T-
If it is turned on, it branches to # T-12.

Return to the flow of # T-16 ;.

As described above, when the switch 75 is turned on, the 10th digit at the set position of the month blinks first, and thereby the position where the data to be input with the 10-key switch is to be set is first shown. If two or more data are input, "0" is automatically set to the tenth digit and the input data is set to the first digit. Of course, if there is an input of 1 or less, it will be input to the 10th digit and blinking will move to the 1st digit, and the data entered with the 10 key will be set to the 1st digit. Nor. Therefore, according to the present embodiment, it is possible to perform a simple month setting by utilizing the fact that when setting the month, 2 or more will not be set in the 10th digit.

Further, in # T-3, only the 10th place digit is blinked here, but it is also possible to blink together with the 10th place digit and the 1st place digit here.

Further, when the setting of the next one digit is completed, the flow returns to in this example, but it is also possible to proceed to the subroutine shown in FIG. 26 and enter the day setting mode.

Next, the data setting of the day will be described in detail with reference to FIG. When the switch 76 is turned on in the flow of, the day data setting mode is called and the flow jumps to.

# U-1; If the PB mode flag is set here, the flow proceeds to # U-16 and returns to the flow of. If the PB mode flag is not set, the process proceeds to # U-2.

# U-2; Here, it is determined whether or not the mode is the ID data SET mode, that is, the mode in which the ID data is superimposed on the video signal and output to the monitor or printer. If not in this mode, the process proceeds to # U-16 and returns to the flow. If in this mode, proceed to # U-3.

# U-3; Here, blink the 10-digit digit of the day setting position on the monitor. The blinking of the 10-digit digit of the month setting position is the blinking of the character at the position shown in Fig. 24 (a). Means to do. This is performed by the CPU 40 controlling the character generator 84 to generate or not generate a character. Then
The flow proceeds to # U-4.

# U-4; Here, there is a waiting period until the date setting switch 76 is turned off. When the switch 76 is turned off, the flow is # U-5.
Proceed to.

# U-5; Here, it is determined whether or not the 10-key switches 63 to 72 are turned on. If the 10-key switch is turned on, the flow proceeds to # U-6. If not, #U
Go to -13.

# U-6; Here, it is determined whether or not the input data is 4 or more by the 10 key switch. If it is 4 or more, the flow proceeds to # U-14, and if not, it proceeds to # U-7. That is, when setting the month, the first entered number is "3",
The flow is branched according to the number set in this step in order to receive the digit of the first digit only in the case of "2", "1", "0".

# U-7; Here, the CPU 40 writes the input data to the RAM 27 and controls the character generator 84 to move the character pattern to the position shown in (a) of FIG. 21, that is, to the position where the character pattern is blinked in # U-3. generate. The flow proceeds to # U-8.

# U-8; Here, blink the first digit of the day setting position. This means that the character at the position shown in FIG. 24 (a) blinks. The flow proceeds to # U-9.

# U-9; Here, wait until the 10-key switch is turned off. When the 10-key switch is turned off, the flow proceeds to # U-10.

# U-10; Here, it is determined whether or not the 10-key switch is turned on. If it is on, the flow is # U-
11. If not, proceed to # U-15.

# U-11; Here, the CPU 40 writes the data input by the 10-key switch in # U-5 or # U-10 to the RAM 27, and sets the character generator at the position shown in FIG. 24, which is the first digit of the date setting position. Control 84 to generate a character pattern, then flow proceeds to # U-12. When # U-14 is branched to this step, by executing # U-14 and # U-11, the data input by the 10 key switch in # U-5 is displayed on the 1st digit. "0" is displayed in the place digit.

# U-12: The blinking of the data at the date setting position is stopped and the completion of the date setting is displayed. The flow proceeds to # U-16.

# U-13; This step is branched if the 10-key step is not turned on in # U-5. Here, it is determined whether or not the switch other than the 10 key is turned on.
If it is not turned on, it branches to # U-5, and if it is turned on, it branches to # U-12. That is, # U- until the 10 key switch or another switch is turned on.
The flow of # 5 and # U-13 is repeated. The flow branches to # T-6 when the 10-key switch is turned on, and the flow branches to # U-12 when a switch other than the 10-key switch is turned on.

# U-14; This step is branched when it is determined in # U-6 that the input data is "4" or more.
Here, the CPU 40 writes the data “0” in the RAM 27 and controls the character generator 84 to generate the character pattern “0” at the tenth digit at the month setting position. The flow proceeds to # U-11.

# U-15; Here, it is determined whether or not any switch other than the 10 key is turned on. # U- if not turned on
If it is turned on, it branches to # U-12.

Return to the flow of # U-16 ;.

As described above, when the switch 76 is turned on, the tenth digit at the set position of the day blinks, so that the position at which the data to be input by the 10-key switch should be set is first indicated. If 4 or more data is input, "0" is automatically set to the 10th digit and the input data is set to the 1st digit. Of course, if there are 3 or less inputs. Needless to say, in the case of 10th digit, the blinking position moves to the 1st digit and the data input by the 10th key is set to the 1st digit. According to this, when setting the day, it is possible to set a simple day setting by utilizing the fact that 4 or more is not set to the 10th digit.

In # U-3, only the 10th place digit is blinked here, but it may be blinked together with the 10th place digit and the 1st place digit here.

In the present embodiment described above, the display is blinked to indicate the set position, but the set position may be indicated by another method such as changing the luminance or changing the color.

Next, the erase sequence will be described. When erasing is performed, the erase execution switch 78 and the erase standby switch 77 shown in FIG. 1 are used. That is, when erasing is performed, the switch 77 is set to the standby state of erasing in advance, and then the erasing is performed only when the erasing execution switch of the switch 78 is turned on. Further, the erasing includes a mode in which a plurality of tracks are continuously erased and a mode in which only a single track is erased. The above operation will be described in detail below based on the flow chart shown in FIG. In the flow chart of FIG. 1A,
When the switch 77 is turned on, the flow calls a subroutine and proceeds to # V-1. Here, the standby state for erasing is set, but at this time, "FF" is set in the buffer memory E for storing the number of erasing tracks. Also, in the 2-digit 7-segment LED 25 displaying the track number, the track number accessed by the head 3-1 is lit at a cycle of about 2 Hz.
Flashes repeatedly without lighting. In other words, the blinking of the track number display LED (2 Hz cycle) allows the operator to confirm that the erase standby mode has been set.

That is, according to the method of the present embodiment, it is not necessary to use such a dedicated display element as compared with the method of using a dedicated display element for indicating that it is in the standby state for erasing, and the track number is displayed. By changing the display form of the display unit, the standby state for such erasure is displayed, so that the track number to be erased can be easily recognized. Also, in this embodiment, 7-segment LED2
Although the standby state for erasing is displayed by blinking the display of 5, it is of course possible to use another liquid crystal or the like as the display element, and in addition to blinking, the display color and brightness can be changed. Alternatively, various methods are possible, such as changing the form of the displayed character.

In addition, if information other than the display for displaying the track number, for example, a display for displaying the number of empty tracks is provided, by changing the display mode of the display as described above, the standby state for erasing You may make it display that there is.

Next, the flow proceeds to # V-2.

# V-2; Here, it is determined whether or not the PB mode flag is set, and if it is set, the flow proceeds to # V-4, and if not, it means that the switch 77 is turned off. After confirmation, the flow proceeds to # V-3.

# V-3; Here, the above-mentioned subroutine for setting the reproduction mode is called, the reproduction mode is set, and the flow proceeds to # V-4. Therefore, when the erase standby switch 77 is turned on, # V-2. , # V-3, the reproduction mode is always set and the erase standby state is set.

# V-4: Here, it is determined whether or not the switch 78, that is, the erase execution switch is turned on. If it is turned on, the flow proceeds to # V-4-1. If not, the flow proceeds to # V-15.

# V-4-1: Here, the branch destination of this step is determined by a switch which is prepared in advance in a case (not shown) of the magnetic sheet 1 and which determines the presence or absence of a claw. That is, this claw has a function of an erroneous erasure prevention claw, and it is promised in advance not to perform erasure when the claw is folded. Therefore, if the erroneous erasure prevention is set, the flow proceeds to # V-18. If not set, the flow proceeds to # V-5.

# V-5; In this step, it is determined whether or not the value set in the buffer memory E (hereinafter referred to as E) for storing the number of erase tracks is "0". The buffer memory E is preset to "FF" in # V-1, but the set value can be changed in # V-15 described later. If the value set in the buffer memory E is "0", the flow proceeds to # V-18, and if not, the flow proceeds to # V-5-1. Then # V-5
1 will be explained.

# V-5-1: In this step, it is judged whether or not the value set in the buffer memory E is "FF". "FF"
If so, the flow proceeds to # V-6, and if not "FF", proceeds to # V-5-2.

# V-5-2: The field flag is set and the field playback mode is set. The flow proceeds to # U-6.

# V-6; Here, the 7-segment LED 25 that displays the track number blinks from 2Hz to 5Hz set in # V-1.
Switch to a faster cycle. When performing continuous track deletion, the number of tracks set in place of the track number being accessed by the head 3-1 in # V-17 described later is displayed by the 7-segment LED 25. However, by executing # V-6, the switching is automatically performed so that the track number is displayed on the 7-segment LED 25. Therefore, at the time of erasing continuous tracks, the user can confirm which track is currently erased.

# V-7; Here, the CPU 40 controls the erase signal generation switch 85 to generate an erase signal and erase is executed. When erasing is performed, the switches 2 and 3 shown in FIG.
Is controlled to connect at least one of the heads 3-1 and 3-2 to the recording amplifier. Here, when the field flag is set, that is, in the field playback mode, the erase current flows only to the head 3-1 shown in FIG. 1 which is being reproduced, and one track is erased. When the field flag is cleared, that is, when the frame reproduction is selected, the heads 3-1 and 3 shown in FIG.
-2, an erasing current flows through both of them simultaneously to erase one frame of video signal, in other words, erasing video signals of two adjacent tracks. In this embodiment, the erasing in the frame mode is executed from # V-5-1 to # V-.
Only when the flow proceeds to # V-6 without passing through 5-2. That is, in # V-5-1, the value of the buffer memory E is set to "FF", that is, when the continuous erasing mode described later is not selected.

# V-8; Wait until erasing ends here. When the erasing is completed, the flow proceeds to # V-8-1.

# V-8-1; Here, it is determined whether or not E is equal to "FF". If it is equal to "FF", the flow is to the single erase mode, so the flow proceeds to # V-18. If not, the flow proceeds to # V-9 because continuous track erase is set.

# V-9; Here, the value of the buffer memory E is decremented by 1. The flow proceeds to # V-10.

# V-10; The value of buffer memory E is 0 at this step.
Is greater than or equal to. That is, the number of tracks to be erased when continuous track erase is set is detected, and if it is greater than 0, the flow proceeds to # V-11. If not, it is assumed that continuous track erase is completed. Go to # V-18.

# V-11: It is determined whether or not the stop switch 61 is turned on in this step. If it is turned on, the flow branches to # V-18, and if it is not turned on, it proceeds to # V-12. That is, the continuous erasing mode, which will be described later, is selected, and the continuous erasing can be interrupted by operating the stop switch 61 while executing the continuous erasing mode. Then, the flow proceeds to # V-12.

# V-12; In this step, whether or not N in the buffer memory of the track number is 50 or more, that is, head 3-
It is determined whether or not the track 1 being accessed is the final track. If so, the flow is # V-18
Proceed to step # V-13 if the erasing operation is not completed.
Proceed to.

# V-13; Head 3 is executed by executing this step.
The track positions accessed by -1, 3-2 move one track toward the inner circumference. Also head 3-1,3-2
N + to N in the track number memory as the
1 is set. Then, the flow branches to # V-5-2.

Therefore, when erasing continuous tracks, the stop switch
Until 61 is turned on or the innermost track is erased, the flow of # V-5-2 to # V-13 is executed until the value of the buffer memory E becomes 0, that is, the set number of tracks. Repeat until erasing is completed.

Next, the flow after # V-15 for setting the continuous erase mode executed as described above will be described.

# V-15: It is determined whether or not any one of the 10 key switches shown at 63 to 72 in FIG. 1 is turned on. If it is turned on, then it is turned to # V-16. If it is not turned on, # V-
The flow proceeds to 15-1.

# V-16; In this step, the continuous track erase mode is set. That is, 10 key switches 63
The number input by ~ 72 becomes the number of tracks for which continuous erasing is executed. The number of erase tracks was turned on for buffer E.
The value of the 10 key is set to the ones digit. Then the flow is #
Proceed to V-17.

# V-17; 7-segment LED25 in this step,
The value of E is displayed. This situation will be described with reference to FIG. At # V-15, the value of the first 10-key switch turned on is set to the 1s position of E (# V-16), and at this step, as shown in FIG. 25 (a),
It will be displayed on the 1st place of LED25. Where the 22nd
Before reaching the display of Fig. (A), the track No. is displayed on the display and is blinking. Further, F set to E is displayed as "0". The numerical value displayed on the display is shown in Fig. 25 (a) because the blinking operation of 2Hz is still repeated in # V-1. Will be flashing. Then the flow is #V
Go to -17-1.

# V-17-1; Here, wait until the 10-key switch is turned off. When turned off, the flow proceeds to # V-15-1.

# V-15-1; Here, it is determined whether or not the erase standby switch 77 is turned on. If it is turned on, the flow proceeds to # V-18. If it is not turned on, # V-
Proceed to 15-2.

That is, the erase standby state set in # V-1 by turning on the erase standby switch 77 is automatically released by turning on the switch 77 again by the steps after # V-18. Therefore, it is not necessary to provide a dedicated release switch.

# V-15-2; Here, it is judged whether or not the switches other than the switch 78 and the 10 key are turned on. If it is on, the flow branches to # V-18, and if it is not on, it branches to # V-4.

That is, the erase standby state is automatically released by turning on any switch other than the 10 key by the steps after # V-18. Therefore, it is not necessary to provide a dedicated release switch. Therefore, it is not necessary to purposely provide another switch. If the above steps # V-15-1 and # V-15-2 are skipped with NO, the above steps after # V-4 will be repeated, but the 7 segment LE has already been completed.
D25 shown in Figure 25 The operation when executing steps after # V-4 when is displayed will be described.

When the 10-key switch is turned on in # V-15, #V
In -16, the value input by the switch is set to the 1st place of the buffer memory E, and the number that was set to the 1st place until then moved to the 10th place of the buffer memory E and is set to the 10th place. Number disappears.

Here, for example, when the "5" key of the 10-key switch is turned on, the display shown in FIG. 28 (b) is displayed on the 7-segment LED 25 by executing # V-16 and # V-17. Be seen. Of course, the value set in the buffer memory E in this case is 15. Similarly, when "2", which is good for the 10-key switch, is similarly input, the display shown in FIG. 25 (c) is displayed. The above display example shows the display performed by the LED 25 when 1, 5, and 2 of the 10 key switches are sequentially turned on in the erase standby state. Further, the displayed numerical value matches the value set to E as it is. That is, when a numerical value of "2" or more is set by the 10-key switch, this is equivalent to the selection of the continuous erasing mode, and the set numerical value becomes the number of tracks at which the continuous erasing is executed. This situation is described in # V- in the above description of the flow.
If the value of the buffer memory E is greater than 0 at 10, the flow proceeds to # V-11, otherwise #V
If the track number N branches to -18 and the track number N is smaller than 50, the track is updated at # V-13 to branch to # V-5-2, and the steps after # V-6 are executed to continuously erase. Is done. In other words, if the stop switch 61 is not turned on in # V-11, the erasing is continuously performed until the value of E becomes equal to 0 or the innermost track 50th track is erased. become. Next, # V-18 to # V-20 executed after executing the steps described above will be described.

# V-18; Here, the 7-segment LED 25 is stopped blinking and the track NON is displayed on the display. Then, the flow reaches # V-19. That is, the standby state for step erase is released.

# V-19; If the switch 77 is turned on here, the process waits, and if it is turned off, the process proceeds to # V-20.

# V-20; Here, the flow returns to the flow shown in A of FIG.

As described above, in the present embodiment, when erasing is performed, the mode in which the erasing is performed only once and the mode in which the erasing is performed continuously, particularly the mode in which the number of tracks to be erased continuously is designated before the erasing However, for erasing when the number of erasing tracks is not set by the 10-key switch, the value of E in # V-5-1 is "FF" in advance.
Since it is set as #, #
Move to V-6. Therefore, when the field flag is cleared in the erase standby state,
Erasing in the frame mode, that is, erasing for two tracks, is performed, and when the field flag is set, erasing in the field mode, that is, erasing for one track is executed. In other words, when the reproduction is performed in the frame mode, the two tracks used for the reproduction are erased when the reproduction is performed in the field mode. However, if the number of erase tracks is set by the 10-key switch, the erase operation is always executed in the field mode because it goes through # V-5-2. However, "0" from the 10 key switch
Is set, the erasure is not executed in # V-5 because the process branches to # V-18. When "1" is set, the field flag is set at # V-5-2.
Therefore, even if the frame is reproduced until then, only the outer track of the two tracks constituting the frame image is erased by one track.

Therefore, it is possible to erase only the signal recorded in one of the two tracks constituting the frame image.

Further, in the case of performing continuous track erasing, it is generally premised that new information such as a video signal is recorded in the erased track. In the above-described embodiment, when the continuous track erasure is completed, the head 3-1 is located on the last erased track, so that when the user records new information, the track is deleted by the user.
It is necessary to operate the UP switch 54 and the DOWN switch 55 so that the head 3-1 can access the track on which erasing has started.

Therefore, the next step is to execute a continuous track erasure, and when this is completed, a flow for realizing a function that is very effective in terms of operability in which the head 3-1 is automatically accessed to the track that started continuous erasure. Is shown in FIG.
The flow shown in FIG. 29 is the same as # V-18, # V-19 shown in FIG.
Is a flow inserted between each step of.

First, when executing the subroutine V, the track number N being accessed at that time in # V-1 is stored in the memory N '. Then, after erasing according to the above-mentioned flow and reaching # V-18, the flow shown in FIG. 29 is executed. That is, in # V-18-1, it is judged whether or not the number of the track being accessed by the head 3-1 at that time matches the number of the track stored in the memory N'in # V-1. If not, # V-18-2 and # V18-3 are executed, the head 3-1 is controlled to access the outer track for one track, and N is set to N-1. The memory N is displayed on the segment LED 25. Then, the flow returns to # V-18-1 to # V-18-2, # V- until the number of the track accessed by the head 3-1 matches the number of the track stored in the memory N '.
When the head 3-1 accesses the track whose erasure has started by repeating 18-3, the flow branches from # V18-1 to # V-19, and the steps from # V-19 onward are executed. Therefore, by executing the flow shown in FIG. 29, the head 3-1 automatically accesses the track at which erasing has started at the end of erasing, and therefore the operation of manually searching for the position at which erasing has started in the next recording can be omitted. Can be done.

Also, when performing continuous erasure, the image to be erased is played back for a certain period of time, the operator confirms this and whether or not the stop switch 61 is turned on, and then the erase execution operation for that track is not started. It is extremely effective in preventing accidental erasure.

In order to realize this function, it is desirable to execute # V-7 of one track in # V-13 of the subroutine V shown in FIG. 27 after executing N + 1 for one track UP, N and preferably # V-6.
Immediately after the step, a step for delaying, for example, about 1 second is provided, and it is determined whether or not the stop switch 61 is turned on during this delay. If not, it is turned on to # V-7. For example, a switch that branches to # V-18 may be provided.

Since the video signal to be erased can be confirmed by providing such a step, continuous erasing can be interrupted by turning on the stop switch 61 when a video which is not desired to be reproduced is reproduced. Therefore, the probability of erroneous erasure is dramatically reduced.

Further, when performing continuous erasing, in the above-described embodiment, the flow branches from # V5-1 to # V5-2 in the subroutine, and by executing # V5-2, all the tracks are in the field mode one track at a time. Although it is erased, in order to shorten the execution time of continuous erase, it is effective to erase two tracks at least once in continuous track erase by sending an erase signal to two heads simultaneously in frame mode. Is. An example of this case will be described below.

First, in FIG. 30, the flow shown in FIG.
This is a step inserted between the steps # V-6 and # V-7 shown in the figure, and the flow shown in FIG. 30 (b) is # V-1.
This is a step inserted between the steps of 1 and # V-12. Next, the flow will be described.

After the subroutine shown in FIG. 27 is executed up to # V-6, # V-6-1 is executed subsequently to # V-6. In this step, it is determined whether the erase track buffer E is 2 or more, that is, whether the continuous track erase is performed. If it is 2 or more, the flow proceeds to # V-6-2, and if not, proceeds to # V-7. # V-6-2
In E, E-1 is set to clear the field flag. The flow reaches # V-7. An erase signal is generated at # V-7 shown in FIG. 27. In this case, if the field flag is set, one of the heads 3-1 and 3-2, that is, field reproduction is performed. When the erase flag is cleared and the field flag is cleared, the head 3-
The erase signal is supplied to both 1 and 3-2 at the same time. After the erasing is completed, # V-8 to # V-11 are executed as described above. If the continuous erasing operation is not completed, the flow goes from # V-11 to # V-11-1 and the field is reached. Determine whether the flag is set. When the continuous track erasure is not set and the field flag is set, the flow proceeds to # V-12 and follows the above-mentioned flow. If continuous track erasure is set in # V-11-1 and the field flag is not set, the erasure of two tracks is performed in # V-7 as described above. V-11-2
The flow reaches, and N + 1 is set to N, and the heads 3-1 and 3-2 move to the inner circumference side of one track. Then the flow is #
After reaching V-13, the head further moves to the inner circumference side of one track according to the above-mentioned flow.

According to the above, when the continuous erasing is executed, the erasing is performed in the frame mode until the remaining number of tracks of the continuous erasing becomes 1, so that the execution speed of the continuous erasing can be increased. However, in this case, when confirming the image to be erased before executing the erasing, the head 3-1 and 3-2 in FIG. Select each and select Head 3-1
It is necessary to carry out the field reproduction by 3 and the field reproduction by 3-2. Also # V-2, #V
It is also possible to omit the step -3 and switch between the PB mode and the REC mode, in particular, to select the mode for confirming the reproduced video to be erased during execution of continuous erasing and the mode for not confirming it. In other words, select the mode that does not confirm the images to be erased when performing continuous erasing
When the flow shown in FIGS. 27A and 27B is added to the flow shown in FIG. 27, the continuous erasing time becomes the shortest. This is a very effective means when erasing all tracks. Becomes

Next, a subroutine executed when the all-track erase standby switch 79 is turned on will be described with reference to FIG.

# W-1: Indicates that the 7-segment LED 25 is in the all-track erase standby state Make (ALL-ERASE) blink at 2Hz.

# W-2: It is determined whether or not the PB mode flag is set. If not set, the flow branches to # W-4 if set to # W-3.

# W-3-1: Clear the PB mode flag and magnetic sheet 1
Prohibit the playback of.

# W-3-2: Detecting that the switch 79 is turned off, the process proceeds to # W-4.

# W-4: It is determined whether or not the erase switch 78 is on. If it is on, the flow branches to # W-9, and if not, the flow branches to # W-5.

# W-5: It is determined whether or not the all-track erase standby switch 79 has been turned on. If it is ON, the flow branches to # W-7, and if it is not ON, the flow branches to # W-6.

# W-6: It is determined whether or not a switch other than the switch 79 is turned on. If it is ON, the flow branches to # W-7, and if it is not ON, the flow branches to # W-4.

# W-7: The blinking of the LED 25 is stopped, and the LED 25 is caused to display N, that is, the track number being accessed by the head 3-1.

# W-8: Wait until switch 79 is turned off, and if turned off, return to.

# W-9: When the erase switch 78 is turned on in # W-4, the flow branches to this step. In this step, it is determined whether or not there is an erroneous erasure prevention claw not shown. If there is, the flow branches to # W-10, and if not, to # W-7.

# W-10: N is "1", that is, it is determined whether the track number accessed by the head 3-1 is "1",
If it is "1", the flow branches to # W-12. If it is not "1", the flow branches to # W-11.

# W-11: Heads 3-1 and 3-2 are moved to the outer peripheral side for one track, 1 is subtracted from N, and the flow returns to # W-10. Therefore, when the number of the track being accessed by the head 3-1 becomes 1 by repeatedly executing # W-10 and # W-11, the flow is # W-12.
Branch to.

# W-12: LED 25 blinks N (5 Hz). This allows the user to know which track has been erased when erasing all tracks.

# W-13: The field flag is set by clearing the field flag. Therefore, the tracks are erased by using the heads 3-1, 3-2 together.

# W-14: These two steps are # W-7, # W-8 # W-1
Same as 5.

# W-16: Heads 3-1 and 3-2 are used together to erase 2 tracks without moving the heads. Therefore, in this step, the heads for 2 tracks are moved to the outer peripheral side, and N Add 2 to.

# W-17: It is determined whether or not N is 50. If it is 50, the flow branches to # W-7, and if it is not 50, the flow branches to # W-12, and the deletion of all tracks is completed. Up to # W-12 to # W-
17 steps are repeated.

As described above, in the all-track erase mode that is executed by turning on the erase switch after turning on the all-track erase standby switch, before erasing
The PB mode flag is cleared so that the image to be erased is not confirmed, and both tracks are erased by using both magnetic heads 3-1 and 3-2. Therefore, erase one track at a time. The time required to erase all tracks is extremely short compared to the method. Further, when erasing all the tracks, the head is moved to the end of the track (outermost circumference in this embodiment) in advance, and then all the tracks are erased in order toward the opposite end. When the head 3-1 is accessed, it is possible to surely erase all tracks regardless of which position the head 3-1 is accessing.

Further, during erasing, the number of the track accessed by the head 3-1 is displayed on the LED 25, so that the user can confirm to what extent the erasing operation is being performed.

Although the magnetic sheet 1 is used as the recording medium in the above-mentioned embodiments, it may be an optical recording medium. A magneto-optical recording medium or another recording medium may be used. The recording means may be a means suitable for the recording medium, for example, an optical head in the case of an optical disc.

As is apparent from the above description, according to the present invention, the display mode by the display means is changed between the reproduction operation in response to the erase command input and the operation in response to the reproduction command input. It is possible to make the user recognize that the erase standby mode is set, and thereby prevent accidental erasure.

[Brief description of drawings]

FIG. 1 is a block diagram showing the construction of an embodiment of the present invention, FIG. 2 is a view showing a combination of switching states of SW2 to SW5 shown in FIG. 1, and FIG. 3 is a front view of the apparatus of this embodiment. Fig. 4 is a front view of a remote control device used with the device, Figs. 5 to 20, Fig. 23, Fig. 25 to Fig. 27,
29 to 31 are flow charts of the CPU 40 shown in FIG. 1, and FIGS. 21, 22, and 24 show I / I displayed on the monitor.
FIG. 28 is a diagram for explaining the D signal, FIG. 28 is a diagram for explaining the flow of FIG. 27, and FIG. 32 is a diagram for explaining the signal generated from the erase signal generator 85 shown in FIG. It is a figure. 1 ... Magnetic sheet 3-1, 3-2 ... Head 40 ... CPU

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasutomo Suzuki 770 Shimonoge, Takatsu-ku, Kawasaki-shi, Kanagawa Canon Inc. Tamagawa Plant (56) Reference JP-A-60-247801 (JP, A) -13729 (JP, U) Actual public 55-45552 (JP, Y2)

Claims (1)

[Claims] 1. A first detecting means for detecting an erasing command input, a second detecting means for detecting a reproducing command input, a reproducing means for reproducing information recorded on a recording medium, and an operation of the reproducing means. A display unit for displaying the state; and a control unit for operating the reproducing unit in response to the erase command input or the reproducing command input and controlling the display unit in conjunction with the operation of the reproducing unit. The erasing device is characterized in that the control means variably sets a display mode depending on whether the reproducing means operates in response to the erase command input or operates in response to the reproducing command input.