JPS62231574A - Channel switching decision circuit - Google Patents

Channel switching decision circuit

Info

Publication number
JPS62231574A
JPS62231574A JP7503186A JP7503186A JPS62231574A JP S62231574 A JPS62231574 A JP S62231574A JP 7503186 A JP7503186 A JP 7503186A JP 7503186 A JP7503186 A JP 7503186A JP S62231574 A JPS62231574 A JP S62231574A
Authority
JP
Japan
Prior art keywords
circuit
channel
output
counter
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7503186A
Other languages
Japanese (ja)
Inventor
Yuji Minami
南 裕治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP7503186A priority Critical patent/JPS62231574A/en
Publication of JPS62231574A publication Critical patent/JPS62231574A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the reliablity in terms of switching a channel by providing a comparator circuit that compares the number of pulses in the 1st and 2nd counters and outputs them when they approximately coincide with each other and a latch circuit sampling the presence or adsence of a coincidence output from the comparator circuit at every predetermined number of pulses. CONSTITUTION:A reference signal generator circuit 4 outputs a pulse with a fixed period as figure shows, and the 2nd counter 5 counts the pulse. Simultaneously the 1st counter 3 counts a synchronizing signal that a synchronous separator circuit 2 separates from a video signal as figure (a) shows. The comparator circuit 6 compares the values counted by the 1st and 2nd counters 3 and 5, and outputs appear and are transmitted to a latch circuit 7 while said counted values are the same. If a channel is switched in a time (x) in figure (a), a vertical synchronizing signal turns out to be a discontinuous pulse. Then the values counted by the 1st and 2nd counters 3 and 5 become unequal, and the output of the comparator circuit 6 disappears as figure (a) illustrates. Therefore the output of the latch circuit 7 is inverted at the time of sampling the eighth pulse after latching is made before, and the circuit decides that the channel is switched.

Description

【発明の詳細な説明】 「産業上の利用分野」 本発明は1文字放送受信可能なTV受信機において、チ
ャンネルを切換えたことを判断するためのチャンネル切
換判定回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a channel switching determination circuit for determining that a channel has been switched in a TV receiver capable of receiving single character broadcasting.

「従来の技術」 あるチャンネル例えば1チヤンネルの文字放送受信中に
、他のチャンネル例えば4チヤンネルに切換えられたと
き、1チヤンネルの文字放送が出力されることがある。
"Prior Art" When receiving a teletext broadcast on a certain channel, for example, channel 1, when switching to another channel, for example, channel 4, the teletext broadcast on channel 1 may be output.

このような場合、従来は。In such cases, traditionally.

リモコンのチャンネル信号等でチャンネルが切換えられ
たかどうかを判断していた。
It was determined whether the channel had been changed based on the channel signal of the remote control, etc.

「発明が解決しようとする問題点」 文字放送受信機がTV受信機と一体形ではあまり問題は
なかったが1文字放送受信機がアダプタ形になっている
ものでは、チャンネルの切換えの判断ができないか、で
きても動作の信頼性が低いという問題があった。
``Problems to be solved by the invention'' There were not many problems when the teletext receiver was integrated with the TV receiver, but when the teletext receiver was an adapter type, it was not possible to judge channel switching. Or, even if it were possible, there was a problem that the reliability of operation was low.

「問題点を解決するための手段」 本発明は上述の問題点を解決するためになされたもので
、TVのビデオ信号から同期信号を分離する同期分離回
路と、この同期分離回路で分離された同期信号数を計数
する第1のカウンタと、前記同期信号と同一周期の基l
曽パルス信号を出力する基?曽信号発生回路と、この基
準信号発生回路から出力された基準パルス信号を計数す
る第2のカウンタと、これら第1、第2のカウンタのパ
ルス・数を比較して略一致したとき出力する比較回路と
、この比較回路の一致出力の有無を一定パルス数毎にサ
ンプリングするラッチ回路とを具備し、このラッチ回路
の出力の有無でチャンネルの切換を判断するようにした
ものである。
"Means for Solving the Problems" The present invention was made to solve the above problems, and includes a sync separation circuit that separates a sync signal from a TV video signal, and a sync separation circuit that separates a sync signal from a TV video signal. a first counter that counts the number of synchronization signals; and a base l having the same period as the synchronization signal.
A base that outputs a pulse signal? A second counter that counts the reference pulse signal outputted from the reference signal generation circuit and the reference signal generation circuit, and a comparison device that outputs an output when the pulses and numbers of the first and second counters are substantially matched. The device includes a circuit and a latch circuit that samples the presence or absence of a coincidence output from the comparison circuit every fixed number of pulses, and the channel switching is determined based on the presence or absence of the output of the latch circuit.

「作用」 TVのビデオ信号中から例えば垂直同期信号を分離し、
第1のカウンタで計数する。また、第2のカウンタでは
、垂直同期信号と同一周期の基準パルス信号を計数する
。第1、第2のカウンタは、同期して計数をすれば常に
一致した信号が比較回路から出力する。ところが、チャ
ンネル切換えに伴いTVの同期信号が不連続になると、
第1、第2のカウンタの計数値が一致しなくなる。一定
パルス数毎にこれをサンプリングして不一致で不連続に
なるとラッチ回路の出力が変り、チャンネルが切換えら
れたものと判定する。
"Operation" Separates, for example, the vertical synchronization signal from the TV video signal,
Count with the first counter. Furthermore, the second counter counts reference pulse signals having the same period as the vertical synchronization signal. If the first and second counters count synchronously, matching signals will always be output from the comparison circuit. However, when the TV synchronization signal becomes discontinuous due to channel switching,
The counts of the first and second counters no longer match. The pulses are sampled every fixed number of pulses, and when they become discontinuous due to mismatch, the output of the latch circuit changes, and it is determined that the channel has been switched.

「実施例」 以下、本発明の一実施例を図面に基づき説明する。"Example" Hereinafter, one embodiment of the present invention will be described based on the drawings.

(1)はTV受信機からのビデオ信号入力端子で、この
入力端子(1)はビデオ信号中の複合、垂直または水平
の同期信号を分離する同期分離回路(2)を介して第1
のカウンタ(3)のクロック入力端子に結合されている
。また、(4)は基準パルス信号を発生する基準信号発
生回路で、前記同期分離回路(2)の出力が垂直同期信
号であるときは、これと同一周期のパルスが出力する。
(1) is a video signal input terminal from a TV receiver, and this input terminal (1) is connected to the first signal via a synchronization separation circuit (2) that separates a composite, vertical or horizontal synchronization signal in the video signal.
The clock input terminal of the counter (3) is coupled to the clock input terminal of the counter (3). Further, (4) is a reference signal generation circuit that generates a reference pulse signal, and when the output of the synchronization separation circuit (2) is a vertical synchronization signal, a pulse having the same period as this is outputted.

この基準信号発生回路(4)は第2のカウンタ(5)の
クロック入力端子に結合され、この第2のカウンタ(5
)と前記第1のカウンタ(3)は比較回路(6)に結合
され、この比較回路(6)と前記第2のカウンタ(5)
はランチ回路(7)に結合され、このラッチ回路(7)
は出力端子(8)に結合されている。なお、前記第2の
カウンタ(5)はインバータ(9)を介して第1のカウ
ンタ(3)のクリア入力端子に結合され、常に一定パル
ス数毎に同期して計数を開始するようになっている。
This reference signal generation circuit (4) is coupled to a clock input terminal of a second counter (5).
) and said first counter (3) are coupled to a comparison circuit (6), said comparison circuit (6) and said second counter (5)
is coupled to the launch circuit (7), and this latch circuit (7)
is coupled to the output terminal (8). The second counter (5) is connected to the clear input terminal of the first counter (3) via an inverter (9), and always starts counting in synchronization with every fixed number of pulses. There is.

つぎに以上の構成による作mを説明する。基準信号発生
回路(4)からは第2図(b)に示すような一定周期の
パルスが出力し、このパルスを第2のカウンタ(5)で
計数をする。同時に、同期分離回路(2)でビデオ信号
から分離された第2図(a)に示すような同期信号も、
第1のカウンタ(3)で計数をする。これら第1、第2
のカウンタ(3)(5)の計数値は比較回路(6)で比
較され、一致している間は出力があられれ、ラッチ回路
(7)へ送られる。ラッチ回路(7)には、第2カウン
タ(5)の例えば8パルス目の信号がサンプリングパル
スとして入力し一致出力があるかどうかを判断する。
Next, the operation using the above configuration will be explained. The reference signal generating circuit (4) outputs pulses with a constant period as shown in FIG. 2(b), and these pulses are counted by a second counter (5). At the same time, the synchronization signal as shown in FIG. 2(a) separated from the video signal by the synchronization separation circuit (2) is also
The first counter (3) counts. These first and second
The count values of the counters (3) and (5) are compared in the comparator circuit (6), and while they match, the output is output and sent to the latch circuit (7). For example, the eighth pulse signal of the second counter (5) is input to the latch circuit (7) as a sampling pulse, and it is determined whether there is a matching output.

チャンネルを切換えなければビデオ信号中の垂直同期信
号は一定周期の連続的なパルスが入力してくるので、比
較回路(6)からは−救出力があられれ、こわが8パル
ス毎にサンプリングされ、チャンネルの切換えがないも
のと判定する。
If the channel is not switched, the vertical synchronization signal in the video signal will be input with continuous pulses of a constant period, so the comparator circuit (6) will sample the rescue power and stiffness every 8 pulses. It is determined that there is no channel switching.

第2図(、)の(x)時点でチャンネルの切換えがある
と、垂直同期信号は不連続なパルスとなる。すると、第
1、第2のカウンタ(3) (5)の計数値が不一致と
なって第2図(c)のように比較回路(6)の出力がな
くなるので、前回のラッチ後の8パルス目のサンプリン
グ時(Y)にラッチ回路(7)の出力が反転してチャン
ネルが切換ったものと判定する。
When the channel is switched at time (x) in FIG. 2(,), the vertical synchronizing signal becomes a discontinuous pulse. Then, the counted values of the first and second counters (3) and (5) do not match, and the output of the comparator circuit (6) disappears as shown in Figure 2 (c), so the 8 pulses after the previous latching At the time of sampling (Y), the output of the latch circuit (7) is inverted, and it is determined that the channel has been switched.

前記実施例では、第1、第2のカウンタ(3)(5)の
出力パルス数が完全に一致したとき比較回路(6)から
出力するようにした。しかし、このようにすると、ノイ
スハルスが1個入っただけでもチャンネル切換えと判定
するおそれがあるので、比較回路(6)は、例えば2個
まで異ってもラッチ回路(7)へ出力するようにし、3
個以上のちがいがあったときチャンネルが切換えられた
ものと判定するようにしてもよい。
In the embodiment described above, the comparator circuit (6) outputs when the output pulse numbers of the first and second counters (3) and (5) completely match. However, if this is done, there is a risk that even one Neushals signal will be judged as a channel change, so the comparator circuit (6) should be configured to output to the latch circuit (7) even if there is a difference of, for example, two. ,3
It may be determined that the channel has been switched when there is a difference of 1 or more.

前記実施例では、8パルス毎にサンプリングして判定し
たがこれに限られるものではない。
In the embodiment described above, the determination is made by sampling every 8 pulses, but the present invention is not limited to this.

「発明の効果」 本発明は上述のように構成したので5文字放送受信機が
アダプタ形であっても、TV受(N機と一体形のように
作動するので、操作性がよく、シがも動作の信頼性が大
巾に向上するものである。
"Effects of the Invention" Since the present invention is configured as described above, even if the 5-character broadcast receiver is an adapter type, it operates as if it were an integrated type with the TV receiver (N machine), so it has good operability and is easy to install. This also greatly improves operational reliability.

40図面のfJ ll’−な説明 第1図は本発明によるチャンネル切換判定回路の一実施
例を示すブロック図、第2図は各部の出力波形図である
6 (1)・・・ビデオ信号入力端子、(2)・・・同期分
離回路、(3)・・・第1のカウンタ、(4)・・・基
準信号発生回路、(5)・・・第2のカウンタ、(6)
・・・比較回路、(7)・・・ラッチ回路、(8)・・
・出力端子、(9)・・・インバータ。
40 Description of Drawings Fig. 1 is a block diagram showing an embodiment of the channel switching determination circuit according to the present invention, and Fig. 2 is an output waveform diagram of each part.6 (1)...Video signal input Terminal, (2)...Synchronization separation circuit, (3)...First counter, (4)...Reference signal generation circuit, (5)...Second counter, (6)
... Comparison circuit, (7) ... Latch circuit, (8) ...
・Output terminal, (9)...Inverter.

Claims (1)

【特許請求の範囲】[Claims] (1)TVのビデオ信号から同期信号を分離する同期分
離回路と、この同期分離回路で分離された同期信号数を
計数する第1のカウンタと、前記同期信号と同一周期の
基準パルス信号を出力する基準信号発生回路と、この基
準信号発生回路から出力された基準パルス信号を計数す
る第2のカウンタと、これら第1、第2のカウンタのパ
ルス数を比較して略一致したとき出力する比較回路と、
この比較回路の一致出力の有無を一定パルス数毎にサン
プリングするラッチ回路とを具備し、このラッチ回路の
出力の有無でチャンネルの切換を判断するようにしたこ
とを特徴とするチャンネル切換判定回路。
(1) A sync separation circuit that separates a sync signal from a TV video signal, a first counter that counts the number of sync signals separated by this sync separation circuit, and outputs a reference pulse signal with the same period as the sync signal. a reference signal generating circuit that counts the reference pulse signals outputted from the reference signal generating circuit; a second counter that counts the reference pulse signals output from the reference signal generating circuit; circuit and
A channel switching determination circuit comprising: a latch circuit that samples the presence or absence of a matching output from the comparison circuit at every fixed number of pulses; and a channel switching determination circuit, comprising: a latch circuit that samples the presence or absence of a matching output from the comparison circuit at every fixed number of pulses;
JP7503186A 1986-03-31 1986-03-31 Channel switching decision circuit Pending JPS62231574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7503186A JPS62231574A (en) 1986-03-31 1986-03-31 Channel switching decision circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7503186A JPS62231574A (en) 1986-03-31 1986-03-31 Channel switching decision circuit

Publications (1)

Publication Number Publication Date
JPS62231574A true JPS62231574A (en) 1987-10-12

Family

ID=13564408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7503186A Pending JPS62231574A (en) 1986-03-31 1986-03-31 Channel switching decision circuit

Country Status (1)

Country Link
JP (1) JPS62231574A (en)

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