JPS63110873A - Noise removing device for synchronizing signal - Google Patents

Abstract

PURPOSE:To generate a synchronizing signal not containing a noise component by counting the number of samples to correspond to a synchronizing signal level among the continuous m-samples of a synchronizing signal, deciding the start of the synchronizing signal from the face that a counted value reaches a predetermined value, and on the other hand, deciding the termination of the synchronizing signal from the fact that is decrease to the other predetermined value. CONSTITUTION:A TV signal inputted from an input terminal 12 is compared with a reference voltage VREF by a voltage comparator 2 after passing through a clamping circuit 1, and when it goes to below the VREF, an output goes to H. This output is latched into a DFF3 by the leading edge of a clock. A latched output is delayed by m-clock by a shift register 4. When the ENP terminal of a counter 8 at the leading of the clock is L, a counting operation is performed, and when the input of a U/ the inverse of D terminal is H or L, a counting up or a counting down is performed respectively. When the counted value of the counter 8 reaches the predetermined value m1 of a detection circuit A, the output of the circuit A goes to H. When the counted value goes to the m2 (<m1), a detection circuit 10 transmits a reset pulse to the circuit A, and the output of the circuit A goes to L. At that time, a limit circuit 11 generates a pulse and makes the detection circuit 9 stop.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal noise removal device for removing noise contained in synchronization signals necessary for television signals and the like.

[Conventional technology]

As shown in FIG. 3, a negative synchronization signal is inserted into the television signal during the blanking period of the video signal.

Separation of synchronization signals is performed by paying attention to this amplitude, and for example, synchronization separation is performed by the circuit shown in FIG. In the circuit shown in FIG. 4, a video signal is applied to the base of the transistor through a CR coupling circuit with a relatively large time constant, a pace current flows only during the synchronization signal period, and a positive synchronization signal is taken out to the collector side. Using the circuit configuration shown in FIG. 45, the synchronization signal can also be extracted by clamping the input video signal and then comparing it with a reference voltage using a voltage comparator.

The synchronization signal thus extracted is passed through an integrating circuit to obtain a vertical synchronization signal. On the other hand, a horizontal synchronization signal 2 is obtained by passing the synchronization signal through a differentiating circuit.

Here, since the vertical synchronization signal is obtained through an integrating circuit, it is not easily affected by noise, but as a horizontal synchronization signal, the signal extracted by differentiation as described above or the amplitude-separated synchronization signal as it is is used in the signal processing system. Because it is used in television, it is directly affected by the noise contained in the television signal. Therefore, a synchronous AFC circuit is used in the horizontal deflection system of a television receiver to prevent horizontal synchronization from being disturbed by noise.

[Problem to be Solved by the Invention 3] As described above, in the conventional configuration, if noise of the same level as the synchronization signal level is mixed into the television signal, the horizontal synchronization signal separated from the television signal will be affected by the noise. The noise will appear directly.

Therefore, when the horizontal synchronizing signal is used as an all-direct reference signal in digital signal processing of a video signal, an error wJft= occurs due to noise. The same is true when the synchronization signal is transmitted through a separate system from the video signal, and is affected by noise. It is also possible to remove noise using a conventional synchronous AFC circuit;
There is a problem that FC circuits cannot cope with period deviations.This invention was made to solve the above problem, and it eliminates the 4% noise shadow from the synchronization signal accompanying the television signal. Synchronization signal noise removal equipment that can remove noise components and generate synchronization signals that do not contain noise components.
'& aims to obtain.

[Means for solving problems]

The synchronization signal f noise removal device according to the present invention samples the synchronization signal at a constant period, counts all the sample points corresponding to the synchronization signal level among consecutive m-point samples,
When the count value increases and reaches the integer value m1, it is determined that the synchronization signal starts, and when the count value reaches the town and decreases to the integer value m2, it is determined that the entire synchronization signal ends. In addition, detection of the synchronization signal is prohibited for a certain period of time after the end of the synchronization signal.

[Effect]

In this invention, the number of sample points corresponding to the synchronization signal level among m consecutive sample points of the synchronization signal increases, and when it reaches an integer value mIK, it is determined that the synchronization signal has been detected, and the synchronization signal After the number of sample points corresponding to the synchronization signal level among m consecutive sample points of m reaches ml, the input synchronization signal is Even if pulse-like noise with a narrow pulse width is included, the level of the output sync signal will not change due to it, and the sync signal detection operation will be prohibited for a certain period of time after the sync signal has been detected once. During the prohibition period, noise will not be mistaken for a synchronization signal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a clamp circuit, (2) is a voltage comparator, and (3) is a D7 lip-flop that samples the output of voltage comparator (2) in synchronization with the clock. Also, (4) is a shift register, (5) is an inverter circuit,
(6) is an AND circuit, (7) is an exclusive N0R (Ex-N
OR) circuit, (8) is for example TTL engineering Q '74169
up/down counters such as (9) and (3)
), and the counted value is a predetermined integer value m.
The detection circuit that detects when the
), and detects that the counted value has become an integer value m2 smaller than a predetermined ml;
υ is a detection operation limiting circuit which inputs the output of the detection circuit (9) and outputs a pulse for stopping the operation of the detection circuit (9) for a certain period of time.

Next, the operation will be explained.

A television signal including a negative polarity synchronous signal 8 is input from the input terminal @, and the DC level is determined by the clamp circuit (1). The clamped television signal is compared with the reference level VREi' between the pedestal level and the synchronization signal tip level in the voltage comparator (2).
The separated synchronization signal is extracted from the output of 2). The output of the voltage comparator (2) indicates that during the synchronization signal level period, the logic level in the subsequent logic circuit is lower than or equal to the high level c.
(hereinafter referred to as "low level") during other periods. The output of the voltage comparator (2) is latched by the D flip-flop (3) in synchronization with the clock applied to the clock input terminal (2). The output of the D7 lip-flop (3) is connected to the input of the shift register (4). The clock of the shift register (4) is supplied from the input terminal (to), and by using an m-bit shift register, the output of the D flip-flop (3) appears at its output with a delay of m clocks.

Further, the clock supplied to the D7 lip 70 block (3) and the shift register (4) K is also applied to the clock terminal of the up/down counter (3) from the input terminal (to). The up/down counter (8) has a count operation control terminal (IP terminal) and an up/down switching terminal (
When the opening terminal is L, counting is performed, and when the U/D terminal is H, counting is performed, and when the U/D terminal is H, counting is performed.
The countdown starts when . An exclusive NOR of the output of the D flip-flop (3) and the output of the shift register (4) is added to the above-mentioned logic circuit. Therefore, a counting operation is performed when the outputs of the D flip-flop (3) and shift register (4) do not match, that is, when the respective outputs are L and ■, or H and L. On the other hand, since the output of the D flip-flop (3) and the inverted output of the shift register (4) are added to the U/D terminal, the output of the D flip-flop (3) is high. When the output of the shift register (4) is L, the counter (3) is in an up-counting state, and when the output of the D flip-flop (3) is L and the output of the shift register (4) is ■. is in a down count state.

It is assumed that the shift register (4) and the counter (8) are cleared when the power is turned on, and the count value of the counter (3) becomes O. The count value of the counter (3) is added to the detection circuit A (9) and the detection circuit B QO. The detection circuit A (9) detects that the count value has reached a preset value m1 and outputs 'iH. On the other hand, the detection circuit BC1O
is the 0 detection time [i%] which outputs a pulse to the detection circuit A (9) when the count value of the counter (3) becomes m2 smaller than ml [i% The output of A (9) is the pulse from the detection circuit B C1O The output of the detection circuit A (9) is input to the limit circuit (MDI). The limiting circuit αυ outputs a pulse with a constant width when the input changes from H to L. The output of the limiting circuit (b) is the detection circuit A.
In addition to (9), the detection circuit A (9) stops operating during the period when the pulse is input from the limiting circuit αη, and does not output even if the count value of the counter (3) reaches ml. It is configured not to be H.

When the output signal of the 0 clamp circuit (1), which will be explained below using the time chart of FIG. 2, becomes lower than the reference voltage VREI applied to the voltage comparator (2), the operation as shown in FIG. ), the output of the voltage comparator (2) becomes H. This output is latched by the D flip-flop (3) at the rising edge of the clock shown in Figure 2 (a) (W, Figure 2 (C)). In the case of FIG. 2, the delay is 5 clocks (FIG. 2(d)). From Fig. 2(C) and Fig. 2(d), the counter control terminals (ENP, uA) have the second factor (e) (mouth terminal) and Fig. 42(f) (σ/
The signal shown in [10,000 terminals] is added. Here, Fig. 2(e)
If the 15 terminal input shown in Fig. 15 becomes L at the rising edge of the clock, a kakunt operation is performed, and the second factor (f) U/D
If the terminal terminal force is H, the count is up, and if the terminal force is L, the count is down. That is, as shown in FIG. 2(g), the count-up state occurs between time t□-tl shown in FIG. 2(j). Then, when the count value of the counter (3) reaches the value m1 (4 in FIG. 2) set in advance by the detection circuit AK, the output of the detection circuit A becomes H. Additionally, the counter (3) is in a countdown state between times t3 and t4 shown in the M2 diagram (j), and when the counted value reaches m2 (2 in the second factor), the detection circuit B (10 is a reset pulse is output to the detection port 66A (9), so
The output of detection port @A (9) becomes L.

Figure 2 shows the case where noise is mixed into the synchronization signal.
The output of the voltage comparator (2) temporarily changes from H to L due to noise. However, if the pulse width of the noise is narrow, as in the case of FIG. 2, although the count value of the counter (8) decreases, the output of the detection port w A (9) does not change.

Further, when the output of the detection port M A (9) changes from H to L, the output of the limiting circuit becomes H and returns after a preset time has elapsed. While the output of the limiting circuit αη is H, the output of the counter (8) is ml (second
In the case shown in the figure, the configuration is such that the output of the detection circuit A (9) does not change to H even if 4) is reached.

Although the above embodiment uses a clamp circuit and a voltage comparator configuration to separate and detect the synchronization signal, this part could be replaced with any other synchronization separation circuit conventionally used in television receivers. You may also use something.

If the synchronization signal is transmitted separately from the video signal, the input synchronization signal whose level has been appropriately converted may be directly applied to the D flip 70 knob (3) shown in FIG.

In addition, if the video signal has been converted into digital data by the A/D converter, the digital data of the video signal is compared with a preset value using a digital data comparator to separate the synchronization signal. , which may be added to the D flip-flop (3). Also, in FIG.
A gate is added to the input of the D7 lip 70 tube (3), so that while the output of the limiting circuit (B) is H, the input of the D clip 70 tube (3) is applied to the detection circuit A. It may be configured to always be L.

〔Effect of the invention〕

As described above, according to the present invention, the input synchronization signal is sampled, the number of samples corresponding to the synchronization signal level among m consecutive samples is counted, and when the counted value reaches a preset value, the synchronization signal is When the count value decreases and reaches the other setting value, which is smaller than the setting value, it is judged that the synchronization signal has ended, so narrow pulses are mixed into the synchronization signal as noise. The output synchronization signal will not be changed by this noise even if the noise is present.

Furthermore, since the detection of the synchronization signal is stopped for a certain period after the synchronization signal ends, it is not affected by noise during this period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synchronization signal noise removal device according to an embodiment of the present invention, FIG. g2 is a timing chart for explaining its operation, and FIG. 3 is a diagram showing a horizontal synchronization signal portion of a composite video signal. Both FIG. 4 and FIG. 5 are diagrams showing a synchronous signal 9 amplitude separation circuit. (1) is a clamp circuit, (2) is a voltage comparator, (3) is a D-clip 70 tube, (4) is an m-bit shift register, (5) is an inverter circuit, (6) is an AND circuit, (7)
) is Ex-1 (OR circuit, (3) is an up/down counter, (9) is a detection circuit A1σQ is a detection circuit B1 (1 is a limiting circuit. In addition, the same reference numerals in the figure indicate the same - or corresponding parts. shows.

Claims (2)

[Claims] (1) In a synchronization signal noise removal device for removing noise contained in a synchronization signal, a synchronization signal amplitude-separated from a composite video signal or a synchronization signal transmitted separately from the video signal is input, and the input synchronization signal is A sampling means for sampling in synchronization with a clock, a counting means for counting the number of sample points corresponding to the synchronization signal level in m consecutive samples, and detecting that the count value of the counting means has reached a preset value. A synchronization signal noise removal apparatus comprising: a detection means; and a detection means for detecting that the count value of the counting means has reached another set value smaller than the set value. (2) The synchronization signal noise removal device according to claim 1, wherein detection of the synchronization signal is stopped for a certain period of time after the detection means detects the synchronization signal.