JPS6365782A - Synchronizinge signal noise rejection device - Google Patents

Abstract

PURPOSE:To prevent the output synchronizing signal level change due to noise by sampling an input synchronizing signal and deciding it as a synchronizing signal when n-sample in consecutive m-sample corresponds to a synchronizing signal level and giving it to a post-stage circuit as an output. CONSTITUTION:When an output of a clamp circuit 1 is lower than a reference voltage 11, an output of a voltage comparator 2 goes to H and is latched to a D flip-flop 3 at the leading of clock. The output (c) is delayed by m-bit by a shift register 4. A counter 8 applies count when the ENP terminal input is at L at the leading of the clock and the count is incremented when the U/-D terminal input is at H and the count is decremented in case of L. When the count reaches a set value or over of the comparator 9, its output goes to H. Even if noise is included for times t0-t4 as shown in figure, the output level of the comparator 9 is unchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal noise removal device for removing noise contained in synchronization signals necessary for television signals and the like.

[Conventional technology]

As shown in FIG. 3, a negative synchronization signal is inserted into the television signal during the blanking period of the video signal.

Separation of synchronization signals is performed by paying attention to this amplitude, and for example, synchronization separation is performed by the circuit shown in FIG. In the circuit shown in FIG. 4, a video signal is applied to the base of the transistor through a CR coupling circuit with a relatively large time constant, the base current flows only during the synchronization signal period, and a positive synchronization signal is taken out to the collector side. Using the circuit configuration shown in FIG. 5, the synchronization signal can also be extracted by clamping the input video signal and then comparing it with a reference voltage using a voltage comparator.

The synchronization signal thus extracted is passed through an integrating circuit to obtain a vertical synchronization signal. On the other hand, a horizontal synchronization signal is obtained by passing the synchronization signal through a differentiating circuit.

Here, the vertical synchronization signal is obtained through an integrating circuit, so it is not easily affected by noise, but as the horizontal synchronization signal, the signal extracted by differentiation as described above or the synchronization signal separated in amplitude is used as it is in the signal processing system. Therefore, 'JE' is directly received despite the noise contained in the television signal.

Therefore, a synchronous AFC circuit is used in the horizontal deflection system of a television receiver to prevent horizontal synchronization from being disturbed by noise.

[Problem that the invention seeks to solve]

As described above, in the conventional configuration, if spike noise of a level comparable to the synchronization signal level is mixed into the television signal, the noise will directly appear in the horizontal synchronization signal separated from the television signal. For this reason, when the horizontal synchronizing signal is directly used as a reference signal when digital signal processing is performed on a video signal, malfunctions occur due to noise.

The same is true when the synchronization signal is transmitted through a separate system from the video signal, and is affected by noise. It is also possible to remove noise using a conventional synchronous AFC circuit, but when digitally processing a video signal using a direct horizontal synchronous signal as a reference as mentioned above, a synchronous AFC circuit cannot cope with period deviations, etc. There's a problem.

This invention was made to solve the above-mentioned problems, and provides a synchronization signal that can remove the influence of spike noise from the synchronization signal accompanying a television signal and generate a synchronization signal that does not contain noise components. The purpose is to obtain a noise removal device.

[Means for solving problems]

A synchronization signal noise removal device according to the present invention samples an input synchronization signal at a constant period, and synchronizes the input signal when n or more samples among consecutive m points of samples correspond to the synchronization signal level. It is determined that it is a signal and sends it to the subsequent circuit as a synchronization signal.

[Effect]

In this invention, the synchronization signal is sampled at regular intervals, and the input signal is accepted as a synchronization signal only when n or more points (m, 〉n) out of m sample points are at the synchronization signal level. Therefore, even if the synchronization signal contains pulses caused by spike noise, the level of the output synchronization signal will not change due to the influence of the pulses.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a clamp circuit, 2 is a voltage comparator, and 3 is a D flip-flop that samples the output of the voltage comparator 2 in synchronization with a clock. Further, 4 is a shift register, 5 is an inverter circuit, 6 is an AND circuit, 7 is an exclusive N0R (Ex-NOR) circuit, and 8 is, for example, a TTL I
An up/ground counter such as C74169 and 9 are digital data comparators such as TTL IC7485, and each of these circuits 4 to 9 constitutes a determining means for determining whether or not the input signal is a synchronous signal. .

Next, the operation will be explained.

A television signal including a negative synchronizing signal is input from the input terminal 19, and the DC level is determined by the clamp circuit 1. The clamped television signal is passed through voltage comparator 2
Since the reference level VFLEF between the video signal blanking level and the leading edge level of the synchronizing signal is compared, the separated synchronizing signal is taken out as the output of the voltage comparator 2.

It is assumed that the output of the voltage comparator 2 is at a high level in the subsequent logic circuit during the synchronization signal level period, and at a low level during other periods. The output of the voltage comparator 2 is connected to the clock input terminal 12 by the D flip-flop 3.
is launched in synchronization with the clock added to . The output of the D flip-flop 3 is connected to the input of the shift register 4. The clock of shift register 4 is input terminal 12
By using an m-bit shift register, its output has three flip-flops.
The output appears with a delay of m clocks.

Also, to the clock terminal of amplifier/down counter 8,
The clock supplied to the D flip-flop 3 and shift register 4 is applied from an input terminal 12. The up/down counter 8 has a count operation control terminal (EN
P terminal) and up/down switching terminal (U/D terminal), and the ENP terminal is low level (hereinafter abbreviated as "low").
A counting operation is performed when the U/D terminal is at a high level (hereinafter abbreviated as H), and when the U/D terminal is at a high level (hereinafter abbreviated as H), the count is up, and when it is L, the count is down. The ENP terminal has an exclusive NO between the output of the D flip-flop 3 and the output of the shift register 4.
R is added. Therefore, a counting operation is performed when the outputs of the D flip-flop 3 and the shift register 4 do not match, that is, when the respective outputs are L and Hl or H and L. On the other hand, since the logical product of the output of D flip-flop 3 and the inverted output of shift register 4 is added to the U/D terminal, the output of D flip-flop 3 is H, and the output of shift register 4 is When the output of the shift register 4 is H, the counter 8 enters the amplifier count state, and when the output of the D flip-flop 3 is high and the output of the shift register 4 is H, the counter 8 enters the down count state. The count value of the counter 8 is input to the digital data comparator 9,
When the count value exceeds the set value, the output terminal 10 becomes H. It is assumed that the shift register 4 and the counter 8 are reset when the power is turned on.

The above operation will be explained below using the time chart of FIG. When the output signal of the clamp circuit 1 becomes lower than the reference voltage vR applied to the voltage comparator S2, the output of the voltage comparator 2 becomes H as shown in FIG. 2(b). This output is latched by the D flip-flop 3 at the rising edge of the clock shown in FIG.
C)). The launch output C is delayed by m bits (4 bits in the case of Figure 2) in the shift register (Figure 2(d)).
. From Fig. 2 (C1 and Fig. 2 (d)), the counter control terminals (ENP, U/D) are the Fig. 2 (e) (ENP terminal).
And the signal shown in FIG. 2(f) (U/D terminal) is added. Here, if the ENP terminal input shown in FIG. 2(e) goes low at the rising edge of the clock, a counting operation is performed, and at this time the U/D terminal input shown in FIG. 2(f) goes high.
If it is L, it will be a count amplifier, and if it is L, it will be a countdown. That is, as shown in FIG. 2(g), a count-up state occurs between times t1 and t2 shown in FIG. 3) In the above case, the output of the comparator 9 becomes H (FIG. 2(h)).

Also, a countdown occurs between times t2 and t3 and between t4 and t5, and when the counter value reaches 2, the comparator 9
The output of is L.

Here, Fig. 2 (bl) assumes that the synchronization signal contains noise, and since the synchronization signal between times tO and t4 contains noise, the output of voltage comparator 2 We are considering the case where the current is reversed for a short period and becomes L.

In this way, even if the output of the voltage comparator 2 is temporarily inverted due to noise or the like, the level of the output terminal 10 does not change. Also, at times t6 to t7, the output of the voltage comparator 2 is temporarily high.
However, because the pulse width is short, the count value is 3.
Since the output terminal 10 does not reach H, the output terminal 10 does not become H.

As mentioned above, even if the synchronization signal separated and detected by a voltage comparator etc. contains a narrow pulse due to the influence of noise, the output will become high.

Or it never changes from L to H.

Furthermore, in this embodiment, even if a period shift occurs in the synchronization signal due to jitter, for example, it is possible to obtain a synchronization signal with noise removed corresponding to the period shift, and the horizontal synchronization signal can be used directly as a reference signal to display images. It is also effective when digitally processing signals.

In the above embodiment, a clamp circuit and a voltage comparator are used to separate and detect the synchronization signal, but this part could be replaced with any synchronization separation and detection circuit conventionally used in television receivers. You may also use something like this.

Furthermore, if the synchronization signal is transmitted separately from the video signal, the synchronization signal may be directly applied to the input of the D flip-flop shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, an input synchronization signal is sampled, and when n samples out of m consecutive samples correspond to the synchronization signal level, it is determined to be a synchronization signal and output to the subsequent circuit. Therefore, even if the synchronization signal includes a short period of level change due to noise or the like, this can be effectively removed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synchronization signal noise removal device according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining its operation, and FIG. 3 is a diagram showing a horizontal synchronization signal portion of a composite video signal. , FIG. 4 and FIG. 5 are both diagrams showing a synchronizing signal amplitude separation circuit. ■...Clamp circuit, 2...Voltage comparator, 3...
D flip flop, 4... m-bit shift register ζ5... inverter circuit, 6... AND circuit, 7
...Ex-NOR circuit, 8... Counter circuit, 9.
...Digital data comparator. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1 Figure 3 Figure 4 Figure 5 ↓-

Claims (2)

[Claims] (1) In a synchronization signal noise removal device for removing noise contained in a synchronization signal, a synchronization signal amplitude-separated from a composite video signal or a synchronization signal transmitted separately from the video signal is input, and the input synchronization signal is A synchronization signal noise removal device comprising: sampling means for sampling in synchronization with a clock; and determination means for determining a synchronization signal when n samples out of m consecutive samples correspond to a synchronization signal level. (2) The determination means includes a delay means for delaying the sample value obtained by the sampling means by m clocks, and a counter whose clock counting operation is controlled by the non-delayed sample value and the delayed sample value. 2. The synchronization signal noise removal device according to claim 1, further comprising: digital data comparison means for comparing the count output with a preset value n (n<m).