JPS62226246A - Bank memory switching device of microcomputer - Google Patents

Abstract

PURPOSE:To increase an overall arithmetic processing speed by setting the size of a bank area of a memory device at the value >=2 times as large as the area used by a group of data and, at the same time, setting the switching unit of the bank area at the value smaller than the size of the bank area. CONSTITUTION:The address area of a bank area of a memory device 11 is set a a size >=2 times as large as the address area used by a group of data which are written and read at a time. At the same time, the switching unit of the bank area is set at the value smaller than the size of the bank area. Then the address signals A13-A15 received from a CPU 12 are decoded by a decoder circuit 17 and therefore the address signals A12-A19 are sent from an address latch circuit 19 or 20. Thus the bank areas of different address areas are switched. As a result, both bank checking and switching frequencies can be decreased and the overall processing speed is increased with a bank switching device.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention provides a microcomputer that uses a part of a memory device as a bank area and switches between each bank memory arranged in this bank area. The present invention relates to a bank memory switching device.

(Prior Art) In general, in microcomputers, the memory address area that can be specified by the CPU (central processing unit) has C.
There are certain restrictions depending on the size of the PU. For example, in 8-bit configuration CPtJ, it is 64 KB. When specifying more addresses than this, a part of the memory device is set as a bank area, and a plurality of bank memories are arranged in this bank area, and each bank memory is used selectively.

Figure 9 shows such a bank l111! This figure shows a memory device in which an address oo is formed as shown in the figure.
Common part 1 of the boy from oo to 4FFF and address 50
It is composed of a plurality of bank memories 2a to 2e from 00 to FFFF. In this memory device 3, when the instruction 5 of the program 4 as shown in FIG. 10 is read and executed! @Think about the theory. In this case, the execution program is stored in the bank memory 2a, and the basic program is stored in the two bank memories 2b and 2G. Further, a variable A, which is the calculation result of instruction 5 in FIG. 10, is stored in the bank memory 2d. Furthermore, the bank memory 2e contains an array B(1) used when executing instruction 5.
is memorized. Also, program 4 in Figure 10 is
It consists of a line number 6, an instruction 5, and a carriage return (CR) symbol 7 indicating the end of the line of this program 4. The contents of instruction 5 are array B of bank memory 2e.
Read out <1) and multiply it by 5 to calculate the variable △,
This indicates that the variable A is to be stored in the bank memory 2d.

Next, the procedure for executing this program 4 will be explained. That is, line number 6 is skipped and the first character of instruction 5 is read, but at that time the execution of the process is temporarily moved to the common section 1 of the memory device M3, the bank memory to be executed is switched to the basic program 2b, and the character is read. read Thereafter, the execution is transferred to the bank memory 2a to execute the next process. In addition, 1
Every time a character is read, it is checked in the bank memory 2b whether this program 5 has reached the bank end where it moves from the bank memory 2b to the bank memory 2C.

Next, when it is confirmed that this instruction 5 is a calculation instruction, the address of the answer variable A and the bank memory are stored, and the address and bank memory of the array B (1) are calculated. After switching the bank memory to the array bank memory 2e, array data B(1) is read out. Next, multiply the read array data B(1) by 5 to calculate the variable Y, specify the previously stored address of the variable Y and bank 2d, and set it to the corresponding address of the corresponding bank memory 2d. Enter the answer for variable Y. This completes the processing for one instruction 5 of the program 4.

However, the bank memory switching control described above has the following problems. That is, as mentioned above, even if you try to read data in another bank memory from the bank memory that is currently being executed, it is not possible to read it directly. Transfer execution to bank memory and read data.

After that, it is necessary to return to the original bank memory.

In other words, if the execution programs are distributed all at once in each bank memory and the bank memory is only switched occasionally, the time required for switching will not be a problem, but as shown in Figure 9, When processing the data (array B) stored in the memory, it is necessary to switch the bank memory to another bank memory, so there is a problem that the time required for switching increases and the overall processing time increases.

For example, in the examples shown in FIGS. 9 and 10, the number of times bank memories are switched is approximately 20 times, including round trips.

In the examples shown in FIGS. 9 and 10, by first moving the 1st part of the program 4 to the common part 1 of the memory device 3 and then switching the execution to the bank memory 2b of the basic program, Although it is not necessary to perform bank switching, the bank end check in the bank memory 2b described above still needs to be performed for each character.

(Problems to be Solved by the Invention) As described above, in conventional bank memory switching control, the number of bank switching increases and it is necessary to check the bank end for each character of the program, which reduces the overall calculation processing speed. There was a problem with the decline.

The present invention has been made based on these circumstances, and its purpose is to set the size of the bank area of the memory device to more than twice the v4 area used by some data, and to To provide a bank memory switching device for a microcomputer that can reduce the number of bank end checks, reduce the number of bank switches, and increase the overall arithmetic processing speed by making the switching middle of bank 1liiE smaller than the size of the bank area. It's about doing.

[Configuration of the Invention (Means for Solving Problems)] In the bank memory switching device for a microcomputer of the present invention, the address ia of the bank area in the memory device is
The size of R is layered at one time. Address 1 is more than twice the address area used by some data to be processed.
m, and when the CPU specifies an address in bank FALIIE of the memory device, a part of the address signal at the beginning is converted into an address signal output from the bank address latch circuit that specifies each bank memory. When it is determined that a group of data is not stored in one bank area, the bank memory is switched by the address signal of the bank address latch circuit, and the group of data is stored in one bank area. It is.

(Function) With the microcomputer bank memory switching device configured as described above, the size of the address area of the bank area in the memory device is the address area used by part of the data that is processed for write/read operations at one time. 2g! i or more, and the bank area switching unit is bank fI4tii!
For example, if the switching unit is set to 1/2 of the size of the bank area, by setting the start address of the group of data to the first half address position in one bank memory, this data The ending address location of can be placed into the bank memory. Therefore, the number of times the bank end is checked can be reduced. Further, when an address in bank fl(bli) is designated, a part of this address signal is switched to an address signal output from a bank address latch circuit that designates each bank memory.

That is, the processing execution is moved to the bank memory designated by the bank address latch circuit.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a bank memory switching device for a microcomputer according to an embodiment, and FIG. 3 is a memory configuration diagram of a memory device in this bank memory switching device U. In FIG. 3, this memory device 11 is applied to the 8-bit CPU 12 shown in FIG.
It has a total addressable area of 64KB. And this memory device 11 has address alj! ooooo.

~BFFF's 48KB common part 13 and coo.

~DFFF 8KB bank area 14 and EOOO~F
It is composed of an 8KB bank area 15 of FFF.

A plurality of bank memories 14a to 14n and 15a to 15n are arranged in each bank area 14.15, respectively.

As a result, in this memory device 11, including the bank memories 14a to 14n and 15a to 15n, the maximum memory capacity is IMB.

In FIG. 1, the AO-
Of the address signals A15, AO to A11 are input to the memory device 11 as they are. And the remaining A1
Address signals 2 to A15 are input to the gate circuit 16. A from this gate circuit 16 to memory @@11
12 to A19 are sent out. When an L level control signal 18 is applied from the decoder circuit 17, this gate circuit 16 is opened and sends the address signals A12 to A15 sent from the CPU 12 to the memory device 11 as they are, and Ground. In addition, the decoder circuit 17 outputs an H level il I
When the ll signal is input, this gate circuit 16 is opened. That is, A12~ input to the memory device 11
The address signal of A9 is applied to the two bank areas 14 and 15.
Address latch circuit for two banks corresponding to 19.
Address signals A12 to A19 output from one of the address latch circuits of 20 are input.

A13. output from the CPU 12. The address signal of A14゜A15 and the enable (EN) signal that enables the output of the address latch circuits 19 and 20 are supplied to the decoder circuit 1.
7. As shown in FIG. 2, this decoder circuit 17 is composed of an AND gate 21 having three input terminals, two Nant gates 22, 23, and an inverter 24, and includes the two most significant digits A15. When the address signal and EN signal of A14 go high, the control signal 18 output from the AND gate 17 goes high, and the gate circuit 16 is opened. And A15. A14.
A13 and EN signals are at H level, that is, CPU1
2 specifies an address in bank ll1j115 of memory device 11 in FIG. Therefore, the address latch circuit 20 is included in the memory 8111.
Address signals A12 to A19 are sent from the address signals A12 to A19. That is, the bank memories 15a to 15n corresponding to the address signals at the back of the bank memories 15a to 15n are selected.

Also, A15. A14. When the EN signal is at H level and A13 is at L level, that is, when the CPU 12 specifies an address in the bank area [14] of the memory snowmaking 11 shown in FIG.
The operation signal 26 is sent to. Therefore, memory device 1
1, address signals A12 to A19 are sent from the address latch circuit 19. That is, the bank memory 14
Among bank memories a to 14n, bank memories 148 to 14n corresponding to this address signal are selected.

In the bank memory switching device configured in this way,
The case where the program 4 shown in FIG. 10 mentioned above is executed will be explained. In this 51 case, the execution program is in address area 14.
The basic program is stored in the bank memory 14a of the bank memory 14a, the basic program is stored in the bank memories 14b and 14c, and the variable A and the array B(1) are stored in the bank memory 15a of a different address area hi15.

15b. Figure 4 (a>(b)
) are configuration diagrams of memory banks 14b and 14c that respectively store basic programs.

In such a state, when executing the program 4 in FIG. 10, if the first line number 6 exists between cooo and CFFF in the first half of the address area 14, this address @ area 14゜15 The size of this line is more than twice the memory area required to execute the length of one line of the one program 4, that is, the memory area required to read this instruction 5. program 4
There is no need to check the memory end until the execution of On the other hand, line number 6 is from DOOO to D at the memory end.
If it is between FFF, there is a possibility that the memory end of DFFF will be reached by the time the execution of program 4 on this line ends. Therefore, in this case line number 6 is ooo
If it is confirmed that the program exists in the bank memory 14c, the value set in the address latch circuit 19 is increased by 1, and the execution of the program is transferred to the bank memory 14c.
As shown in Figure (b), line number 6 enters C000 to CFFF. Therefore, during the period when this program 4 is executed for one line, it is not necessary to check the bank end for each character as in the conventional case.

In this way, by making the size of the address [of the bank area 14] more than twice the area required to execute the program 4 111 times, and by making the switching unit of the bank area smaller than the size of the bank area, the program 4 can be executed. When executing, first set only the address position of line number 6 to 1.
If the program is checked twice, there is no need to check the -rebank end while the program 4 is being executed, so the overall processing speed using this bank memory can be increased. Furthermore, the tick operation does not need to be checked over all address signals AO to A15, but only the upper 4 digits (bits) or 8 digits (bits) of A12 to A15 need to be checked.

In addition, in the embodiment, two bank areas 14 and 15
are provided, and each bank memory 158 to 15 in the bank area 15
Since I placed variable A and array B (1) in n,
The total number of bank switching can be reduced, and the calculation processing speed can be further increased.

FIGS. 5 and 6 show other embodiments applied to a microcomputer using a 16-bit CPU. That is, as shown in FIG. 5, the memory drawing 31 of this embodiment has a common portion 32 and four bank areas 33, 34 .
35, 36 and another memory area b137. A basic program is stored in each bank memory of the bank area 23, and a basic program is stored in each bank memory of the bank area 23.
Each bank memory 4 stores data such as the variables and arrays, and the bank area 35 is used for interrupt processing. This eliminates the need for switching bank areas many times when an interrupt occurs. Further, the bank area 26 is DM
Used to specify the upper address (A16 to A19) during A (direct memory access). Furthermore, the memory being executed is stored in another memory fj[37.

Note that the contents of each bank memory in each bank area 33 to 36 represent a part of the other memory area 1437, and the same memory can be stored in the other memory area 15137 at its physical location.
It is also possible to access each bank memory in each bank area 33 to 36.

In FIG. 6, the address signal of ADO-ADl 1 output from the 16-bit ℃PtJ 38 is input to the memory device 31 as it is via the latch circuit 39.

Note that this latch circuit 39 is a latch circuit that partially latches only the address signal because the address signal output from the CPU 38 is output in a time-divided state with the data signal.

A12~A15°A16~A output from CPU38
Each of the 19 address signals is input to the latch circuit 40.

When the control signal @42 outputted from the OR gate 41 becomes H level, the latch circuit 40 opens its output terminal.
Address signals A12 to A15 for the memory device 31 are supplied from a bank address latch circuit 43, and A1
Address signals 6 to A19 are supplied from the bank address latch circuit 44.

ADl3. output from the CPU 38. The address signal of ADl4 is inputted via the latch circuit 45 to the bank address latch circuits 43 and 44.

This latch circuit 45 is connected from the CPU 38 to
When the DA signal 46 is input, the output end is opened.

When the bank address latch circuit 43 receives an L level control signal, A13. Address signals A12 to A15 are input to the memory device 31 by a combination of address signals A14. Similarly, when the bank address latch circuit 44 receives an L level control signal, the bank address latch circuit 44
The address signal of A19 is input to the memory 8131. That is, each bank memory is selected by address signals A12 to A19 output from each bank address latch circuit 43,44.

In addition, the H level HLDA output from the C-PU38
The signal 46 is input to the latch circuit 40 via the inverter 47 and the OR gate 41, and is also input to the bank address latch circuit 44 via the NOR gate 48.

Furthermore, the ADI 5° A16 output from the CPU 38
The address signals and EN signals of ~A19 are input to the decoder circuit 49. This decoder circuit 49 outputs an H or L level switching signal 50 to each gate 41, 48 and bank address latch circuit via a latch circuit 45 according to a combination of address signals input during an H level EN signal input period. 43. That is, when the L level switching signal 50 is output, the output terminal of the latch circuit 40 is opened, and address signals A12 to A19 are output from the bank address latch circuits 43 and 44. Also) −
When ILDA signal @46 is at L level and switching signal @50 is at H level, conversely, the latch circuit 40 outputs A12 to A19.
The address signal is input to the memory device 31.

Further, when the HLDA signal 46 at H level is output from the HLDA terminal of the CPU 38 as during DMA operation, address signals A16 to A19 are output from the bank address latch circuit 44, but the address signals A16 to A19 are output from the bank address latch circuit 44. The output terminal is opened and the bank address latch circuit 4
The output end of No. 3 is also opened. Therefore, during DMA operation, AO~
The address signal of A15 is input to the memory device 31, and the address signal of A16 to A is input from the bank address latch circuit 44.
19 address signals are input to the memory device 31.

Even in the microcomputer bank memory switching device configured in this way, the size of the address area in the bank area 33 of the memory device 31 is changed to the bank f in FIG.
By setting it to correspond to the size of the address area in iljbl+14, it is possible to obtain almost the same effect as Moe's actual IM example.

Further, in this embodiment, one bank area 36 out of each bank area 33 to 36 of the memory device 31 is used as a DMA.
Control! For 111, as mentioned above, C
The PU 38 outputs an H-level HLDA signal 46, and the bank address latch circuit 44 outputs upper addresses A16 to A19 specifying each bank memory in the bank area 36. Therefore, even if a DMA LSI that outputs only AO to 15 is used, A16 to A1
9 is output from the bank address latch circuit 44, the bank memory can also be used for DMA.

FIGS. 7 and 8 show still another embodiment applied to a microcomputer using a 16-bit CPU. Components that are the same as those in the embodiment shown in FIGS. 5 and 6 are given the same reference numerals, and explanations of the overlapping parts will be omitted.

The memory device 31 of this embodiment, as shown in FIG.
In addition to the bank areas 33 to 36 shown in FIG. 5, another bank area 5 is provided in address areas 5ooo to BFFFF.
1 is formed, and eight bank memories 518 to 51h from BO to B7 are arranged in the bank area 51.

In FIG. 8, reference numeral 52 indicates each bank memory 51a to 51h of the bank area 51 in the memory device 31, and this bank memory 52 receives address signals of the latch circuits 39.4C1l and AO-A17. is input, and A1 is input from the bank address latch circuit 53.
8. Address signals of A19° and A20 are input. Then, A18. which is output from the latch circuit 40. The address signal A19 is input to the C8 terminal of the bank memory 52 via a decoder circuit consisting of an inverter 54 and an AND gate 55. Of course, this bank memory 52 is capable of write/read operations only when the address signal A18 output from the latch circuit 40 is at L level and the address signal A19 at the highest level is at H level.

The bank address latch circuit 53 receives A13.A13. output from the latch circuit 45. The address signals of A14 are inputted through AND gates 56 and 57, respectively, and the control signal 42 outputted from the OR gate 41 is inputted to the other input terminal of each AND gate 56 and 57.

When using the bank memory switching device configured in this way,
CPU38 is memory device [3117)80000-B F
When one address in the address area 51 of FFF is directly accessed, the address signal of the most significant A19 goes to H level, and the address signal of the next AlB goes to L level. As a result, the switching signal 50 of the decoder circuit 49 becomes H level, and the control signal 42 input to the latch circuit 40 becomes L level. Therefore, the latch circuit 40.
The address signals from 39 to AO to A17 are sent to the bank memory 5.
2, this bank memory 52 becomes operational. Further, when the control signal 42 becomes low level, the A13. Since the address signal A14 is not input, the 0th combination of the four predetermined combinations of address signals A18 to A20 is input from the bank address latch circuit 53 to the bank memory 52.

Further, when the CPU 38 accesses the bank memory in the bank area 34, the control signal @42 becomes H level, contrary to the above, and address signals are sent out from each bank address latch circuit 43, 44. At the same time, the bank address latch circuit 53 receives A13. Address signals A18 to A20 corresponding to the combination of address signals A14 are input to the bank memory 52. That is, one bank memory is selected from the eight bank memories 51a to 51h forming the bank memory 52.

In this state where each bank memory in the bank areas 33 to 36 is accessed, the bank fWiii! corresponding to this bank memory 33 to 36 is accessed. 51 each bank memory 51a
~ 51i1 is automatically switched banks, so multiple bank memories 5
1a to 51h can be accessed.

[Effects of the Invention] As explained above, according to the present invention, the size of the bank area of the memory device is set to be more than twice the area used by some data, and the bank area switching unit is set to the size of the bank area. It is smaller than the size. Therefore, the number of bank end checks can be reduced, the number of bank switches can be reduced, and the overall screening processing speed can be increased.

[Brief explanation of drawings]

1 to 4 are diagrams showing a bank memory switching device for a microcomputer according to a practical example of the present invention,
Fig. 1 is a block diagram showing the entire structure, Fig. 2 is a circuit diagram showing a decoder circuit, Fig. 3 is a memory layout diagram of the memory device, Fig. 4 is a diagram showing bank memory, and Fig. 5 is a diagram showing the main part. A memory layout diagram of a memory device of a bank memory switching device according to another embodiment of the invention, FIG. 6 is a block diagram showing the entire embodiment, and FIG. 7 is a diagram of a bank memory switching device according to still another embodiment of the invention. FIG. 8 is a block diagram showing the entire embodiment, FIG. 9 is a memory layout diagram of the memory device in a conventional device, and FIG. 10 is a diagram showing a program. 11.31...Memory device, 12.38...CPU
. 14.15, 33, 34.35.36...Bank area, 16...Gate circuit, 17.49...Decoder circuit, 19,20.43.44.53...Bank address latch circuit , 39.40.45...Latch circuit. Applicant's agent Patent attorney Takehiko Suzue (a) (b) Figure 4 Figure 7 Figure 9 Figure 110 PRINT A @ Figure 10

Claims (4)

[Claims] (1) In a bank memory switching device for a microcomputer that uses a partial area of a memory device as a bank area and switches between each bank memory arranged in this bank area,
The size of the address area of the bank area is set to be at least twice the size of the address area used by a group of data that is processed in a write/read operation at one time, and the address area in the bank area of the memory device is transmitted from the CPU to the address area. When specified, a part of this address signal is switched to an address signal output from a bank address latch circuit that specifies each bank memory, and it is determined that the group of data is not stored in one bank area. A bank memory switching device for a microcomputer, characterized in that the bank memory is switched by an address signal of the bank address latch circuit, and the group of data is stored in one bank area. (2) A bank memory switching device for a microcomputer according to claim (1), characterized in that a plurality of bank areas are provided in the memory device. (3) The microcomputer according to claim (2), wherein one bank area of the plurality of bank areas is used as an addressing bank area during a direct memory access operation. Bank memory switching device. (4) The bank memory switching device for a microcomputer as set forth in claim (2), wherein one bank area of the plurality of bank areas is a bank area exclusively used for interrupts.