JPS6227825A - General-purpose high-speed processor - Google Patents

Abstract

PURPOSE:To attain both the high-speed operation and the universal applicability by providing a low-speed memory containing programs at the outside of a chip together with a high-speed memory for development of programs set inside of the chip and also providing a function which initializes programs to the high-speed memory from the low-speed memory. CONSTITUTION:A low-speed EP-ROM 111 is provided together with a high-speed RAM 110 and therefore the high-speed processing is possible with a processor 1 after initialization. Then, the contents of the RAM 110 can be changed with rewriting of the contents of the EP-ROM 111. Thus, it is possible to provide the universal applicability to the processor 1. However, it is needed to reduce the working speed of the processor 1 compared with the normal working speed level in an initialization mode. For this purpose, a clock control circuit 112 is added together with a dividing circuit 113.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a general-purpose high-speed processor in which a RAM is used as a program memory within the processor.

[Conventional technology]

Conventional one-chip high-speed processors are classified as shown in FIGS. 7 to 9 depending on the type of memory in which programs are stored. FIG. 7 shows the mask ROM (
read-only memory) 100 is the program memory,
Further, in FIG. 8, the external ROM10I becomes the program memory. A data memory 102 uses RAM (Random Access Memory). D-BUS
is a data bus, P-BUS is a program bus, 103 is a controller, 104 is a register, 105 is a shifter, 1
06 is a multiplier, and 107 is an ALU for addition and subtraction. 9th
The figure shows a system using EP-ROM (electrically writable ROM), but since it cannot be accessed directly from the high-speed processor 1, a low-speed program transfer circuit 3 is used to transfer program data from the EP-ROM to the RAM. There is.

In the figure, 1 is a high-speed processor (Main CPU) dedicated to digital signal processing, 2 is a high-speed memory block, and 3 is a low-speed program transfer circuit.

There are a clock generation circuit 11, a reset circuit 12, a power supply circuit 13, an I10 controller 14, etc. around the CPU 1, and by combining these hardware and the program in the memory block 2, one signal processing system is configured. This example is mainly used as a program development tool, and as an example, a low-pass filter ( LPF) function is realized. The CPUI and the memory block 2 are connected by a data bus D-BUS and an address bus A-BUS, and a bidirectional path transceiver 41 and a unidirectional buffer 42 are interposed between them.

The main memory block 2 includes memory 21 (RAMI
), a memory 22 (RAM2), and a memory controller (decoder) 23. FIG. 10 shows the details of the memory controller 23, in which the write enable WE from the CPUI is input to the terminal (2), the memory enable MEN is input to the terminal (2), and the address ADR (H) is input to the terminal (2). Terminal ■■ is a memory enable output EN for RAMI and RAM2, and terminal ■■ is its write enable output WEN. This memory controller is a simple decoder that switches between RAMI and RAM2 with address ADR (H).

Table 1 shows this decoding logic.

Table 1 The program transfer circuit 3 includes a sub-memory block 5 and a sub-low-speed processor 6, and around them are a clock generation circuit 61, a reset circuit 62, and a power supply circuit 63. Further, a bidirectional path transceiver 71 is provided on the data bus D-BUS, and a unidirectional buffer 7 is provided on the address bus A-BUS.
2 is intervening. Memory block 5 is memory 51
(RAM 3) and a memory 52 (EP-ROM), an address decoder 53 is provided, and this EP-ROM serves as a storage location for programs.

I will explain the entire operation. When power supply circuit 13.63 is turned on,
First, the sub CPU 6 starts operating, turns off the path transceiver 41 and buffer 42 between the main CPU 1 and the main memory block 2, and separates the bus between them.

On the contrary, the path transceiver 71 and buffer 72 are turned on to connect the buses of the six sub-CPUs to the main memory block 2. Then, the sub CPU 6 accesses the memory block 5 and transfers the data read from the EP-ROM (program executed by the main CPU) to the RAMI of the main memory block 2.

When this is executed up to the specified address, the transceiver 71
and turns off buffer 72 and turns on transceiver 41 and buffer 42 instead. Until this time, the reset control signal R has been input to the main side reset circuit 12 from the sub CPU 6, so the main CPU is in a reset state and stopped. Then, when the program transfer is completed and the signal R is turned off, the main CPUI starts operation (for example, LPF processing).

[Problem that the invention seeks to solve]

Since the configuration shown in FIG. 7 can be processed within the chip, there is no need to draw out the pass line to the outside, the wiring length of the pass line can be shortened, and it is suitable for high-speed operation. However, since the program is converted into hardware, it is difficult to change it, and the processor itself lacks versatility, making it unsuitable for small-scale production or program development.

Although the configuration shown in FIG. 8 maintains the versatility of the processor itself, the internal path lines must be brought out outside the chip, resulting in longer wiring lengths and is disadvantageous compared to FIG. 7 in terms of high speed. In addition, since the external ROM also requires processor access speed and high speed, EP-R
Memory with relatively slow access speed, such as OM, cannot be used and is not suitable for program development.

The configuration in Figure 9 has longer path line wiring lengths as in Figure 8, and is less fast than Figure 7, but since the program memory is RAM, it is easy to change the program, making it convenient for program development. It is.

However, since the system becomes large-scale, it is difficult to meet the needs for compact size and low cost.

The present invention aims to achieve both high speed and versatility by using RAM as the program memory built into the processor.

[Means for solving problems]

The present invention provides a low-speed memory storing a program outside the chip, a high-speed memory for expanding the program inside the chip, and a function to initialize the program from the low-speed memory to the high-speed memory and a function to execute the program. The details of its structure and operation will be explained together with the illustrated embodiments.

〔Example〕

FIG. 1 shows one embodiment of the present invention, and the same parts as in FIG. 7 are given the same reference numerals. This example also uses a system in which a program memory is built into the processor 1, but unlike in FIG. 7, it is implemented in the RAM 110.

However, since RAM is volatile, an external program memory 111 using EP-ROM is provided, and the RA
Initialize (load) the program to MI10. 110' is a small capacity program ROM that stores an initialization program for this purpose. In this way, BP-ROMI 11 is slow, but the RAM
Since I10 is high-speed, high-speed processing by the processor is possible after initialization. Also EP-ROM
Since the contents of RAMll0 can be changed by rewriting the contents of 111, the processor can be made versatile.

However, high-speed processor 1 directly supports low-speed EP-ROMI.
In order to make the processor 11 accessible, it is necessary to lower the operating speed of the processor 1 during initialization than during normal operation. 112 and 113 are clock control circuits and frequency dividing circuits for this purpose, and FIG. 2 is a detailed diagram thereof. The clock control circuit 112 is a D-type flip-flop F.
It can be realized by F, and when reset by the output of the reset circuit 12, the Q output is set to "O", and the gate of the frequency dividing circuit 113) G+
is opened to output a low-speed clock from the 1/an frequency divider. This low-speed clock causes the EP-ROM111 to
The program is loaded into AMll0. When this initialization is completed, the controller 103
sets the clock control output CC to 51'', so the flip-flop FF sets the Q output to "1" and opens the gate G2.

As a result, a high-speed clock is output from the 1/n frequency divider,
Processor 1 can access the program in RAMll0 at high speed.

FIG. 3 is an explanatory diagram of the program memory, in which (a) is the internal memory 110S (bl is the external memory 111).

The internal memory from addresses △△Δ+1 to Rororo is for programming (RAM), and the external memory (EP-ROM) is located here.
) program is initialized. Internal memory 1
000 to △△△ of 10 is a mask ROMI 10' that stores this initialization program, and by executing this initialization program after resetting, the processor 1 reads RAMI from EP-ROMI 11.
1 (l main program can be loaded. 4th
The figure is a flowchart showing the contents of this initial program.

FIG. 5 shows another embodiment of the present invention, in which the external memory 111+~
n types of programs are stored in the internal memory 110, and one of them can be selected by a switch 112 and initialized in the internal memory 110. In this way,
For example, by storing filter programs with different attenuation amounts and cutoff frequencies in each external memory, it is possible to configure a fixed tone control circuit that can realize any frequency characteristic by the user's switch operation.

In FIG. 6, the addresses of the program memories 110 and 111 are made consecutive so that the initial program in the program ROM can be accessed without being particularly aware of the external memory. At this time, if the clock is set to a low speed, there is no need to consider the difference in access speed with the internal memory.

〔Effect of the invention〕

As described above, according to the present invention, the versatility of the processor itself can be maintained, so the same processor can be used for various types of processing, and costs can be reduced due to its mass production effect. Further, since a low-speed EP-ROM or EEP-ROM can be used as the external memory during development, and a ROM can be used after development, it is possible to reduce development costs and shorten the development period for small-volume production.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a detailed diagram of the clock switching circuit, Fig. 3 is an explanatory diagram of the program memory, Fig. 4 is a flow chart of the initialization program, and Fig. 5 is a detailed diagram of the clock switching circuit. FIG. 6 is a block diagram showing another embodiment of the present invention; FIG. 6 is an explanatory diagram showing another example of a program memory; FIGS. 7 to 9 are block diagrams showing different examples of a conventional processor and program memory; FIG. 10 is a detailed diagram of the memory controller of FIG. 9. In the figure, 1 is a processor, 110 is an internal program memory (RAM), 111 is an external program memory, and 112
．． 113 is a clock switching circuit. Applicant Fujitsu Ten Ltd. Representative Patent Attorney Minoru Aoyagi Kuro 7F Moon Wedge Circuit Diagram 2 (d) Internal 1 Sn'
(1)) % Memo Sore 0 Gefm T Morinishi 〒 17 ° O -ga 9m Hm 70- ÷ 7 ° Roppumume T -Ni -T -Ni -T -Tori 7T Ricon -torch 1 Police Figure 10

Claims (2)

[Claims] (1) A low-speed memory storing a program is provided outside the chip, a high-speed memory for expanding the program is provided inside the chip, and a function for initializing the program from the low-speed memory to the high-speed memory and a function for executing the program are provided. A general-purpose high-speed processor characterized by: (2) The general-purpose high-speed processor according to claim 1, wherein the operating speed during initialization from low-speed memory to high-speed memory is lower than during normal operation.