JPS62217486A - Manufacture of magnetic bubble memory chip - Google Patents

Manufacture of magnetic bubble memory chip

Info

Publication number
JPS62217486A
JPS62217486A JP61059758A JP5975886A JPS62217486A JP S62217486 A JPS62217486 A JP S62217486A JP 61059758 A JP61059758 A JP 61059758A JP 5975886 A JP5975886 A JP 5975886A JP S62217486 A JPS62217486 A JP S62217486A
Authority
JP
Japan
Prior art keywords
insulating layer
pattern
bubble
interlayer insulating
conductor pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61059758A
Other languages
Japanese (ja)
Inventor
Yusuke Nakagawa
裕介 中川
Hiroshi Inoue
博史 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61059758A priority Critical patent/JPS62217486A/en
Publication of JPS62217486A publication Critical patent/JPS62217486A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve bubble transfer characteristics by removing the surface part of an insulating layer between layers which swells because of a conductor pattern and flattening a soft magnetic pattern. CONSTITUTION:An insulating layer 2, the conductor pattern 3, and the interlayer insulating layer 3 are laminated on a bubble crystal layer 1 and a swelling part 6 is exposed to form resist 7. Then, plasma etching is performed by a parallel flat plate type dry etching device to remove the swelling part 6 and flatten the interlayer insulating layer 4, and then resist 7 is removed by ashing. Then, a 'Permalloy(R)' pattern 5 is formed on the surface of the interlayer insulating layer 4 to obtain a chip with improved operation margin characteristics. Consequently, the operation margin characteristics at the intersection part of the conductor patterns are widened and the operation margin characteristics at a nonintersection part become nearly equal, so that a high- density bubble memory with a wide operation margin is realized.

Description

【発明の詳細な説明】 〔概要〕 本発明は、磁気バブルメモリチップの導体パターンによ
って隆起した層間絶縁層の表面部分を除去し、軟磁性パ
ターンが形成される層間絶縁層表面の平坦化を行ない、
それによって軟磁性パターンの平坦化を図りバブル転送
特性を向上されたものである。
[Detailed Description of the Invention] [Summary] The present invention removes the surface portion of the interlayer insulating layer raised by the conductor pattern of a magnetic bubble memory chip, and flattens the surface of the interlayer insulating layer on which the soft magnetic pattern is formed. ,
This flattens the soft magnetic pattern and improves bubble transfer characteristics.

〔産業上の利用分野〕[Industrial application field]

本発明は磁気バブルメモリチップの製造方法に関する。 The present invention relates to a method of manufacturing a magnetic bubble memory chip.

バブルメモリはOA機器等種々の機器にも使用され、そ
の使用量は年々増加する傾向にある。
Bubble memory is also used in various devices such as office automation equipment, and its usage tends to increase year by year.

この種バブルメモリは今日4Mb i を容量が製品化
され、16Mbit容量のものも研究開発されている。
This type of bubble memory is now commercialized with a capacity of 4 Mbit, and one with a capacity of 16 Mbit is also being researched and developed.

このような高密度バブルメモリにはバブル径がサブミク
ロンのバブルを用いて実現されるが、バブルの微少化に
伴ない動作マージンが劣化する傾向にある。
Such high-density bubble memories are realized using bubbles with submicron diameters, but as the bubbles become smaller, the operating margin tends to deteriorate.

従って、動作マージンの広い高密度バブルメモリの実現
が要望されている。
Therefore, it is desired to realize a high-density bubble memory with a wide operating margin.

へ2− 〔従来の技術〕 第3図ta+ (b)は従来の磁気バブルメモリチップ
におけるメジャー転送路部分の断面図である。
B2- [Prior Art] FIG. 3 (b) is a sectional view of a major transfer path portion in a conventional magnetic bubble memory chip.

図において、1は非磁性ガーネット基板上に液相エピタ
キシャル成長法にて形成されたガドリニウム−ガリウム
−ガーネット等からなるバブル結晶層、2はバブル結晶
Nl上にスパッタ形成された3402等からなる絶縁層
、3はスワップやレプリケート等の機能ゲートを構成す
るAu等からなるバブル制御用導体パターン、4は導体
パターン3の平坦化を目的としてPLO3(ポリラダー
オルガ)シロキサン樹脂)等の耐熱性樹脂を塗布−熱硬
化してなる層間絶縁層、5はバブル転送用の軟磁性体か
らなるパーマロイパターン、6は層間絶縁N4の導体パ
ターン3による隆起部分である。
In the figure, 1 is a bubble crystal layer made of gadolinium-gallium-garnet etc. formed on a non-magnetic garnet substrate by liquid phase epitaxial growth, 2 is an insulating layer made of 3402 etc. formed by sputtering on bubble crystal Nl, 3 is a conductor pattern for bubble control made of Au, etc. that constitutes a functional gate such as swap or replicate, and 4 is a heat-resistant resin such as PLO3 (Poly Ladder Orga) siloxane resin applied for the purpose of flattening the conductor pattern 3. An interlayer insulating layer formed by thermosetting, 5 a permalloy pattern made of a soft magnetic material for bubble transfer, and 6 a raised portion of the interlayer insulating layer N4 formed by the conductor pattern 3.

第3図はメジャー転送路部分と異なりfb1図の如く導
体パターン3とパーマロイパターン4との重なり部を有
する。
Unlike the major transfer path portion, FIG. 3 has an overlapping portion between the conductive pattern 3 and the permalloy pattern 4 as shown in FIG. fb1.

従来においては、(a)図の如く樹脂による層間絶縁N
4にて導体パターン3の平坦化を行なった後。
In the past, (a) interlayer insulation N using resin as shown in the figure
After flattening the conductor pattern 3 in step 4.

(b)図の如くパーマロイパターン4を形成し、しかる
後回示せぬ保護層を被覆して形成していた。
(b) As shown in the figure, a permalloy pattern 4 was formed, and then a protective layer (not shown) was coated.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来は層間絶縁層4によりかなりの平坦化は実現できる
が、隆起部分6を完全になくすことはできず、パーマロ
イパターン5には図示すように段差を生じバブル転送特
性が劣化する。
Conventionally, considerable flatness can be achieved by using the interlayer insulating layer 4, but the raised portions 6 cannot be completely eliminated, and the permalloy pattern 5 has a step difference as shown in the figure, which deteriorates the bubble transfer characteristics.

このため、第4図の如く導体パターンとの交差部分の動
作マージン特性Aは導体パターンとの交差なし部分の動
作マージン特性Bに比ベマージン幅が狭くなる。
Therefore, as shown in FIG. 4, the operating margin characteristic A at the intersection with the conductor pattern has a narrower margin width than the operating margin characteristic B at the area without intersection with the conductor pattern.

尚、第4図は第3図のチップをバイアス磁石や駆動コイ
ル等と組合せてメモリデバイスに組立てた状態における
バイアス磁界と駆動磁界との関係における動作マージン
を示しており、この際のバブル径は約1.3μm、パー
マロイパターンのバタ右 一ン周期は約4みで−mである。
Furthermore, Fig. 4 shows the operating margin in the relationship between the bias magnetic field and the drive magnetic field when the chip shown in Fig. 3 is assembled into a memory device by combining it with a bias magnet, a drive coil, etc., and the bubble diameter in this case is It is about 1.3 .mu.m, and the batten period of the permalloy pattern is about 4 -m.

そして、このような動作マージンはバブル径の微少化に
より増々劣化する傾向にある。
Such an operating margin tends to deteriorate further as the bubble diameter becomes smaller.

rLJIIf1点を解決するための手段〕本発明は上記
従来の問題点を解決するため。
rLJIIf Means for Solving Point 1] The present invention aims to solve the above-mentioned conventional problems.

層間絶縁層形成後で軟磁性パターン形成前に、導体パタ
ーンが位置する層間絶縁層の隆起部分を除去し平坦化さ
せる工程を有し、軟磁性パターンが層間絶縁層上に形成
される磁気バブルメモリチップの製造方法を提供した。
A magnetic bubble memory in which the soft magnetic pattern is formed on the interlayer insulating layer, which includes a step of removing and flattening the raised part of the interlayer insulating layer where the conductor pattern is located after forming the interlayer insulating layer and before forming the soft magnetic pattern. Provided a method for manufacturing chips.

〔作用〕[Effect]

隆起部分の除去工程によりほぼ完全な導体パターンの平
坦化ができるため、パーマロイパターンは段差がなくな
りバブル転送特性の向上が図れる。
Since the process of removing the raised portions allows the conductor pattern to be almost completely flattened, the permalloy pattern has no steps and improves bubble transfer characteristics.

〔実施例〕〔Example〕

第1図(al〜(e)は本発明の磁気バブルメモリチッ
プの製造方法を説明する図で、従来と同様メジャー転送
部分におけるゲート部の断面図である。
FIGS. 1A to 1E are diagrams illustrating the method of manufacturing a magnetic bubble memory chip of the present invention, and are sectional views of the gate portion in the major transfer portion as in the conventional method.

図において、符号1〜6は従来と同じ構成を示し、7は
隆起部除去用のレジストを示す。
In the figure, numerals 1 to 6 indicate the same structure as the conventional one, and 7 indicates a resist for removing the raised portion.

本実施例の工程は(81図の如くバブル結晶Fil上に
絶縁層2.導体パターン3.層間絶縁N4を積層形成し
た後、(b)図の如く隆起部分6が露出するようにレジ
スト7を被覆形成する。この後平行平板型ドライエツチ
ング装置を用いてプラズマエツチングして隆起部分6を
除去し層間絶縁層4を平坦化させる((C)図)。しか
る後、レジスト7を灰化除去して(d1図の状態とし、
その後層間絶縁層4の表面上にパーマロイパターン5を
形成すれば(81図の如き本発明に係る磁気バブルメモ
リチップが得られる。
The process of this example is as shown in Figure 81, after laminating the insulating layer 2, conductor pattern 3, and interlayer insulation N4 on the bubble crystal Fil, (b) applying the resist 7 so that the raised portion 6 is exposed as shown in the figure. After that, plasma etching is performed using a parallel plate type dry etching device to remove the raised portion 6 and flatten the interlayer insulating layer 4 (Figure (C)).Then, the resist 7 is ashed and removed. (As shown in figure d1,
Thereafter, a permalloy pattern 5 is formed on the surface of the interlayer insulating layer 4 (a magnetic bubble memory chip according to the present invention as shown in FIG. 81 is obtained).

第2図は第1図のチップをバブルメモリデバイスに組上
げた際の動作マージンを示す。
FIG. 2 shows the operating margin when the chip shown in FIG. 1 is assembled into a bubble memory device.

これは第4図と同条件下での測定結果であり。This is a measurement result under the same conditions as in Fig. 4.

本発明においては導体パターンとの交差部分の動作マー
ジン特性Aが広くなり、導体パターンとの交差なし部分
の動作マージン特性Bとほぼ等しくなる。
In the present invention, the operating margin characteristic A at the intersection with the conductor pattern is widened and becomes almost equal to the operating margin characteristic B at the section without intersection with the conductor pattern.

=6− 〔発明の効果〕 以上の本発明によれば動作マージンの広い高密度バブル
メモリを実現でき、その実用上の効果は著しいものであ
る。
=6- [Effects of the Invention] According to the present invention described above, a high-density bubble memory with a wide operating margin can be realized, and its practical effects are remarkable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al〜telは本発明の製造工程を示す断面図
、第2図は本発明に係るバブルメモリデバイスの動作マ
ージン特性図、第3図+a) (blは従来の製造工程
を示す断面図、第4図は従来のバブルメモリデバイスの
動作マージン特性図である。 〔符号の説明〕 1−・−一一一 バブル結晶層。 2  −一−−−−− 絶縁。 3  −一−−−−− 導体パターン。 4 −−−−−−−一 層間絶縁層。 5 −・−・−軟磁性パターン。 6  −−−−−−−−一 隆起部分。 、)#蛎の襞血工膠ε1祷卯− 第 1 ロ 本発明め製造工程を示す断面図 第 1 図 4θ   5θ   lθ   7θ 欺動石放5R−rθe) 発明1乙係るバ乃しヌtり執゛イズの動イ乍マージン第
2図
Figure 1 (al to tel is a cross-sectional view showing the manufacturing process of the present invention, Figure 2 is an operating margin characteristic diagram of the bubble memory device according to the present invention, Figure 3+a) (bl is a cross-sectional view showing the conventional manufacturing process. 4 are operating margin characteristics diagrams of conventional bubble memory devices. [Explanation of symbols] 1-.-111 Bubble crystal layer. 2-1-- Insulation. 3-1-- −−− Conductor pattern. 4 −−−−−−−1 Interlayer insulating layer. 5 −・−・−Soft magnetic pattern. 6 −−−−−−−−1 Raised part. 4θ 5θ lθ 7θ 5R-rθe) Invention 1B Cross-sectional view showing the manufacturing process of the present invention Figure 2

Claims (1)

【特許請求の範囲】 少なくとも磁気バブル結晶層上に絶縁層を介しバブル制
御用導体パターンが形成され、その上に絶縁性樹脂材か
らなる層間絶縁層が形成され、該絶縁層上に複数個のバ
ブル転送用軟磁性パターンが形成されている磁気バブル
メモリチップにおいて、 前記層間絶縁層形成後で前記軟磁性パターン形成前に、
前記導体パターンが位置する前記層間絶縁層の隆起部分
を除去し平坦化させる工程を有し、前記軟磁性パターン
が該除去部分を含む前記層間絶縁層の表面に形成される
ことを特徴とした磁気バブルメモリチップの製造方法。
[Claims] A bubble control conductor pattern is formed on at least the magnetic bubble crystal layer via an insulating layer, an interlayer insulating layer made of an insulating resin material is formed on the conductor pattern, and a plurality of conductor patterns are formed on the insulating layer. In a magnetic bubble memory chip on which a soft magnetic pattern for bubble transfer is formed, after forming the interlayer insulating layer and before forming the soft magnetic pattern,
A magnetism comprising the step of removing and flattening a raised part of the interlayer insulating layer where the conductor pattern is located, and the soft magnetic pattern is formed on the surface of the interlayer insulating layer including the removed part. Method of manufacturing bubble memory chips.
JP61059758A 1986-03-18 1986-03-18 Manufacture of magnetic bubble memory chip Pending JPS62217486A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61059758A JPS62217486A (en) 1986-03-18 1986-03-18 Manufacture of magnetic bubble memory chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61059758A JPS62217486A (en) 1986-03-18 1986-03-18 Manufacture of magnetic bubble memory chip

Publications (1)

Publication Number Publication Date
JPS62217486A true JPS62217486A (en) 1987-09-24

Family

ID=13122481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61059758A Pending JPS62217486A (en) 1986-03-18 1986-03-18 Manufacture of magnetic bubble memory chip

Country Status (1)

Country Link
JP (1) JPS62217486A (en)

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