JPH0223674A - Connection of wiring - Google Patents
Connection of wiringInfo
- Publication number
- JPH0223674A JPH0223674A JP63173311A JP17331188A JPH0223674A JP H0223674 A JPH0223674 A JP H0223674A JP 63173311 A JP63173311 A JP 63173311A JP 17331188 A JP17331188 A JP 17331188A JP H0223674 A JPH0223674 A JP H0223674A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- connection
- connection portion
- thin film
- superconducting material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 12
- 239000013078 crystal Substances 0.000 abstract description 7
- 239000010410 layer Substances 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002887 superconductor Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Manufacturing Of Electrical Connectors (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は基板上に形成された超電導材料による配線と、
他の配線との接続方法に関するものであり、具体的には
超電導材料を配線や素子(例えばジョセフソン素子)に
使った集積回路やセンサーの接続方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to wiring made of superconducting material formed on a substrate,
It relates to a method of connecting with other wiring, and specifically relates to a method of connecting integrated circuits and sensors that use superconducting materials for wiring and elements (for example, Josephson elements).
従来の技術
第4図(a)は従来の代表的な配線の接続を示した平面
図であり、第4図(b)は第4図(a)のAB線におけ
る断面図である。基板4上において第1の配線1と第2
の配線2が層間絶縁層3の開口部7で接続されている。BACKGROUND ART FIG. 4(a) is a plan view showing a typical conventional wiring connection, and FIG. 4(b) is a sectional view taken along line AB in FIG. 4(a). On the substrate 4, the first wiring 1 and the second wiring
The wiring 2 is connected through the opening 7 of the interlayer insulating layer 3.
第4図において第1の配線lが超電導材料による配線で
ある。In FIG. 4, the first wiring 1 is a wiring made of a superconducting material.
発明が解決しようとする課題
超電導材料を用いた第1の配線と第2の配線(第2の配
線については超電導材料に限定しない)を接続する場合
、しばしは配線間の接続性能が問題となる。配線間の接
続部では抵抗が生したり、あるいは流すことのできる電
流値が制限されたりする(超電導体配線どうしの接続で
あってもジョセフソンジャンクションを作りやすく抵抗
成分が生じたり電流値の制限が起こる)。とりわけ第1
の配線自体は超電導材料であり零抵抗あるいは大きな臨
界電流をもつという優れた性質があるにも関わらず、実
際には配線の能力が接続部の特性で律速されてしまうこ
とが多い。Problems to be Solved by the Invention When connecting a first wiring and a second wiring using superconducting materials (the second wiring is not limited to superconducting materials), the connection performance between the wirings often becomes a problem. . Resistance occurs in connections between wires, or the current value that can flow is limited (even when connecting superconductor wires, it is easy to create a Josephson junction, creating a resistance component or limiting the current value) occurs). Especially the first
Although the wiring itself is made of superconducting material and has excellent properties such as zero resistance or large critical current, in reality, the performance of the wiring is often limited by the characteristics of the connections.
原理的には接続部の面積を大きくすれば、接続部の抵抗
は減少し、流せる電流値も増大する。しかしながら単純
に面積を大きくする事は集積回路やセンサーの面積が大
きくなり実用的でなく、小面積で効率よく配線の接続を
行なうことが重要である。In principle, if the area of the connection section is increased, the resistance of the connection section will decrease and the current value that can flow will also increase. However, simply increasing the area increases the area of the integrated circuit and sensor, which is not practical, and it is important to efficiently connect wiring within a small area.
本発明は、そのような要望を満足する配線の接続方法を
提供することを目的とする。An object of the present invention is to provide a wiring connection method that satisfies such demands.
課題を解決するための手段
本発明は、 基板上に形成された超電導材料による第1
の配線に、複数の小孔もしくは凹凸を形成した接続部を
作り、前記接続部に第2の配線の一部を重ねるように形
成し、前記第1の配線と前記第2の配線を電気的に接続
するものである。Means for Solving the Problems The present invention provides a first method using a superconducting material formed on a substrate.
A connecting portion with a plurality of small holes or irregularities is formed in the wiring, a part of the second wiring is formed so as to overlap with the connecting portion, and the first wiring and the second wiring are electrically connected. It is connected to.
作用
上記手段により回路レイアウトとして配線どうしの重な
り部は同程度でも、配線間の接続面積が増大し、接続部
の抵抗が減少し、流せる電流値(許容電流)が増大する
。Effect: With the above means, even if the overlapping portions of the wires are the same in the circuit layout, the connection area between the wires increases, the resistance of the connection portion decreases, and the current value (allowable current) that can flow increases.
実施例 以下、本発明の実施例を図面をもとに説明する。Example Embodiments of the present invention will be described below with reference to the drawings.
第1図(a)、 (b)は本発明の第1の実施例の配線
の接続部を示したものである(従来の第4図と同一構成
要素には同一符号を記している)。本実施例では超電導
材料として導電性に異方性を有するYBa2Cu3Ox
単結晶からなる第1の配線1′と第2の配線2の接続を
行なっている。眉間絶縁層30開口部7における第1の
配線1′に凹凸をつけ、その上に第2の配線2の形成を
行い接続を行なった。この接続方法を行なうことにより
、開口部7の面積が従来と同一であっても接続抵抗が半
分以下となり、許容電流が増加した。FIGS. 1(a) and 1(b) show the wiring connections of the first embodiment of the present invention (the same components as in the conventional FIG. 4 are denoted by the same reference numerals). In this example, YBa2Cu3Ox, which has anisotropy in conductivity, is used as a superconducting material.
A first wiring 1' made of single crystal and a second wiring 2 are connected. The first wiring 1' in the opening 7 of the glabella insulating layer 30 was made uneven, and the second wiring 2 was formed thereon and connected. By using this connection method, even if the area of the opening 7 is the same as the conventional one, the connection resistance is reduced to less than half, and the allowable current is increased.
第2図(a)、 (b)は第1図の接続を行なう際の、
第1の配線の凹凸の形成方法を示したものである。第2
図(a)は、基板4上に第1の配線1′を形成した後に
眉間絶縁層3を形成し、開口部7を開けた状態に薄膜8
を被着した状態を示している。この場合 薄膜8はスパ
ッタ法によるものでありamな穴9が多数開いている(
薄膜8の材質、膜厚、作成条件を調整することにより穴
9の数を調整できる)。この状態で超電導材料の一部を
エツチングすると第2図(b)のように、開口部70部
分に凹部6が多数生じる。この後、薄膜8を除去し第2
の配線2を形成して第1図の状態となる。Figures 2 (a) and (b) show the connections shown in Figure 1.
This figure shows a method for forming unevenness in the first wiring. Second
Figure (a) shows that after forming the first wiring 1' on the substrate 4, a glabellar insulating layer 3 is formed, and a thin film 8 is formed with an opening 7 opened.
It shows the state where it is covered. In this case, the thin film 8 is made by sputtering and has many holes 9 (
The number of holes 9 can be adjusted by adjusting the material, film thickness, and production conditions of the thin film 8). When a part of the superconducting material is etched in this state, many recesses 6 are formed at the opening 70, as shown in FIG. 2(b). After that, the thin film 8 is removed and the second
After forming the wiring 2, the state shown in FIG. 1 is obtained.
第3図(a)、(b)は本発明の第2の実施例の配線の
接続部を示したものである(従来の第4図と同一構成要
素には同一符号を記している)。超電導材料として導電
性に異方性を有するYBa2Cu3Ox単結晶からなる
第1の配線1目と第2の配線2の接続を行なっている。FIGS. 3(a) and 3(b) show the wiring connections of the second embodiment of the present invention (the same components as in the conventional FIG. 4 are denoted by the same reference numerals). A first wiring line 1 and a second wiring line 2 made of a YBa2Cu3Ox single crystal having anisotropic conductivity as a superconducting material are connected.
本実施例では開口部70部分に第1の配線の膜厚と同程
度の幅の溝10を多数形成した。溝10を作るのに半導
体素子を作るのに通常用いられるフォトリソグラフィの
技術を用いた。この接続方法を行なうことにより、開口
部7の面積が従来と同一であっても接続抵抗が半分以下
となり、許容電流が増加した。In this example, a large number of grooves 10 having a width comparable to the film thickness of the first wiring were formed in the opening 70 portion. To create the groove 10, a photolithography technique commonly used for manufacturing semiconductor devices was used. By using this connection method, even if the area of the opening 7 is the same as the conventional one, the connection resistance is reduced to less than half, and the allowable current is increased.
また本発明による接続の改良は、YBa2Cu3Oxの
ような導電性に異方性を有する超電導材料を使う場合に
特に大きかった。これは、通常YBa2Cu3Oxのよ
うな層状酸化物超電導体単結晶を形成する場合、臨界電
流の小さいC軸を基板面に垂直に成長させる、このとき
の結晶の向きが関係しているためと推定される。従来の
第4図のような基板に平行な面のみでの接続では、接触
面を流れる電流の向きは臨界電流の小さい方向に限定さ
れていたのに対し、本発明を施した接続では臨界電流の
大きな方向の接続が含まれており、そのため効果が大き
くなったと考えられる。Furthermore, the connection improvements of the present invention were particularly significant when using superconducting materials with anisotropic conductivity, such as YBa2Cu3Ox. This is presumed to be due to the fact that when forming a layered oxide superconductor single crystal such as YBa2Cu3Ox, the C-axis with a small critical current is grown perpendicular to the substrate surface, and the orientation of the crystal at this time is related. Ru. In the conventional connection made only on the plane parallel to the substrate as shown in Fig. 4, the direction of the current flowing through the contact surface was limited to the direction where the critical current was small. It is thought that this included connections in a large direction, which is why the effect was large.
発明の効果
以上述べたように本発明は、回路レイアウトと従来に比
へ配線の能力向上による設計マージンが向上したり、逆
に接続部の回路レイアウトを小さくして集積回路やセン
サーを小型化することができるようになった。Effects of the Invention As described above, the present invention improves the design margin by improving the circuit layout and wiring ability compared to the conventional one, and conversely, reduces the size of integrated circuits and sensors by reducing the circuit layout of the connection part. Now I can do it.
第1図(a)、 (b)は本発明の第1の実施例を施
した配線の接続部の平面図と断面図、第2図(a)、
(b)は第1の実施例の配線の接続方法を示す工程断
面図、第3図(a)、 (b)は本発明の第2の実施
例を施した配線の接続部を示す平面図と断面図、第4図
(a)、 (b)は従来の配線の接続部を示す平面図
と断面図である。
1、l’l”・・・第1の配線、2・・・第2の配線、
3・・・層間絶縁層、4・・・基板、6・・・凹部、
10・・・溝。FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view of a connection portion of wiring according to the first embodiment of the present invention, and FIG. 2(a),
(b) is a process sectional view showing the wiring connection method of the first embodiment, and FIGS. 3(a) and 3(b) are plan views showing the wiring connection part according to the second embodiment of the present invention. FIGS. 4(a) and 4(b) are a plan view and a sectional view showing a conventional wiring connection. 1, l'l"...first wiring, 2...second wiring,
3... Interlayer insulating layer, 4... Substrate, 6... Recessed part,
10...Groove.
Claims (3)
に、複数の小孔もしくは凹凸を形成した接続部を作り、
前記接続部に第2の配線の一部を重ねるように形成し、
前記第1の配線と前記第2の配線を電気的に接続する配
線の接続方法。(1) Creating a connection part with a plurality of small holes or irregularities formed on the first wiring made of superconducting material formed on the substrate,
forming a part of the second wiring so as to overlap the connection part;
A wiring connection method for electrically connecting the first wiring and the second wiring.
薄膜をマスクに超電導材料をエッチングし、前記第1の
配線に小孔もしくは凹凸を形成することを特徴とする請
求項1記載の配線の接続方法。(2) A thin film having a small hole is formed on the first wiring, and a superconducting material is etched using the thin film as a mask to form a small hole or unevenness in the first wiring. How to connect the wiring described.
の臨界電流より小さい超電導材料による第1の配線を用
いることを特徴とする請求項1記載の配線の接続方法。(3) The wiring connection method according to claim 1, characterized in that the first wiring is made of a superconducting material whose critical current in the direction perpendicular to the substrate surface is smaller than the critical current in the direction parallel to the substrate surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63173311A JPH0223674A (en) | 1988-07-12 | 1988-07-12 | Connection of wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63173311A JPH0223674A (en) | 1988-07-12 | 1988-07-12 | Connection of wiring |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0223674A true JPH0223674A (en) | 1990-01-25 |
Family
ID=15958094
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63173311A Pending JPH0223674A (en) | 1988-07-12 | 1988-07-12 | Connection of wiring |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0223674A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5672569A (en) * | 1990-10-31 | 1997-09-30 | Sumitomo Electric Industries, Ltd. | Process for fabricating a superconducting circuit |
DE112011102024T5 (en) | 2010-06-15 | 2013-06-06 | Denki Kagaku Kogyo Kabushiki Kaisha | masking tape |
-
1988
- 1988-07-12 JP JP63173311A patent/JPH0223674A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5672569A (en) * | 1990-10-31 | 1997-09-30 | Sumitomo Electric Industries, Ltd. | Process for fabricating a superconducting circuit |
DE112011102024T5 (en) | 2010-06-15 | 2013-06-06 | Denki Kagaku Kogyo Kabushiki Kaisha | masking tape |
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