JPH0221149B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to inductances used as components of Josephson integrated circuits.

Interferometers, a type of Josephson junction device, are used as logic and storage devices. An interferomitter consists of two or more Josephson junctions and an inductance connecting them. Logic elements and memory elements operate by controlling the current flowing through the junction by flowing a control current into this inductance or by coupling a magnetic field excited by a control current placed nearby to this inductance.
In order for the device to work in this case, the excited magnetic flux Φ must be of the order of the flux quantum Φ ₀ .
Since magnetic flux is expressed as the product of current and inductance L, the following relational expression must hold.

Since the typical current value in a Weber Josephson integrated circuit is 200 _μA , the value ^of L must be approximately 10 PH.

L~Φ ₀ /I~10 ^-11 Heri=10PH In Josephson integrated circuits, the inductance is normally determined by placing an insulator layer with a thickness of t on the superconductor layer that constitutes the ground plane, and on top of this an insulator layer with a width of W and a length of It is composed of a superconductor arrangement of 1.5 cm. At this time, L can be approximated as a function of t, W, and l as follows.

L=μ ₀ t/wl μ ₀ =1.26×10 ⁻⁶ H/m As a numerical example, when t=0.2 μm, w=2.5 μm, and l=100 μm are substituted, L=10 pH. In this case, the area occupied by the inductance is wl = 250 (μm) ² . In order to increase the density of the circuit, it is necessary to reduce the area occupied by the inductance.

Conventionally, in order to reduce the area occupied by the inductance, the thickness of the insulator layer has been equivalently increased using one of the following two methods. The first means is as shown in FIG.
A flat ground plane 1 made of superconductor provided above
A first insulating layer 12 is uniformly formed on the first insulating layer 1, then a second insulating layer 13 is locally formed, and a superconducting layer 14 is disposed on top of this. Further, the second means includes a substrate 24 as shown in FIG.
A part of the flat ground plane 21 made of superconductor provided above is removed by etching,
After exposing the surface of the substrate 24, the insulating layer 22 is
is formed uniformly, and a superconductor layer 23 is disposed on an insulating layer covering the exposed portion of the substrate.

However, according to the first means, the second insulating layer 1
There was a drawback that a step appeared around the convex portion where the superconductor layer 14 was formed, and a wire breakage occurred when the superconductor layer 14 was disposed. Also, according to the second means,
In order to prevent the magnetic field excited by the current flowing through the inductance from concentrating only in the vicinity of the second superconductor layer and from coupling with other inductances, the spacing between the inductances must be sufficiently wide. There were flaws.

SUMMARY OF THE INVENTION An object of the present invention is to provide an inductance for Josephson integrated circuits that overcomes the above-mentioned drawbacks.

According to the present invention, a first superconductor layer is formed on a substrate and constitutes a ground plane of an integrated circuit;
An inductance for a Josephson integrated circuit is obtained, which is characterized by comprising an insulating layer filling a recess formed in a superconducting layer, and a second superconducting layer disposed on the insulating layer.

According to the invention, it is possible to realize an inductance that occupies a small area, and it exhibits a remarkable effect in increasing the density of Josephson integrated circuits.

Hereinafter, this invention will be explained in detail using the drawings.

FIG. 3 is a drawing showing an embodiment of the present invention. In the figure, a recess with a depth t 1 is formed in a first superconductor layer ₃₂ forming a ground plane formed on a substrate 31, and an insulator is placed in this recess with a thickness t ₂ . Layer 33 is filled. A second superconductor layer 34 disposed on 33 forms an inductance. Circuit elements other than the inductance are mounted on the first superconductor layer 32 constituting the ground plane.
It is placed on top of the insulator layer ₃₅ formed thereon.
A Josephson junction formed by an oxide film barrier 37 sandwiched between a portion of the second superconductor layer and the third superconductor layer 36 is an example of a circuit element. In order to form the superconductor layer 34 on the insulator layers 33 and 35 without disconnection, the _depth of the recess should be selected to be t1 to _t2 - _t3 .

As a specific configuration example, the superconductor layer 32 constituting the ground plane is made of niobium, the insulator layers 33 and 35 are insulator layers with a two-layer structure of niobium oxide and silicon oxide, and the superconductor layers 34 and 36 are mainly made of lead. The alloy layer to be used as a component can be selected.

Now, if t ₃ is 0.2 μm and w = 2.5 μm, t ₂ = 0.8 μm
To achieve this, the depth of the recess should be 0.6 μm. In this case, to obtain L=10PH, it is sufficient to set l=25 μm.

Next, a method of manufacturing the Josephson integrated circuit shown in the above embodiment will be explained with reference to FIG.

First, a niobium layer 42 is deposited on a substrate 41, and then the surface of the niobium layer is oxidized to form a niobium oxide film 43. On top of this, a niobium layer 42 and a niobium oxide layer 4
A mask material layer 44 serving as a mask for the etching step 3 is formed, and openings are provided in the regions where the recesses are to be formed using photoresist technology. ZnO or photoresist is used as the mask material.
(FIG. 4a) Next, using the mask material layer 44 as a mask, the niobium oxide layer 43 and the niobium layer 42 are removed by an anisotropic etching method, for example, an ion etching method to form a recessed portion. (FIG. 4b) At this time, the mask material layer 44 is also etched, so that the mask material layer remains when the recesses of the required depth are formed.
It is necessary to choose the initial layer thickness. The exposed surface of the niobium layer is then oxidized to form a niobium oxide layer 45, and then an insulator layer 46 is deposited by vapor deposition or sputtering. (Fig. 4c) If the mask material layer 44 is dissolved by an appropriate method,
A flat surface appears, as seen in Figure 4d. An inductance is formed by depositing a further insulator layer, for example a silicon mooxide layer 47, and then a second superconductor layer 48, for example a lead alloy metal. A Josephson integrated circuit is then obtained by forming a Josephson junction using a conventional method.

As explained above, the inductance for Josephson integrated circuits obtained by the present invention is formed on the insulator layer filled in the recess of the ground plane, so that it is possible to disconnect an element with a large inductance per unit length. It has the advantage that it can be formed without fear of damage, and its effects are great. Note that the selection of the superconductor, insulator, and mask material exemplified in the description of the above embodiments does not impose any limitations on the present invention. It goes without saying that the transformer using the inductance of the present invention as a primary or secondary coil can also be widely used in Josephson integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a first example of an inductance structure used in a conventional Josephson integrated circuit. FIG. 2 is a sectional view showing a second example of an inductance structure used in a conventional Josephson integrated circuit. In the figure, 11 and 21 are ground planes, 12 and 1
3 and 22 are insulator layers, 14 and 23 are superconductor layers,
15 and 24 indicate substrates. FIG. 3 is a diagram showing an embodiment of an inductance according to the present invention. FIGS. 4a, b, c, and d are diagrams for explaining a manufacturing method according to an embodiment of the present invention, and show cross sections of the circuit in main steps. In the figure, 31 and 41 are the substrates, 32 is the first superconductor layer constituting the ground plane, and 33, 35, 4
6 and 47 are insulator layers, 34 is a second superconductor layer,
36 is a third superconductor layer, 37 is an oxide film barrier,
42 is a niobium layer, 43 and 45 are niobium oxide layers, 4
4 represents a mask material layer, and 48 represents a superconductor layer.

Claims (1)

[Claims] 1. A first superconductor layer formed on a substrate and constituting a ground plane of an integrated circuit, an insulator layer filling a recess formed in this first superconductor layer, and an insulator layer disposed on this insulator layer. An inductance for an integrated circuit comprising a second superconductor layer.