JPH0291920A - Method of making minimum connection window of semiconductor device - Google Patents

Method of making minimum connection window of semiconductor device

Info

Publication number
JPH0291920A
JPH0291920A JP1124661A JP12466189A JPH0291920A JP H0291920 A JPH0291920 A JP H0291920A JP 1124661 A JP1124661 A JP 1124661A JP 12466189 A JP12466189 A JP 12466189A JP H0291920 A JPH0291920 A JP H0291920A
Authority
JP
Japan
Prior art keywords
connection window
width
minimum
mask pattern
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1124661A
Other languages
Japanese (ja)
Inventor
Han-Su Park
パーク　ハン―ス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH0291920A publication Critical patent/JPH0291920A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G03F7/2014—Contact or film exposure of light sensitive plates such as lithographic plates or circuit boards, e.g. in a vacuum frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE: To strengthen the resolving power by forming a connecting window using a rectangular mask pattern for minimum connecting window in lithographic step. CONSTITUTION: After bonding a photoresist 1 onto a substrate 2, a mask pattern forming a connecting window is formed in rectangular form of one side W3 wider than the marginal value W1 of the minimum resolving width while the other side W2 narrower than the marginal value W1. When the photoresist 1 in the connecting window position in such a state is developed, the proximity effect wherein the side W3 wider than the marginal W1 promotes the developement of the other side W2 narrower than the marginal value W1 is gained, thereby enabling the connecting window in the W2 narrower than the marginal value W1 of the minimum resolving width to be formed.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体製造工程の内のリソグラフ工程に関し、
特に、既存の最小の接続窓の限界値より小さい接続窓を
形成することができる「近接効果（Ｐｒｏｘｉｍｉｔｙ
　Ｅｆｆｅｃｔ）　Ｊを用いた半導体装置の最小接続窓
の形成方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a lithography process in a semiconductor manufacturing process,
In particular, the ``proximity effect'' can form a connection window smaller than the limit value of the existing minimum connection window.
This invention relates to a method for forming a minimum connection window in a semiconductor device using J.Effect).

［従来の技術］ リソグラフ工程を通して基板の最上層に接続窓を形成し
ようとする場合、正方形の接続窓のマス円形に形成され
る。[Prior Art] When a connection window is formed on the top layer of a substrate through a lithography process, a square connection window is formed in a circular shape.

〔発明が解決しようとする謀８〕 この時、最小接続窓の大きさは、例えばフォトレジスト
を用いる場合、そのエツチングの最小線幅によって決定
されるので、最小接続窓の大きさには制限がある。即ち
、第１図（Ａ）〜第１図（Ｃ）に示されているように、
フォトレジスト１の解像力の限界値に従って最小接続窓
を形成することができるマスクパターンの幅をＷｌとす
ると、ｔＪ２図（Ａ）〜！Ｊ２図（Ｃ）に示されている
ように、フォトレジスト１の解像力の限界値以下の幅Ｗ
２を有する接続窓のマスクパターンでは目的とする接続
窓を形成することができない。即ち、接続窓が基板（導
電層又は絶縁層）２の表面まで形成されない。[Plot 8] At this time, the size of the minimum connection window is determined by the minimum line width of etching when using photoresist, so there is no limit to the size of the minimum connection window. be. That is, as shown in FIG. 1(A) to FIG. 1(C),
If the width of the mask pattern that can form the minimum connection window according to the limit value of the resolution of the photoresist 1 is Wl, then tJ2 (A)~! As shown in Figure J2 (C), the width W is less than the limit value of the resolution of photoresist 1.
The mask pattern of the connection window having the number 2 cannot form the intended connection window. That is, the connection window is not formed up to the surface of the substrate (conductive layer or insulating layer) 2.

本発明はこのような問題点を解決するためになされたも
のであり、その目的は、既存の最小の接続窓の限界値よ
り小さい接続窓の形成が可能な、［課題を解決するため
の手段］ 上記目的を達成するため、本発明の第１の形態によれば
、半導体製造工程の内のリングラフ工程において最小接
続窓用に長方形のマスクパターンを用いて接続窓を形成
し、もって解像力を改良する半導体装置の最小接続窓の
形成方法が提（Ｒされ、そして、本発明の！＠２の形態
によれば、半導体製造工程の内のリソグラフ工程におい
て最小接続窓用に十字形のマスクパターンを用いて接続
窓を形成し、もって解像力を改良する半導体装置の最小
接続窓の形成方法が提供される。The present invention has been made to solve these problems, and its purpose is to provide a means for solving the problems, which enables the formation of a connection window smaller than the limit value of the existing minimum connection window. ] In order to achieve the above object, according to a first aspect of the present invention, a rectangular mask pattern is used to form a connection window for a minimum connection window in a ring graph process in a semiconductor manufacturing process, thereby improving resolution. A method for forming the minimum connection window in a semiconductor device is proposed, and according to the second aspect of the present invention, a cross-shaped mask pattern is formed for the minimum connection window in the lithography process of the semiconductor manufacturing process. A method of forming a minimum connection window in a semiconductor device is provided that uses the present invention to form a connection window, thereby improving resolution.

［実　施　例］ 以下、添付図面を参照して本発明の実施例を詳細に説明
する。[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

第３図に示されているように、基板２（ウェーハ最上層
の導電層又は絶縁層）に７オトレジスト１を付着させた
後、接続窓形成用のマスクパターンを、−辺Ｗ３は最小
解像幅の限界値Ｗ１より大きく、他辺Ｗ２は前記最小解
像幅の限界値Ｗ１より小さい長方形に形成する。この状
態で接続窓部位のフォトレジスト１を現像すると、最小
解像幅の限界値Ｗ１より大きい辺Ｗ３が最小解像幅の限
界値Ｗ１より小さい辺Ｗ２の現像を助けるところの近接
効果が発生し、最小解像幅の限界値ｗ１より小さい幅Ｗ
２を有する接続窓の形成が可能になる。また、この際、
辺Ｗ３の艮の変化に応じて接続窓の小さい幅Ｗ２の大き
さが変化するので、辺Ｗ３を調節することで接続窓の大
きさの調整が可能になる。As shown in FIG. 3, after attaching the 7 photoresist 1 to the substrate 2 (the uppermost conductive layer or insulating layer of the wafer), a mask pattern for forming a connection window is formed. It is formed into a rectangle whose width is larger than the limit value W1 and whose other side W2 is smaller than the minimum resolution width limit W1. When the photoresist 1 in the connection window area is developed in this state, a proximity effect occurs in which the side W3 larger than the minimum resolution width limit W1 helps the side W2 smaller than the minimum resolution width limit W1. , width W smaller than the minimum resolution width limit value w1
This makes it possible to form a connection window with 2. Also, at this time,
Since the size of the small width W2 of the connection window changes according to the change in the width of the side W3, the size of the connection window can be adjusted by adjusting the side W3.

上記長方形の接続窓マスクを利用する場合よりも更に小
さい接続窓を形成する二とが可能な方法が第４図に示さ
れている。これは前記最小解像幅の限界値Ｗ１より狭い
幅Ｗ５の十字形の接続窓マスクを用いたものであり、最
小解像幅の限界値Ｗ１より長い辺Ｗ４が幅Ｗ５の解像力
に影響を与え、通常の最小接続窓の大きさより小さい接
続窓の形成が可能になる。特に、この場合、基板２に対
す［発明の効果〕 以上のように、本発明によれば、半導体装置の接続窓の
形成部位が最小化され得、これにより、高密度半導体装
置のチップ面積を減少させることが可能になる。Two possible ways to create smaller connection windows than using the rectangular connection window mask described above are shown in FIG. This uses a cross-shaped connection window mask with a width W5 narrower than the minimum resolution width limit W1, and the side W4, which is longer than the minimum resolution width limit W1, affects the resolution of the width W5. , it is possible to form a connection window smaller than the normal minimum connection window size. Particularly, in this case, [Effects of the Invention] on the substrate 2 As described above, according to the present invention, the area where the connection window of the semiconductor device is formed can be minimized, thereby reducing the chip area of the high-density semiconductor device. It becomes possible to reduce the

【図面の簡単な説明】[Brief explanation of drawings]

第１図、（Ａ）は従来のリソグラフ工程の限界値幅Ｗ１
を有する接続窓の平面図、 第１図（Ｂ）は第１図（Ａ）の■−■′線に沿う断面図
、 第１図（Ｃ）は第１図（Ａ）の１−１’線に沿う断ｉＩ
ｊ図、 第２図（Ａ）はリソグラフ工程の限界値幅Ｗ１未満の幅
Ｗ２を有する接続窓の平面図、ｆｆ１２図（Ｂ）は第２
図（Ａ）の■−■′線に沿う断面図、 第２図（Ｃ）は第２図（Ａ）の１−１’線に沿う断面図
、 第３図（Ａ）は本発明の第１の形態に係る実施例におけ
る接続窓の平面図、 第３図（Ｂ）は第３図（Ａ）のｎ−ｎ’線に沿う断面図
、 第３図（Ｃ）は第３図（Ａ）の１−１’線に沿う断面図
、 第４図（Ａ）は本発明の第２の形態に係る実施例におけ
る接続窓の平面図、 第４図（Ｂ）は第４図（Ａ）の■−■′線に沿う断面図
、および 第４図（Ｃ）は第４図（Ａ）の１−１′線に沿う断面図
である。 １・・・フォトレジスト ２・・・基板（ウェーハ最上層の導電層又は絶縁層）Ｆ
ＩＧ、１ ＦＩＧ−２ （Ａ） （Ｂ） （Ａ） （Ｂ） ロー■ 「−■ ＦＩＧ、３ ＦＩＧ、４ （Ａ） 「■ ＣＢ）Figure 1 (A) shows the limit value width W1 of the conventional lithography process.
1(B) is a sectional view taken along the line ■-■' in FIG. 1(A), and FIG. 1(C) is a sectional view taken along the line 1-1' in FIG. 1(A). Cut along the line
Fig. j, Fig. 2 (A) is a plan view of a connection window having a width W2 less than the limit value width W1 of the lithography process, and Fig.
2(C) is a sectional view taken along line 1-1' of FIG. 2(A); FIG. 3(A) is a sectional view taken along line 1-1' of FIG. FIG. 3(B) is a sectional view taken along line nn' in FIG. 3(A), and FIG. ), FIG. 4(A) is a plan view of a connection window in an embodiment according to the second embodiment of the present invention, and FIG. 4(B) is a cross-sectional view of FIG. 4(A). FIG. 4(C) is a sectional view taken along the line 1--1' of FIG. 4(A). 1... Photoresist 2... Substrate (wafer top conductive layer or insulating layer) F
IG, 1 FIG-2 (A) (B) (A) (B) Low ■ “-■ FIG, 3 FIG, 4 (A) “■ CB)

Claims (6)

【特許請求の範囲】[Claims] （１）半導体製造工程の内のリソグラフ工程において最
小接続窓用に長方形のマスクパターンを用いて接続窓を
形成し、もって解像力を改良する半導体装置の最小接続
窓の形成方法。(1) A method for forming a minimum connection window in a semiconductor device, which improves resolution by forming a connection window using a rectangular mask pattern for the minimum connection window in a lithography process in a semiconductor manufacturing process. （２）最小接続窓用のマスクパターンの狭い方の幅は解
像力の限界値幅より小さく、最小接続窓用のマスクパタ
ーンの広い方の幅は解像力の限界値幅より大きい請求項
１記載の半導体装置の最小接続窓の形成方法。(2) The semiconductor device according to claim 1, wherein the width of the narrower side of the mask pattern for the minimum connection window is smaller than the limit value width of resolution, and the width of the wider side of the mask pattern for the minimum connection window is larger than the limit value width of resolution. How to form a minimum connection window. （３）接続窓用のマスクパターンの広い方の幅の長さを
調節して接続窓の大きさを調節する請求項２記載の半導
体装置の最小接続窓の形成方法。(3) The method for forming a minimum connection window in a semiconductor device according to claim 2, wherein the size of the connection window is adjusted by adjusting the length of the wider width of the mask pattern for the connection window. （４）半導体製造工程の内のリソグラフ工程において最
小接続窓用に十字形のマスクパターンを用いて接続窓を
形成し、もって解像力を改良する半導体装置の最小接続
窓の形成方法。(4) A method for forming a minimum connection window in a semiconductor device, which improves resolution by forming a connection window using a cross-shaped mask pattern for the minimum connection window in a lithography process in a semiconductor manufacturing process. （５）最小接続窓用のマスクパターンの狭い方の幅は解
像力の限界値幅より小さく、最小接続窓用のマスクパタ
ーンの広い方の幅は解像力の限界値幅より大きい請求項
４記載の半導体装置の最小接続窓の形成方法。(5) The semiconductor device according to claim 4, wherein the narrower width of the mask pattern for the minimum connection window is smaller than the resolution threshold width, and the wider width of the minimum connection window mask pattern is larger than the resolution threshold width. How to form a minimum connection window. （６）接続窓用のマスクパターンの広い方の幅の長さを
調節して接続窓の大きさを調節する請求項５記載の半導
体装置の最小接続窓の形成方法。(6) The method for forming a minimum connection window in a semiconductor device according to claim 5, wherein the size of the connection window is adjusted by adjusting the length of the wider width of the mask pattern for the connection window.
JP1124661A 1988-09-16 1989-05-19 Method of making minimum connection window of semiconductor device Pending JPH0291920A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019880012029A KR920004910B1 (en) 1988-09-16 1988-09-16 Minimum contact hole forming method of semiconductor device
KR88-12029 1988-09-16

Publications (1)

Publication Number Publication Date
JPH0291920A true JPH0291920A (en) 1990-03-30

Family

ID=19277820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1124661A Pending JPH0291920A (en) 1988-09-16 1989-05-19 Method of making minimum connection window of semiconductor device

Country Status (5)

Country Link
JP (1) JPH0291920A (en)
KR (1) KR920004910B1 (en)
DE (1) DE3916329A1 (en)
FR (1) FR2636775A1 (en)
GB (1) GB2222893A (en)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2755399A1 (en) * 1976-12-14 1978-06-22 Ernst Prof Dipl Phys Froeschle Electron beam irradiation system for structures on substrates - irradiates structure surrounds to compensate for electron scattering
US4099062A (en) * 1976-12-27 1978-07-04 International Business Machines Corporation Electron beam lithography process
EP0043863B1 (en) * 1980-07-10 1984-05-16 International Business Machines Corporation Process for compensating the proximity effect in electron beam projection devices
JPS58102939A (en) * 1981-12-15 1983-06-18 Canon Inc Mask for mask aligner and mask aligner
JPS5948924A (en) * 1982-09-14 1984-03-21 Nec Corp Positioning mark for electron beam exposure
JPS60210839A (en) * 1984-03-05 1985-10-23 Fujitsu Ltd Reticle detection method
JPS62198861A (en) * 1986-02-27 1987-09-02 Hoya Corp Reticle
JPS62264052A (en) * 1986-05-10 1987-11-17 Sony Corp Mask for exposure

Also Published As

Publication number Publication date
GB8911307D0 (en) 1989-07-05
KR920004910B1 (en) 1992-06-22
KR900005553A (en) 1990-04-14
GB2222893A (en) 1990-03-21
DE3916329A1 (en) 1990-03-22
FR2636775A1 (en) 1990-03-23

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