JPS6254923A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability of metal wirings on an insulating film by selectively etching the insulating film or a wiring layer to the midway, the ion implanting, and selectively reetching to alleviate the influence at etching time on a semiconductor substrate. CONSTITUTION:An insulating film 2 is formed on a semiconductor substrate 1, and to obtain the width A and the interval B of desired patterns, photoresist patterns 3, 4 are formed by existing photoetching technique. Then, the initial etching is executed, the all layer to be etched is not removed, the etching is stopped, and the remaining layer to be etched is ion implanted in the state that the photoresist remains coated. Then, the remaining ion implanted layer to be etched is completely removed by etching.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to improving the selective etching of an insulating film or wiring layer of a semiconductor device. This relates to improvement, expansion of manufacturing limits between each process, and process simplification.

[Conventional technology]

The conventional manufacturing method for this type of semiconductor device is a dry process using plasma or the like to form a single or multiple insulating pA or polycrystalline silicon wiring layer formed on a semiconductor substrate into a desired pattern. Complex etching was performed by combining etching and wet etching using hydrofluoric acid to form a desired pattern.

Next, a method for obtaining a desired pattern using conventional techniques will be explained with reference to FIGS. 2 and 3.

As shown in FIG. 2, an insulating film 2 is provided on a semiconductor substrate 1, and a photoresist pattern 3.4 is formed using existing photolithography techniques to obtain a desired pattern width A and spacing B. In the prior art, etching is performed from this state shown in FIG. 2 by dry etching using plasma or wet etching using hydrofluoric acid or the like to obtain a desired pattern once or by a combination of etching techniques several times. FIG. 3 shows the etching completed state at that time.

The dimensional state at this time is as follows.

First, with respect to the desired pattern A, the actual dimension near the photoresist is X, and the actual dimension near the semiconductor substrate is Y (A>Y>X). Also, for the desired pattern B, B+2T near the photoresist and D(B(I
)(B+2T). In this way, a large error occurs from the initial desired dimensions, which has a large impact on the semiconductor device and causes various problems (for example, the shadow # on the next process, etc.)
comes out. If the width in the lateral direction is as large as T, it is a big problem, and it also affects the design of semiconductor devices. In severe cases, it may reach X20.

[Problem that the invention seeks to solve]

As mentioned above, conventional semiconductor device manufacturing methods inevitably lead to overetching.
There is a problem in that desired pattern dimensions cannot be obtained with high precision, and this has to be taken into consideration at the design stage of semiconductor devices.

In addition, the subsequent dry etching process using plasma or the like results in overetching, which can cause damage to the semiconductor substrate, etc., and seriously affect the characteristics and reliability of semiconductor devices.

The present invention eliminates the above-mentioned conventional drawbacks, reduces the shadow 4 on the semiconductor substrate in the semiconductor device manufacturing process, forms a desired pattern with better dimensional accuracy, and obtains a stable and highly reliable semiconductor device. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes the step of selectively etching a single or multiple insulating film and wiring Ja formed on a semiconductor substrate using photolithography. The method includes a first etching step in which the insulating film or the wiring layer is selectively etched halfway, a next step in which ions are implanted, and a second etching step in which selective etching is performed again.

To explain in more detail, after forming a desired pattern on the photoresist by photolithography, first some selective etching is performed, and then the ion implantation energy, implantation amount, etc. are determined by considering the properties of the gas and liquid used in the final selective etching. The implanted impurities are determined and the ions are implanted, so that during the final selective etching, the ion-implanted layer is etched more quickly than the non-ion-implanted layer.

According to the structure of the present invention, when the same etching gas and the same etching solution are used in the layer to be etched, the lateral spread, which is a problem during etching, is reduced. That is, the dimension d in FIG. 1 becomes d2B, which is more accurate than the dimension in FIG. 3. Similarly, the dimension y in FIG. 1 becomes y:A, and the precision of the dimension Y machining in FIG. 3 also improves.

Furthermore, in the present invention, which performs two etchings and ion implantations using one photolithography technique, since the layer to be etched is etched to some extent in the first etching, the second etching improves the time accuracy and saves time from wasted etching. You don't have to put it on.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram for explaining an embodiment of the present invention, and is a schematic cross-sectional view of the embodiment.

In this embodiment, selective etching of an insulating film of a semiconductor device will be explained.

First, as shown in FIG. 2, an insulating film 2 is provided on a semiconductor substrate 1, and in order to obtain a desired pattern width A and a machining interval B, an existing copy Xi1! Photoresist patterns 3 and 4 are formed using an il engraving technique.

Therefore, from the state shown in Figure 2, first perform the first etching, stop the etching without removing all of the layer to be etched, and with the photoresist still attached to the casing, carry out complete ion implantation into the remaining layer to be etched, and then remove the remaining layer. The ions were implanted into the etched area 8' and completely removed by etching. In this case, the insulating film is etched into the state shown in FIG.

The layer to be etched into which ions have been implanted can be removed in a short period of time because the etching progresses more quickly than the layer into which ions have not been implanted. Therefore, as shown in FIG. 3 in the prior art, the width of the pattern spacing B in the lateral direction was 9 dimensions'r and the size of the finished geometries was 9, but in this embodiment shown in FIG. The spread dimension is t, and the finished dimension is d,
Further, in the conventional example, the pattern width A was X at the top and Y at the bottom, but in this embodiment, it is X at the top and Y at the bottom, greatly improving dimensional accuracy.

After ion implantation, the layer to be etched has a slight etching-like step. This step is very useful because it prevents disconnection of metal wiring, etc., which will be formed on the layer to be etched in a subsequent process.

Furthermore, the total etching time is shortened and the etching time can be easily controlled, so that the influence on the semiconductor substrate 1 during etching is reduced.

[Effects of the Invention] As explained above, according to the present invention, the influence of etching on a semiconductor substrate is reduced, the reliability of metal wiring on an insulating film is improved, and the reliability of the entire semiconductor device is improved overall. The effects such as improvement and stable yield are very large.

In addition, in ion implantation, energy and implantation amount are controlled,
It is also easy to increase the accuracy of a desired pattern. Therefore, it is thought that the present invention can be applied to all manufacturing processes of all semiconductor devices.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining one embodiment of the present invention, and is a schematic cross-sectional view of the etching formed in the embodiment, and Fig. 2 shows the state before etching in the conventional example and one embodiment of the present invention. The sectional view, FIG. 3, is the ninth diagram for explaining an example of the conventional example, and is a schematic sectional view formed by the conventional example. 1... Semiconductor substrate, 2... Insulating film (layer to be etched), 3.4... Photoresist,
5... Insulating film step. Agent Patent Attorney Susumu Uchihara 2nd V Article 3 ■ Procedural amendment (,4)

Claims (1)

[Claims] In a method for manufacturing a semiconductor device including a step of selectively etching a single or multiple insulating films or wiring layers formed on a semiconductor substrate using photolithography, the insulating film or the wiring layer is partially selected. 1. A method of manufacturing a semiconductor device, comprising a first etching step of etching, a next step of ion implantation, and a second etching step of reselective etching.