JPS62214622A - Formation of recession in semiconductor wafer - Google Patents
Formation of recession in semiconductor waferInfo
- Publication number
- JPS62214622A JPS62214622A JP5746186A JP5746186A JPS62214622A JP S62214622 A JPS62214622 A JP S62214622A JP 5746186 A JP5746186 A JP 5746186A JP 5746186 A JP5746186 A JP 5746186A JP S62214622 A JPS62214622 A JP S62214622A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- thin film
- substrate
- layer
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 238000005530 etching Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000001514 detection method Methods 0.000 claims description 6
- 238000012544 monitoring process Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 238000001947 vapour-phase growth Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241000238557 Decapoda Species 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005474 detonation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造プロセスにおいて半導体ウ
ェーハに所要深さの凹部を正確基こ形成する方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for accurately forming recesses of a required depth in a semiconductor wafer in a semiconductor device manufacturing process.
近年、半導体集積回路装置の製造においては、微細加工
等の各種の技術の進展に伴い、その集積度等の向上も著
しい。特に、半導体装置上の必要性、マたは集積度の向
上などのために、シリコン(Si)基板に微細凹部を形
成する技術も進展し、各種の実験も行なわれている。In recent years, in the manufacture of semiconductor integrated circuit devices, with the progress of various technologies such as microfabrication, the degree of integration has been significantly improved. In particular, the technology for forming fine recesses in silicon (Si) substrates has been developed to meet the needs of semiconductor devices and to improve the degree of integration, and various experiments have been conducted.
ところが、従来技術では半導体ウェーハの表面から凹部
を形成するに当って、その深さを正確に所望値番こ止め
る適切な技術はなく深さが不正確になるという問題点が
あった。However, in the prior art, when forming a recess from the surface of a semiconductor wafer, there is no suitable technique for accurately setting the depth to a desired value, and the problem is that the depth becomes inaccurate.
この発明は以上のような問題点を解消するためになされ
tこもので、半導体ウェーハ1c深さが正確に所望値で
ある凹部を形成する方法を提供することを目的としてい
る。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for forming a recessed portion in a semiconductor wafer 1c having an accurately desired depth.
この発明に係る凹部形成方法では、 Si基板上のモニ
タ一部分にStとは異なる物質の薄膜を形成し、その上
を含めてSi基板上に既知の厚さのSt層をエピタキシ
ャル成長させ、まずモニタ一部にエツチングを施して凹
部を形成し、これによって得られたデータにもとづいて
、その他の部分に実用の凹部を正確な確さに形成する。In the recess forming method according to the present invention, a thin film of a substance different from St is formed on a portion of the monitor on a Si substrate, and an St layer of a known thickness is epitaxially grown on the Si substrate including the thin film on the monitor. The recesses are formed by etching the parts, and based on the data obtained, practical recesses are formed in other parts with precision.
この発明では、上述のようにモニタ一部にエツチングを
施して凹部を形成する際に、上記Siとは異なる物質の
薄膜にエツチングが達するまでの時間とエピタキシャル
成長シリコン層の既知の厚さとからエッチング速度を知
り、これを用いて、その他の部分に実用の凹部を形成す
れば正確な深さの凹部が得られる。In this invention, when etching a part of the monitor to form a recess as described above, the etching rate is determined based on the time it takes for the etching to reach the thin film of a substance different from Si and the known thickness of the epitaxially grown silicon layer. If you know this and use this to form practical recesses in other parts, you can obtain recesses with accurate depth.
第1図(at〜(clはこの発明の一実施例方法の主要
工程段階における状態を示す断面図で、まず、第1図(
atに示すように、S五基板(1)の上のモニター専用
部位、ダイシングライン部等にエツチング終点検出用の
薄膜層(2)(質量分析計や分光分析計等の終点検出機
を用いた特番こ81基板だけの場合とは異なる情報が得
られるような材料層)を形成する。FIG. 1 (at to (cl) is a cross-sectional view showing the state at the main process steps of a method according to an embodiment of the present invention.
As shown in FIG. A material layer is formed that allows different information to be obtained from the case of only the special number 81 substrate.
これは薄膜炸裂技術やホトエツチング技術を用いて行い
得るものである。その後に、Si気相成長技術を用いて
St基板【1)上に、必要厚さのSiエピタキシギル成
長層(3)(単結晶Si層)を形成する。この時に薄膜
層(2)上には多結晶St層となってもかまわない。す
なわち、単結晶St層と多結晶Si層の成長速度比やエ
ツチング速度比を調べておけば問題にならないであろう
。This can be done using thin film detonation techniques or photoetching techniques. Thereafter, a Si epitaxial growth layer (3) (single-crystal Si layer) of a required thickness is formed on the St substrate (1) using Si vapor phase growth technology. At this time, a polycrystalline St layer may be formed on the thin film layer (2). That is, if the growth rate ratio and etching rate ratio of the single crystal St layer and the polycrystalline Si layer are investigated, there will be no problem.
次に、第1図fblに示すように、St基板(1)に直
接対向する部分にはエッチング用開孔(4)を、薄膜層
(2)上の部分にはモニターエツチング用開孔(5)を
存するエツチングマスク(6)8形成する。Next, as shown in FIG. ) is formed as an etching mask (6) 8.
次に、第1図telに示すように、リアクティブイオン
エツチング等にてSi気相成長層[3)の異方性エツチ
ングを行う。この時に質量分析計や分光分析計等の終点
検出機を用いているならば、把握された異方性エツチン
グ条件の下では、Sl気相成長層(3)のエッチングが
進んで薄膜層(2)まで到達した場合には、エッチング
時の信号強度が変化してエツチングの終点が判る様にな
るので、このエツチング時間を単位終点検出時間として
、Siエビ成長層(3)の厚さ程度の深さの凹部の形成
と評価とに用い得ることが出来る。Next, as shown in FIG. 1, the Si vapor phase growth layer [3] is anisotropically etched by reactive ion etching or the like. If an end point detector such as a mass spectrometer or spectrometer is used at this time, under the determined anisotropic etching conditions, the etching of the Sl vapor phase growth layer (3) will progress and the thin film layer (2 ), the signal intensity during etching changes and the end point of etching can be determined, so this etching time is taken as the unit end point detection time and the etching depth is approximately the same as the thickness of the Si shrimp growth layer (3). It can be used for forming and evaluating concave portions.
従って、Siエピタキシギル成長層(3)の厚さの数倍
程度の深い凹部をSt基板(1) +こ形成する時には
、この単位終点検出時間を用いて、連続的に数倍程度の
時間エッチング処理すれば良いこと−こなる。Therefore, when forming a deep recess several times the thickness of the Si epitaxial growth layer (3) on the St substrate (1), this unit end point detection time is used to continuously etch for several times the thickness. All you have to do is deal with it.
この様な凹部形成時では、異方性エツチングの先行チェ
ックと本番処理を同一サイクル内で行うことになり、そ
れだけエツチングサイクル間のバラツキ要因を減らせる
こと醤こなり、又同時に&気相成長層の厚さ及びエツチ
ング時間により、凹部の深さをもモニターリングしてい
ることになると言える。When forming such a recess, the preliminary check of anisotropic etching and the actual processing are performed in the same cycle, which reduces the factors of variation between etching cycles. It can be said that the depth of the recess is also monitored based on the thickness and etching time.
また、上記実施例では凹部形成対象基板内1こモニター
用薄膜層を設けたが、Si基板全面にエツチング終点検
出用モニター用の薄膜層を形成した後。Further, in the above embodiment, a thin film layer for monitoring was provided in one part of the substrate on which the recess was to be formed, but after a thin film layer for monitoring for etching end point detection was formed on the entire surface of the Si substrate.
必要厚さにSi気相成長層(必要に応じて溶融再結晶化
Si層としたものも可能である)を形成して、パターニ
ング化されているエツチングマスクを設けた専用モニタ
ーを用い、凹部形成対象基板1c対する本番エツチング
サイクル内で同時処理する様にすれは、この発明の効果
を太き(すること(こなるであろう。A Si vapor phase growth layer (a fused recrystallized Si layer is also possible if necessary) is formed to the required thickness, and a recess is formed using a dedicated monitor equipped with a patterned etching mask. The effects of the present invention will be greatly enhanced if the target substrate 1c is processed simultaneously within the actual etching cycle.
従って、Si基板上・こバターニングされた薄膜層(エ
ツチング終点検出用になりうるものンを形成して、必要
厚さにSi気相成長を行い、溶融再結晶化Si層とした
8i基板に、凹部を形成する場合にも有効であり、特に
、エツチング終点検出領域を出来るだけ広めることが出
来るならば、この発明の効果を太き(することになるで
あろう。Therefore, a thin film layer (which can be used to detect the end point of etching) is formed on the Si substrate, and Si vapor phase growth is performed to the required thickness to form a molten recrystallized Si layer on the 8i substrate. It is also effective when forming a concave portion, and in particular, if the etching end point detection area can be expanded as much as possible, the effect of the present invention will be increased.
以上説明したよう番こ、この発明ではエツチング終点検
出用薄膜層を有するモニタmmつエーノ・を用い、これ
によってその上のStエピタキシャル成長層のエツチン
グの終点を検知し、エツチング速度を知り、これをもと
にして目的とする凹部のエツチング形成を制御するので
正確な深さの凹部か得られる。As explained above, in this invention, a monitor having a thin film layer for detecting the end point of etching is used to detect the end point of etching of the St epitaxial growth layer thereon, to know the etching rate, and to detect the end point of etching of the St epitaxial growth layer thereon. Since etching formation of the desired recess is controlled, recesses with accurate depth can be obtained.
第1図(al、第1図(bl及び第1図fclはこの発
明の一実施例方法の主要工程段階での状態を示す断面図
Cある。
一番こおいて、i)はシリコン基板、(2)はエッチン
グ終点検出用薄膜1i 、 (3)はシリコン・エヒタ
キシャル成長層、 (6)はエソナングマスクである。
rlお、図中同一符号は同一、または相当部分を示す。FIG. 1 (al), FIG. 1 (bl), and FIG. 1 (fcl) are cross-sectional views C showing the state at the main process steps of the method according to an embodiment of the present invention. First, i) is a silicon substrate; (2) is a thin film 1i for detecting the end point of etching, (3) is a silicon epitaxial growth layer, and (6) is an etsonization mask.rlThe same reference numerals in the drawings indicate the same or equivalent parts.
Claims (2)
ル成長させてなる加工対象半導体ウェーハの表面にエッ
チングによつて凹部を形成するに際して、 半導体シリコン基板上にシリコンと異なる物質からなる
エツチング終点検出用薄膜層を形成しその上に上記シリ
コンのエピタキシャル成長層を形成したモニター用ウェ
ーハと上記加工対象半導体ウェーハとに所要パターンの
エッチングを施し、上記モニター用ウエーハにおいてエ
ッチングが上記エッチング終点検出用薄膜層に達するま
での時間からエツチング速度を知り、 このエッチング速度にもとづいて上記加工対象半導体ウ
ェーハに所望深さの凹部を形成することを特徴とする半
導体ウエーハへの凹部形成方法。(1) When forming recesses by etching on the surface of a semiconductor wafer to be processed, which is made by epitaxially growing silicon on a semiconductor silicon substrate, a thin film layer for etching end point detection made of a substance different from silicon is formed on the semiconductor silicon substrate. The monitoring wafer on which the silicon epitaxial growth layer is formed and the semiconductor wafer to be processed are etched in a required pattern, and the time from the time until the etching reaches the etching end point detection thin film layer on the monitoring wafer. A method for forming a recess in a semiconductor wafer, comprising knowing an etching rate and forming a recess of a desired depth in the semiconductor wafer to be processed based on the etching rate.
一部に形成することを特徴とする特許請求の範囲第1項
記載の半導体ウエーハへの凹部形成方法。(2) A method for forming recesses in a semiconductor wafer according to claim 1, characterized in that the monitor wafer is formed in a part of the semiconductor wafer to be processed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5746186A JPS62214622A (en) | 1986-03-14 | 1986-03-14 | Formation of recession in semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5746186A JPS62214622A (en) | 1986-03-14 | 1986-03-14 | Formation of recession in semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62214622A true JPS62214622A (en) | 1987-09-21 |
Family
ID=13056314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5746186A Pending JPS62214622A (en) | 1986-03-14 | 1986-03-14 | Formation of recession in semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62214622A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015122419A (en) * | 2013-12-24 | 2015-07-02 | 三菱電機株式会社 | Semiconductor laser element manufacturing method |
-
1986
- 1986-03-14 JP JP5746186A patent/JPS62214622A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015122419A (en) * | 2013-12-24 | 2015-07-02 | 三菱電機株式会社 | Semiconductor laser element manufacturing method |
US9184566B2 (en) | 2013-12-24 | 2015-11-10 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor laser element |
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