JPS6221415B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error control system for transmission codes, and includes a bit rate conversion circuit for adding check bits necessary for error control to information bits input in series, converting the bits into serial bits again, and outputting the bits. encoding circuit,
The present invention relates to a decoding circuit that performs the reverse operation.

Conventionally, this type of error control circuit has been incorporated into a transmission information encoding circuit, and has been designed to stop the transmission of information bits when error control check bits are transmitted. For this reason, it has been difficult to convert already generated serial information bits into error control codes for the purpose of improving transmission reliability.

The present invention differs the input and output bit rates by the ratio of (number of information bits)/(number of information bits) + (number of error control bits) (1) (or its inverse), and The present invention provides a serial input/serial output type error control encoding/decoding circuit which enables conversion of already generated serial information bits into error control codes with a simple circuit by aligning the columns.

The present invention has a serial input parallel output shift register, a multiplexer, and an up-down counter circuit, and the output of the shift register is connected to one input of the multiplexer, and the up-down counter circuit is configured to switch and output this input. The output of the circuit is connected to the other input of the multiplexer. The up-down counter circuit operates to count up with a clock pulse synchronized with the input of the shift register and count down with a clock pulse synchronized with the serial pulse output from the multiplexer. Now, when one serial pulse train is input to the shift register, a serial pulse train having a different bit rate from this pulse train can be obtained from the output of the multiplexer. Furthermore, by setting the ratio of the input and output bit rates to the value of equation (1) above, an error control code can be added to the information bit string without including a 0-value continuous interval for error control check bits. It can be easily removed.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the encoding circuit of the present invention. The transmission input signal 1 is input to the serial input parallel output shift register 6, and the parallel output signal 23 is input to the serial input parallel output shift register 6.
get. This output is selected by the multiplexer 7 and connected to the inputs of the multiplexing circuit 14 and the dividing circuit 12. The test signal 27 output from the division circuit 12 is input to the multiplexing circuit 14, and the frame synchronization signal 25 from the frame synchronization signal generation circuit 11 is input to the multiplexing circuit 1.
Enter 4. A multiplexing circuit 14 time-division multiplexes the above three signals to obtain a transmission signal 29, which is waveform-shaped by a flip-flop 16 to obtain a transmission output signal 3. On the other hand, the clock pulse 2 and the control pulse 19 from the control pulse generating circuit 10 are input to the up-down counter circuit 8, and the output multiplexer control signal 22 is input to the multiplexer 7.

The clock pulse 2 is a clock pulse synchronized with the transmission input signal 1, and shifts the serial input parallel output shift register 6 to generate a parallel output signal 23 delayed by one clock from the transmission input signal 1, as shown in FIG. At the same time, as shown in FIG. 6, the up-down counter circuit 8 is caused to count up every time one clock is input. Fifth
In the figure, a indicates the transmission input signal, b indicates the output of the shift register 6 delayed by one to four stages, and c indicates the clock pulse 2. The control pulse 19 is a clock pulse synchronized with the transmission output signal 3 output from the flip-flop 16, and shifts the divider circuit 12, controls the frame synchronization signal generation circuit 11, the multiplexing circuit 14, and the flip-flop 16, and performs up-down. The counter circuit 8 is caused to count down as shown in FIG. In FIG. 6, I indicates a 1-bit input, O indicates a 1-bit output, and N indicates the number of delay stages of the delayed signal.

As shown in FIG. 6, the up-down counter circuit 8 counts up by the number of bits of the transmission input signal 1 input to the serial input parallel output shift register 6, and the parallel output signal 23 is output to the multiplexer 7.
The number of bits selected by and output to the multiplexing circuit 14 is counted down.

The multiplexer control signal 22 of the output of the up-down counter circuit 8 is expressed by the relational expression for the serial input parallel output shift register 6: (number of input bits) - (number of output bits) = (currently accumulated number of bits) . . . Equation (2) indicates the address on the shift register where the first bit of the bit string input bit-serially is stored in the serial input parallel output shift register 6. For this reason, the information signal 26 at the output of the multiplexer 7
The bit string is always arranged in the same order as the transmission input signal 1.

The relationship between the transmission input signal 1 and the transmission output signal 3 is shown in FIGS. 2a and 2b. Transmission input signal 1
The bit rate of the transmission output signal 3 is set lower than the bit rate of the transmission output signal 3 according to the ratio of equation (1) above, so the number of bits in a certain period of time is higher for the transmission output signal 3 than for the transmission input signal 1 according to the ratio of equation (1). It will increase by a considerable amount.
Therefore, in Figure 6, as time elapses,
Even if the initial state is N, the up-down counter 8 always counts down to the 0 state. At this time,
As shown in FIGS. 2 and 7, the frame synchronization signal 25 is input to the transmission output signal 3, and during this time, the multiplexer 7 does not output the information signal 26, so the up-down counter 8 counts up again.
In addition, the transmission output signal 3, which is the minimum unit of error control,
1 block (information block 3 in Figures 2 and 4)
0 (indicated by b, b+1, . . . b+n) include check bits in addition to information bits.
Since the multiplexer 7 does not output the information signal 26 even while the test bit 27 is being input to the transmission output signal 3, the up-down counter circuit 8 counts up.

While the information signal 26 is being input to the transmission output signal 3, it is output from the multiplexer 7, so the countdown is performed at the ratio of equation (1) as described above. This situation is illustrated in FIGS. 7a and 7b. Here, the minimum unit of error control, which consists of a set of information bits 26 and check bits 27, is shown in Figs. 2 and 4, b.
(or b+1,..., b+n). This information bit 26 corresponds to j (or j +
1,...,j+n).

FIG. 3 shows an embodiment of the decoding circuit of the present invention. A received input signal 4 is input to a frame synchronization detection circuit 9, a division circuit 12, and a shift register 17. Syndrome signal 2 of the output of the divider circuit 12
4 indicates the remainder of the division, which is input to the syndrome expansion circuit 13, which outputs the error pattern signal 20 and the output of the shift register 17 as the received signal 2.
1 is input to the error correction circuit 18 and the error is corrected. The frame synchronization signal 25 and test signal 27 are removed from the output by the gate circuit 15 and input to the serial input parallel output shift register 6. Parallel output signal 2 of the output of the serial input parallel output shift register 6
3 is input to the multiplexer circuit 7, selected according to the state of the multiplexer control signal 22, and sampled by the flip-flop 16 to obtain the reception output signal 5.

On the other hand, the frame synchronization control signal 28 output from the frame synchronization detection circuit 9 is input to the control pulse generation circuit 10, and a clock pulse 19 synchronized with the received input signal 4 is obtained. A clock pulse 2 synchronized with the received output signal 5 is applied to an up-down counter circuit 8.
and its output multiplexer control line 2
2 is input to the multiplexer 7. To further explain how this works,
The syndrome signal 24 output from the division circuit 12 is subjected to syndrome expansion in the syndrome expansion circuit 13, and only the bit position where the error occurs is set to "1".
Then, an error pattern signal 20 is generated such that the correct bit position is "0". A received signal 21 corresponding to the error pattern signal is stored in the shift register 17, and this signal 21 and the error pattern signal 20 are input to the error correction circuit 18 at the same timing by the control pulse 19.

Since the test signal 27 and frame synchronization signal 25 are removed from the signal input from the gate circuit 15 to the serial input parallel output shift register 6, the control pulse 19 input to the serial input parallel output shift register 6 is As shown in the figure, the parallel output signal 23 is shifted by one clock and output as shown in the figure, and as shown in Fig. 6, the up-down counter is output every time one clock is input. Count up circuit 8. 8th
In the figure, a indicates the output signal of the gate circuit 15, b indicates the control pulse 19, and c indicates the delayed output of the shift register 6 from one stage to four stages.

Clock pulse 2 controls flip-flop 16 and causes up-down counter circuit 8 to count down as shown in FIG. As shown in FIG. 6, the up-down counter circuit 8 counts up by the number of bits input from the gate circuit 15, and counts down by the number of bits sampled by the flip-flop 16 when the parallel output signal 23 is selected by the multiplexer. do.

According to the above equation (2), the multiplexer control signal 2
2 indicates the address on the shift register where the first bit of the bit string input to the serial input parallel output shift register 6 is stored. Therefore, the received output signal 5 always has a bit string arranged in the same order as the information bits obtained from the output signal of the gate circuit 15.

FIGS. 4a and 4b show the relationship between the received input signal 4 and the received output signal 5. Since the bit rate of the received input signal 4 is set higher than the bit rate of the received output signal 5 according to the ratio of formula (1) above, the number of bits in the received input signal 4 is higher than that of the received output signal 5 in the formula (1). The amount increases by the ratio of 1). Therefore, in FIG. 6, even if the count starts from the initial state 0, the count gradually increases and approaches the maximum value N. However, the received input signal 4 includes a test signal 27 and a frame synchronization signal 25, and these signals are not only not input to the serial input parallel output shift register 6 as described above, but also input to the up/down counter circuit. 8 is not counted up, only the countdown operation is performed during this period, as shown in FIGS. 9a and 9b. Therefore,
If the bit rate is set to the ratio of equation (1), the bit rate of the signal can be converted without the number of delay stages exceeding the number of stages of the serial input parallel output shift register 6.

As explained above, the present invention inputs an input code pulse train to a serial input parallel output shift register,
The shift register is shifted by a clock pulse synchronized with the code pulse train, and at the same time an up-down counter circuit is counted up, the output of the shift register is input to a multiplexer controlled by the up-down counter, and the output is output as an output code. By sampling and extracting data using a clock pulse synchronized with the pulse train and by configuring the up-down counter to count down, it becomes possible to operate the input code pulse train and the output code pulse train asynchronously at different bit rates. It becomes possible to easily add or remove an error correction code from the line, and it becomes possible to arbitrarily apply an error control method that is optimal for the transmission characteristics of the line without changing the original code generation circuit. It has the advantage of being highly versatile, allowing the transmission efficiency and reliability of information codes to be significantly improved by simply adding a simple circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the encoding circuit according to the present invention, Figs. 2, 5 and 7 are time charts when the above circuit is operated, and Fig. 6 is an up-down counter circuit. FIG. 3 is a circuit diagram of the decoding circuit, and FIGS. 4, 8, and 9 are time charts thereof. 1... Transmission input signal, 2... Clock pulse,
3... Transmission output signal, 4... Reception input signal, 5...
... Reception output signal, 6 ... Series input parallel output shift register, 7 ... Multiplexer, 8 ... Up-down counter circuit, 9 ... Frame synchronization detection circuit, 10 ... Control pulse generation circuit, 11 ... Frame synchronization signal Generation circuit, 12... Division circuit, 13
... syndrome expansion circuit, 14 ... multiplexing circuit, 15 ... gate circuit, 16 ... flip-flop, 17 ... shift register, 18 ... error correction circuit, 19 ... control pulse, 20 ... error pattern signal, 21... Reception signal, 22... Multiplexer control signal, 23... Parallel output signal, 24...
... Syndrome signal, 25 ... Frame synchronization signal, 26 ... Information signal, 27 ... Test signal, 28
... Frame synchronization control signal, 29 ... Transmission signal,
30...Error control block group, 31...Information bit block group (in the error control block).

Claims (1)

[Claims] 1. A serial input/parallel output shift register that takes a transmission input signal as an input and performs a shift operation using a clock synchronized with this input signal.The output of this shift register is taken as one input, and the bit rate is changed between the input and the bit rate by a control signal input to the other input. a multiplexer for outputting different series pulse trains; up-counting by the clock and down-counting by a clock synchronized with the output of the multiplexer;
and an up-down counter that switches and outputs the input of the multiplexer using the count value as the control signal, and the input signal and the output of the multiplexer operate asynchronously to add and remove an error control code. A serial input serial output type error control encoding/decoding circuit.