JPS6221290A - Wiring board for semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a wiring board for a semiconductor device. More specifically, the present invention relates to a single-layer or multi-layer wiring board for a semiconductor device useful for satisfying demands for higher density, smaller size, etc. of electronic circuits, and a method for manufacturing the same.

Conventional technology In order to systemize electronic equipment or configure functional units, a board is required to mount predetermined active and passive elements in the designed layout and to make electrical connections between them. It is said that This board is required to satisfy various requirements: it must be capable of achieving high precision and diverse functions of the unit, it must be able to be made compact over time, and it must also have high reliability. Typical requirements include that it be of high quality, that circuit formation can be automated, and that total costs including maintenance can be reduced.

Conventionally, substrates for such integration can be roughly divided into three types: ceramic substrates, metal-based substrates, and resin substrates.
Each species has unique properties and is used depending on the purpose and use.

Further, in order to increase the density of electronic circuits, attention has been paid to stacking circuits to make them multilayered. Conventionally, when forming multilayer wiring on such semiconductor device substrate materials, the following three methods have been mainly adopted. That is, the first method is to form an organic adhesive layer on an insulating base material 1 (an insulating sheet pasted on a conductor is also acceptable) as shown in FIGS. 2(a) to (C). A conductor layer 3 is provided through the conductor layer 2 (see Fig. 2(a)), or a conductor layer is formed by electroless plating, and the conductor layer 3 is formed into a predetermined wiring using an appropriate photo-etching technique. (see FIG. 2, et al.)), and further provide an insulating sheet 5 via the adhesive layer 4 (see FIG. 2(C)), or repeat the above operation as many times as necessary to form a predetermined multilayer wiring structure. is formed and used as a substrate.

The second method uses thick film printing technology to
A conductor 11, a resistor (including a dielectric material, an insulating glass layer, etc.) 12, and a second conductor 13 are printed on top as shown in FIG. 3, and the resulting laminate is fired to form a multilayer structure. It consists of obtaining a substrate.

Furthermore, the third method is to create a ceramic green sheet and print a special M on the green sheet using printing technology.
Wiring is performed using a conductive paste containing a conductive substance such as O, W, etc., dried, and green sheets are stacked on top of each other to print the wiring, which is repeated, followed by pressing and firing.

If a through hole or a contact hole is required in these methods, the hole is formed by a photoetching method or a printing method, and the above operation is performed while filling the hole with a conductive paste or the like.

In addition, various methods have been attempted in which the three methods described above are combined. In recent years, there has been a strong trend toward faster operation, higher density packaging, and larger sizes for semiconductor devices, and for semiconductor devices, there has been a strong trend toward faster speeds, higher density, and smaller sizes. Improvement of heat dissipation, thinning, reduction of resistance of wiring conductors, shortening of wiring distance, direct mounting of semiconductor elements, unification of mounting technology,
The development of technology that can satisfy various requirements such as simplifying the mounting process is desired, and extensive research is being conducted.

Problems to be Solved by the Invention As mentioned above, in order to meet the demands for faster operation, higher density, etc. for semiconductor elements and devices, there are also demands for the substrates used for packaging and mounting these semiconductor elements and devices. In order to fully utilize the functions of improved elements and devices, improvements to substrates must be made in parallel.

Therefore, recently, multilayer wiring boards have been attracting attention, and the above-mentioned method for each layer has been known and used as a manufacturing method thereof. However, regarding the first method, the thermal conductivity of the organic sheet and adhesive is low, and the thickness of the insulating sheet cannot be reduced due to dielectric strength requirements and processing limitations (generally 100%
(the lower limit is μm), it is not possible to ensure sufficient heat dissipation, which is important in packaging. In addition, since organic materials with poor heat resistance and high hygroscopicity are used, sufficient sealing performance of semiconductor elements cannot be guaranteed.
It has drawbacks such as difficulty in directly mounting semiconductor elements on a substrate.

In the second method as well, the firing conditions for the paste material are severe at around 850°C in the air, so the base substrate is limited to those made of oxide ceramics or those whose surfaces are covered with such ceramics. , therefore the heat dissipation is poor. Incidentally, some ceramics such as BaO are known to have excellent thermal conductivity, but they are expensive and have toxicity problems, so they are not used much. Furthermore, with the current level of ceramic manufacturing technology, it is difficult to manufacture ceramics with a thickness of 0.3 mm or less;
~0.6 mm is the limit that can be manufactured reliably. This is due to the problems of cracking and warping that occur during handling during paste printing, baking, and mounting processes. Furthermore, it is difficult to reduce the thickness of the glass insulating layer to 40 μm or less, and furthermore, it is extremely difficult to reduce the thickness of each layer to 10 μm or less due to the nature of the paste. Therefore,
With this second method, it is difficult to reduce the thickness. Further, due to the characteristics of the paste, if the wiring width is made thinner than a certain value, predetermined electrical characteristics cannot be obtained even after firing. That is, in general, the lower limit of the wiring width is practically about 150 μm. Therefore, with this method, it is difficult to shorten the wiring distance, and the method does not satisfy the requirements for higher density, smaller size, or higher speed operation of devices. Recently, attempts have been made to realize a line width of about 30 to 50 μm through the development of intaglio printing technology and special pastes, but these have not been widely used so far.

Finally, in the third method, the ceramic materials that can be used with the green sheet method are limited to a few types, including Al2O3, and Al2O3 is generally widely used, but it has poor thermal conductivity. Furthermore, since it is practically difficult to reduce the thickness of the green sheet to 0.3 mm or less, the resulting substrate has poor heat dissipation properties. In addition, only Mo and W-based conductor materials can be used, and these have higher conductor resistance than Cu and Ag-based materials, so there are limitations in reducing the conductor resistance. For the same reasons as described for method 2, it is difficult to shorten the wiring distance and, by extension, to achieve high-speed operation, high density, and miniaturization of semiconductor devices and the like.

Therefore, developing a new wiring board or its manufacturing method that can overcome the drawbacks of the methods described above is important not only to improve the board itself, but also to meet the various requirements of each Yuzu semiconductor element and device. I have an extremely large amount of envy. The purpose of the present invention is also in this point, with good heat dissipation,
An object of the present invention is to provide a thin wiring board for mounting a semiconductor device, which can shorten wiring and lower resistance.

Means for Solving the Problems The inventors of the present invention have conducted various studies in order to solve the various drawbacks of the conventional wiring boards for semiconductor devices as described above. The present inventors have discovered that problems such as diversification of the materials used, thinning of the substrate, and reduction in the width of the wiring 4 can be solved by performing the formation using thin film formation technology, and have completed the present invention.

That is, in the method of manufacturing a wiring board for a semiconductor device of the present invention, thin films of an insulating material and a conductive material are alternately deposited on a conductive substrate base material through a vapor phase of the material or a substance constituting the material. Each layer is formed in a predetermined pattern by selective deposition using a mask or by partial etching after deposition of a thin film.

First, the substrate base material may be any conductive material as described above. Typical examples include metals such as Cu, Al, Ti, Fe, Ni, Mo, W,
1 selected from the group consisting of Si or alloys thereof
I can name the seeds.

Further, as a material for a conductor layer (wiring layer), [u.

A1. , Ni, Ag, Au, Pt5Ti, Ta, Mo,
One or more selected from the group consisting of W, Si, and alloys thereof, conductive ceramics such as ITO (In2035nO-), and conductive plastics can be used.

Also, carbides, nitrides, carbonitrides, borides, silicides, oxides of IVa group, Va group, VIa group and ZnO2, Sn
○2, In2O3, and ReO3-based oxides may be used.

Furthermore, there are no particular restrictions on the insulating material, and various conventionally known materials can be used. Incidentally, if oxide or nitride ceramics are used, conventional mounting techniques can be used as is, which is advantageous.

These conductive wiring forming layers and insulating layers are deposited on the substrate base by a sputtering method, a CVD method, a vapor deposition method, etc., which can be formed at a particularly low temperature. It is advantageous to use an organic CVD method, a vapor deposition method, a vapor deposition method that ionizes a part of the deposited substance, or a photo-CVD method, which can be appropriately selected and used depending on the material.

According to the method of the present invention, a substrate for a semiconductor device is provided which has an insulating layer having a thickness of 2 to 20 μmc7M'c and a conductive wiring layer having a thickness of 0.5 to 10 μm. For example, as shown in FIG. 1, the structure is such that a thin film insulating layer 21, a thin film conductor wiring 22, a thin film insulating layer 23, and a second thin film conductor wiring 24 are deposited in this order on a conductor base material 20, Partially etched if necessary, or
(See Figure 1).

Etching treatment of each deposited layer can be carried out according to various conventionally known methods. That is, a wet etching method using an etching solution such as hydrochloric acid, or a dry etching method such as reactive ion etching or sputter etching can be used, and the most suitable method should be selected and used depending on the material to be etched. Can be done.

The single-layer or multilayer wiring board obtained by the method of the present invention can be applied to various semiconductor elements and devices including ICs.

Thus, according to the method of the present invention, the conductor layer and the insulator layer are formed on the semiconductor substrate base material by the thin film formation method, so that the conductor layer and the insulator layer can be used as the substrate base material, conductor material, and insulator material. The selection range is widened, and the overall thickness of the board can be easily reduced.

In the method of the present invention, the insulator layer and the conductor layer are in the range of 2 to 20 μm and 0.5 to 10 μm, respectively;
First, looking at the insulator layer, it changes somewhat depending on the surface condition of the base material, but for materials other than those with a mirror finish, insulation is applied over a large area with less than 2 μm (on lclTIJJ).
It is actually difficult to secure a thickness of 20 μm.
If it exceeds the above, it will impede the thinning and heat dissipation properties intended in the present invention, and depending on the material of the insulating layer, stress will become large, causing warpage or making multilayer wiring difficult, so either of these is not preferable.

Furthermore, if the film thickness of the conductor wiring is less than 0.5 μm, the wiring resistance will become too large when a fine pattern is formed, and if it exceeds 10 μm, the thickness of the insulating layer should be 20 μm or more. Otherwise, it is not preferable because a predetermined dielectric strength voltage cannot be ensured, the yield is greatly reduced, and the productivity is reduced.

What is particularly important in this type of wiring board is good heat dissipation from the standpoint of package thermal design. In the present invention, materials with good heat dissipation properties can be freely combined and used, and the insulating layer can be made thin, so that a substrate with high heat dissipation properties can be provided. In particular, a wiring board with high heat dissipation using a conductive base material can be realized.

Furthermore, in semiconductor elements and devices that require high-speed operation, it is necessary to reduce wiring resistance and shorten delay time. Regarding this point as well, the present invention does not require a firing process, low resistance materials can be selected freely, and wiring patterns can be made finer, so wiring resistance can be reduced and high-speed operation can be achieved. It can be said that it is fully satisfactory as a substrate for elements and devices that require high performance.

Furthermore, in response to recent trends in semiconductor devices toward higher density and miniaturization, metal can be used as the base material, and the thickness can be reduced to about 0.2 mm, and insulators can be used. Since the conductor layer and the conductor layer are formed using thin film technology, it is possible to make the device sufficiently thin, and it can be used satisfactorily.

However, even if metal is used as the base material, the thickness is 0.1 m.
If the thickness is less than m, problems such as warping may occur and handling becomes difficult.

In addition, by using ceramics as an insulator,
Conventional mounting techniques can be used as is, and semiconductor elements can be directly mounted.

Suitable man Hereinafter, the present invention will be explained in more detail according to Examples.

However, the scope of the present invention is not limited in any way by the following examples.

A multilayer wiring board having the structure shown in FIG. 1 et al. was fabricated. A1 alloy was used as the substrate base material, and Al and Al2O3 were used as the conductor wiring layer and the insulator layer, respectively.

The alumina layer serving as the insulator layer was formed to a thickness of 10 μm by ion blasting, and the conductor wiring layer was formed by depositing AI to a thickness of 3 μm by vapor deposition, and then etching it into a predetermined pattern by wet etching with dilute hydrochloric acid at 50°C. The lines were etched to have a minimum line width and line spacing of 50 μm. As a result, it was possible to obtain a substrate with a withstand voltage of 500μ or more.

Effects of the Invention As explained in detail above, according to the present invention, by utilizing thin film formation technology for forming an insulating layer and a conductive wiring layer on a substrate base material, the range of materials that can be used can be further expanded. In addition, various benefits such as no need for a firing process can be obtained, and as a result, a thin and highly reliable wiring board for mounting a semiconductor device with high heat dissipation properties can be obtained.

In addition, according to the present invention, since there is a wide range of materials to choose from, it is possible to make fine conductor wiring using low-resistance materials. A wiring board capable of high-speed operation can be provided.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view schematically showing one preferable embodiment of the wiring board for a semiconductor device of the present invention, and FIG.
C) is a schematic diagram for explaining one method of applying multilayer wiring to a conventional board material, and FIG. 3 is a schematic diagram for explaining a multilayer wiring board different from the conventional one shown in FIG. It is a diagram. (Main reference numbers) 1.10.20...Base material, 2.4...Adhesive, 3.11.13...Conductor layer, 5...Insulating sheet, 12... ...Glass insulating layer, 22...Thin film conductor wiring layer, 21.23...Thin film insulator layer,

Claims (12)

[Claims] (1) A process of alternately depositing thin films of an insulator and a conductive substance on a conductive substrate base material through the vapor phase of the substance or a substance constituting the substance, and each layer is selectively deposited by using a mask. 1. A method of manufacturing a wiring board for a semiconductor device, characterized in that the wiring board is formed in a predetermined pattern by deposition treatment or by partial etching treatment after deposition of a thin film. (2) The method according to claim 1, wherein the thin film is formed by a sputtering method, a CVD method, or a vapor deposition method. (3) a sputtering method, a plasma CVD method, a metal organic CVD method, a photo-CVD method, in which the thin film applies a magnetic field;
3. The method according to claim 2, characterized in that it is formed by a vapor deposition method or a vapor deposition method that ionizes a part of the vapor deposited substance. (4) The substrate base material is Cu, Al, Ti, Fe, N
4. The method according to claim 3, wherein the material is one selected from the group consisting of i, Mo, W, Si, and alloys thereof. (5) The conductive substance is Cu, Al, Ti, Ni, Au
, Ag, Pt, Ta, Mo, W, Si and alloys thereof, conductive ceramics, and conductive plastics. (6) The method according to claim 5, wherein the insulator is an oxide or a nitride. (7) The conductive substance is a group IVa, Va, or VIa group carbide, nitride, carbonitride, boride, silicide, oxide, or an oxide whose main component is ZnO, SnO_2, In_2O_3, or ReO_3. 6. A method according to claim 5, characterized in that: (8) A conductive substrate base material, and a plurality of thin film layers having a predetermined pattern obtained by alternately providing an insulating material and a conductive material on the base material in this order, wherein each insulating layer is A wiring board for a semiconductor device, characterized in that the thickness is 1 μm or more and 20 μm or less, and each conductive layer has a thickness of 0.5 μm or more and 10 μm or less. (9) The substrate base material is Cu, Al, Ti, Fe, N
9. The wiring board for a semiconductor device according to claim 8, wherein the wiring board is one selected from the group consisting of i, Mo, W, Si, and alloys thereof. (10) The conductive substance is Cu, Al, Ti, Ni, A
10. The wiring board for a semiconductor device according to claim 9, which is selected from the group consisting of u, Ag, Pt, Ta, Mo, W, Si, alloys thereof, conductive ceramics, and conductive plastics. (11) The wiring board for a semiconductor device according to claim 10, wherein the insulator is an oxide or a nitride. (12) The conductive substance is a group IVa, Va, or VIa group carbide, nitride, carbonitride, boride, silicide, oxide, or an oxide whose main component is ZnO, SnO_2, In_2O_3, or ReO_5. 11. The wiring board for a semiconductor device according to claim 10, wherein: