JPS6221277B2 - - Google Patents

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Publication number
JPS6221277B2
JPS6221277B2 JP1891179A JP1891179A JPS6221277B2 JP S6221277 B2 JPS6221277 B2 JP S6221277B2 JP 1891179 A JP1891179 A JP 1891179A JP 1891179 A JP1891179 A JP 1891179A JP S6221277 B2 JPS6221277 B2 JP S6221277B2
Authority
JP
Japan
Prior art keywords
layer
type semiconductor
semiconductor layer
thyristor
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1891179A
Other languages
Japanese (ja)
Other versions
JPS55111169A (en
Inventor
Yoshiki Hamaguchi
Yutaka Oosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansha Electric Manufacturing Co Ltd
Original Assignee
Sansha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansha Electric Manufacturing Co Ltd filed Critical Sansha Electric Manufacturing Co Ltd
Priority to JP1891179A priority Critical patent/JPS55111169A/en
Publication of JPS55111169A publication Critical patent/JPS55111169A/en
Publication of JPS6221277B2 publication Critical patent/JPS6221277B2/ja
Granted legal-status Critical Current

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  • Thyristors (AREA)

Description

【発明の詳細な説明】 この発明は、逆導通サイリスタの製造方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a reverse conducting thyristor.

従来、逆導通サイリスタには第1図に示すよう
なものがあつた。この逆導通サイリスタは、NB
層1の一方の主表面の所定位置を選択拡散によつ
てN+領域とした後、NB層の両側よりガリウム等
のP型不純物を拡散させて、N+領域をN領域に
反転させると共にPB層2及びPE層3を形成し、
その後PB層2にN型不純物を選択拡散させて、
E層4を形成して製造する。この方法ではPB
2を深い一様な拡散層とするためにガリウムを使
用するが、ガリウムは選択拡散ができないので、
E層3の厚さH1はPB層2の厚さH2と等しく約
40〜50μになる。逆導通サイリスタはサイリスタ
部と、ダイオード部を組合せたものであるのでサ
イリスタ部の逆耐圧は不要でPE層の厚さは数μ
でよく、上述した方法で製造した逆導通サイリス
タではPE層3が必要以上に厚くなつていた。ま
た逆導通サイリスタをインバータ等に使用する場
合ある程度の高速性が必要で、高速性を増加させ
るために金をサイリスタ内に特にNB層1内に拡
散させて、キヤリヤのライフタイムを短くしてタ
ーンオフタイムを短くすることが行われていた。
しかし、PE層3が厚いと、所定のターンオフタ
イムを得るために、金拡散温度を高くしてNB
内に多くの金を拡散させることが行われていた。
金拡散温度が高いと、オン電圧が高くなり電力損
失が大きくなつていた。たとえば、PE層をPB
に対して薄くする製造方法としては、PB層及び
B層からなるPN接合基体を形成し、PB層に選
択拡散してNE層を形成した後、PB層側の主表面
全域を酸化膜で被覆し、P型不純物をNB層側の
主表面から拡散させて、PB層と比較して薄いPE
層を形成するものが考えられる。しかし、これで
はPE層を形成する際に、PB層側の主表面全域を
酸化膜で被覆しなければならず、製造コストが高
くなるという問題点がある。
Conventionally, there has been a reverse conduction thyristor as shown in FIG. This reverse conducting thyristor is N B
After selectively diffusing a predetermined position on one main surface of layer 1 to form an N + region, a P-type impurity such as gallium is diffused from both sides of the N B layer to invert the N + region into an N region. forming a P B layer 2 and a P E layer 3;
After that, N-type impurities are selectively diffused into the P B layer 2,
N E layer 4 is formed and manufactured. In this method, gallium is used to make the P B layer 2 a deep and uniform diffusion layer, but since gallium cannot be selectively diffused,
The thickness H 1 of P E layer 3 is approximately equal to the thickness H 2 of P B layer 2.
It becomes 40-50μ. Since a reverse conduction thyristor is a combination of a thyristor part and a diode part, there is no need for reverse breakdown voltage in the thyristor part, and the thickness of the P E layer is only a few microns.
However, in the reverse conduction thyristor manufactured by the method described above, the PE layer 3 was thicker than necessary. Furthermore, when a reverse conduction thyristor is used in an inverter, etc., a certain level of high speed is required, and in order to increase the speed, gold is diffused into the thyristor, especially in the N B layer 1, to shorten the carrier lifetime. Efforts were being made to shorten the turn-off time.
However, when the P E layer 3 is thick, in order to obtain a predetermined turn-off time, the gold diffusion temperature has been raised to diffuse a large amount of gold into the N B layer.
When the gold diffusion temperature is high, the on-voltage increases and power loss increases. For example, a manufacturing method for making the P E layer thinner than the P B layer is to form a PN bonded substrate consisting of a P B layer and an N B layer, selectively diffuse into the P B layer to form the N E layer, and then , the entire main surface on the P B layer side is covered with an oxide film, and the P type impurity is diffused from the main surface on the N B layer side to form a thin P E layer compared to the P B layer.
One that forms layers can be considered. However, this has the problem that when forming the P E layer, the entire main surface on the P B layer side must be covered with an oxide film, which increases manufacturing costs.

この発明は、PB層に比較して薄いPE層を有す
る逆導通サイリスタを安価に製造できる方法を提
供することを目的とする。
An object of the present invention is to provide a method of manufacturing a reverse conduction thyristor having a P E layer thinner than the P B layer at low cost.

以下この発明を第2図乃至第8図に示す1実施
例に基づいて説明する。
The present invention will be explained below based on one embodiment shown in FIGS. 2 to 8.

まず第2図に示すようにN型シリコン半導体基
体内に、その両主表面よりガリウムを拡散させ、
N型半導体層6及びP型拡散層8,8を形成す
る。次に第2図におけるP型拡散層8,8のうち
どちらか一方をエツチングまたはラツピングによ
つて除去し、第3図に示すようなPN接合基体を
形成する。以下、N型半導体層6をNB層6と、
残したP型半導体層8をPB層8と称する。な
お、P型拡散層8を除去する場合、NB層6の一
部まで除去してもよい。
First, as shown in Figure 2, gallium is diffused into the N-type silicon semiconductor substrate from both its main surfaces.
An N-type semiconductor layer 6 and P-type diffusion layers 8, 8 are formed. Next, one of the P-type diffusion layers 8, 8 in FIG. 2 is removed by etching or wrapping to form a PN junction substrate as shown in FIG. 3. Hereinafter, the N-type semiconductor layer 6 will be referred to as the N B layer 6,
The remaining P-type semiconductor layer 8 is referred to as a P B layer 8. Note that when removing the P-type diffusion layer 8, even a part of the N B layer 6 may be removed.

次に第4図に示すようにPB層8のサイリスタ
部にNリツチであるNE層24を、NB層6のダイ
オード部にN+領域26をそれぞれリンを選択拡
散して形成する。次に第4図に示す主表面28,
30よりガリウムを薄く拡散させて、第5図に示
すようにNB層6に厚さ数μのPE層32を形成す
る。このときN+領域26はガリウムによつてN
領域に反転するが、NE層24はNリツチに形成
してあるのでP型には反転しない。最後に第6図
に示すように主表面28のサイリスタ部及び主表
面30のダイオード部を二酸化ケイ素膜33,3
4でそれぞれ被覆した後、金を露出面28,30
より拡散させる。
Next, as shown in FIG. 4, an N-rich N E layer 24 is formed in the thyristor portion of the P B layer 8, and an N + region 26 is formed in the diode portion of the N B layer 6 by selectively diffusing phosphorus. Next, the main surface 28 shown in FIG.
By diffusing gallium thinner than 30, a P E layer 32 with a thickness of several μm is formed on the N B layer 6, as shown in FIG. At this time, the N + region 26 is N
However, since the N E layer 24 is formed to be N-rich, it does not invert to P type. Finally, as shown in FIG.
4, the exposed surfaces 28 and 30 are coated with gold.
Make it more diffuse.

このようにして製造した逆導通サイリスタのサ
イリスタ部と従来の方法で製造した逆導通サイリ
スタのサイリスタ部のオン電圧―ターンオフタイ
ムの関係を第7図に示す。曲線36が従来のサイ
リスタ部の特性を表わし、曲線38がこの発明に
よるサイリスタ部の特性を表わす。同図からも分
るようにこの発明による逆導通サイリスタはPE
層32を薄く形成しているので従来よりも低い温
度でNB層6まで金拡散ができ、よつてターンオ
フタイムを短くできると同時にオン電圧が約
0.3V低くなつている。またPE層32が薄いので
サイリスタとダイオードとの分離が完全に行わ
れ、転流失敗が発生しない。また第8図にこの発
明によつて製造した逆導通サイリスタのダイオー
ドと従来の方法によつて製造した逆導通サイリス
タのダイオードとのダイオード電圧―ダイオード
レカバリタイムの関係を示す。曲線40が従来の
逆導通サイリスタの特性を表わし、曲線42がこ
の発明による逆導通サイリスタの特性を表わす。
同図からも判るように同一レカバリタイムでもこ
の発明による逆導通サイリスタのダイオード電圧
が約0.2V低くなつている。
FIG. 7 shows the relationship between on-voltage and turn-off time of the thyristor portion of the reverse conduction thyristor manufactured in this manner and the thyristor portion of the reverse conduction thyristor manufactured by the conventional method. Curve 36 represents the characteristics of a conventional thyristor section, and curve 38 represents the characteristics of a thyristor section according to the invention. As can be seen from the figure, the reverse conduction thyristor according to the present invention has P E
Since the layer 32 is formed thin, gold can be diffused up to the N B layer 6 at a lower temperature than before, thereby shortening the turn-off time and at the same time reducing the on-voltage to approx.
It is 0.3V low. Furthermore, since the P E layer 32 is thin, the thyristor and diode are completely separated, and commutation failure does not occur. Further, FIG. 8 shows the relationship between diode voltage and diode recovery time between a diode of a reverse conduction thyristor manufactured by the present invention and a diode of a reverse conduction thyristor manufactured by the conventional method. Curve 40 represents the characteristics of a conventional reverse conducting thyristor, and curve 42 represents the characteristics of a reverse conducting thyristor according to the invention.
As can be seen from the figure, even with the same recovery time, the diode voltage of the reverse conduction thyristor according to the present invention is lower by about 0.2V.

以上のように、この発明の逆導通サイリスタの
製造方法では、NE層24をNリツチに形成する
と共にN+領域26を形成しているので、主表面
28,30より不純物を拡散しても、NE層24
はP型に反転せず、またN+領域26の部分を除
いて主表面30側はPE層32に反転する。従つ
て、選択拡散を用いないで、PE層32をPB層8
に比較して薄くできる。このように、選択拡散を
用いないで、PE層32を薄く形成できるので逆
耐圧が不要な逆導通サイリスタの製造コストを引
下げられる。
As described above, in the method for manufacturing a reverse conduction thyristor of the present invention, since the N E layer 24 is formed to be N-rich and the N + region 26 is formed, impurities can be diffused from the main surfaces 28 and 30. , N E layer 24
is not inverted to P type, and the main surface 30 side except for the N + region 26 is inverted to P E layer 32. Therefore, without using selective diffusion, the P E layer 32 is replaced with the P B layer 8.
It can be made thinner compared to . In this way, the P E layer 32 can be formed thin without using selective diffusion, so that the manufacturing cost of a reverse conduction thyristor that does not require reverse breakdown voltage can be reduced.

なお、上記の実施例において、第3図に示すよ
うにP型拡散層8の一方を除去した直後に、ガリ
ウムを主表面12,14,28,30より薄く拡
散してPE層32を形成した後に、リンを選択拡
散してNE層24を形成することも考えられる
が、リンを選択拡散するときの熱でガリウムが深
く浸透してPE層32が厚くなり、オン電圧が高
くなるので好ましくない。
In the above embodiment, as shown in FIG. 3, immediately after removing one of the P-type diffusion layers 8, gallium is diffused to be thinner than the main surfaces 12, 14, 28, and 30 to form the PE layer 32. After that, it is possible to selectively diffuse phosphorus to form the NE layer 24, but the heat generated when selectively diffusing phosphorus causes gallium to penetrate deeply, making the PE layer 32 thicker and increasing the on-state voltage. So I don't like it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の製造方法で製造した逆導通サイ
リスタの縦断面図、第2図乃至第6図はこの発明
による製造方法で逆導通サイリスタを製造する過
程を示す縦断面図、第7図はこの発明による製造
方法で製造した逆導通サイリスタ及び従来の製造
方法で製造した逆導通サイリスタのサイリスタ部
のオン電圧―タンオフタイム特性図、第8図は同
逆導通サイリスタのダイオード弾圧―レカバリタ
イム特性図である。 6…第1のN型半導体層、8…第1のP型半導
体層、24…第2のN型半導体層、32…第2の
P型半導体層、33,34…二酸化ケイ素膜(マ
スク膜)、26…N+領域。
FIG. 1 is a longitudinal sectional view of a reverse conduction thyristor manufactured by a conventional manufacturing method, FIGS. 2 to 6 are longitudinal sectional views showing the process of manufacturing a reverse conduction thyristor by the manufacturing method according to the present invention, and FIG. On-voltage-turn-off time characteristic diagram of the thyristor portion of the reverse conduction thyristor manufactured by the manufacturing method according to the present invention and the reverse conduction thyristor manufactured by the conventional manufacturing method, and Fig. 8 is a diode suppression-recovery time characteristic diagram of the same reverse conduction thyristor. It is. 6... First N-type semiconductor layer, 8... First P-type semiconductor layer, 24... Second N-type semiconductor layer, 32... Second P-type semiconductor layer, 33, 34... Silicon dioxide film (mask film) ), 26...N + area.

Claims (1)

【特許請求の範囲】[Claims] 1 N型半導体層の両主表面からそれぞれP型不
純物を拡散して上記両主表面からそれぞれ所定の
深さまでP型半導体層を形成する工程と、上記両
P型半導体層の一方を除去して第1のN型半導体
層と第1のP型半導体層とからなるPN接合半導
体基体を形成する工程と、上記基体の第1のP型
半導体層の主表面の第1の所定位置と第1のN型
半導体層の主表面の第1の所定位置とは対向しな
い第2の所定位置とにN型不純物を選択拡散して
第1の所定位置にNリツチな第2のN型半導体層
を第2の所定位置にN+型半導体層を形成する工
程と、第1のP型半導体層側の主表面及び第1の
N型半導体層側の主表面からそれぞれ選択拡散で
きないP型不純物を短時間拡散させて第1のN型
半導体層側の主表面の第2の所定位置以外の面に
第1のP型半導体層の厚さに比較して薄い厚さの
第2のP型半導体層を形成する工程とを備える逆
導通サイリスタの製造方法。
1. Diffusing P-type impurities from both main surfaces of the N-type semiconductor layer to form P-type semiconductor layers from both main surfaces to predetermined depths, and removing one of the P-type semiconductor layers. forming a PN junction semiconductor base including a first N-type semiconductor layer and a first P-type semiconductor layer; selectively diffusing N-type impurities into a second predetermined position that is not opposite to the first predetermined position on the main surface of the N-type semiconductor layer to form a second N-rich N-type semiconductor layer in the first predetermined position; A step of forming an N + type semiconductor layer at a second predetermined position, and shortening P type impurities that cannot be selectively diffused from the main surface on the first P type semiconductor layer side and the main surface on the first N type semiconductor layer side, respectively. By time-diffusion, a second P-type semiconductor layer having a thickness thinner than that of the first P-type semiconductor layer is formed on a surface other than the second predetermined position of the main surface on the side of the first N-type semiconductor layer. A method for manufacturing a reverse conduction thyristor, comprising the step of forming a reverse conducting thyristor.
JP1891179A 1979-02-19 1979-02-19 Method of manufacturing semiconductor device Granted JPS55111169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1891179A JPS55111169A (en) 1979-02-19 1979-02-19 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1891179A JPS55111169A (en) 1979-02-19 1979-02-19 Method of manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS55111169A JPS55111169A (en) 1980-08-27
JPS6221277B2 true JPS6221277B2 (en) 1987-05-12

Family

ID=11984781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1891179A Granted JPS55111169A (en) 1979-02-19 1979-02-19 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS55111169A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63260174A (en) * 1987-04-17 1988-10-27 Sanyo Electric Co Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS55111169A (en) 1980-08-27

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