JPS6245709B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a semiconductor device, and particularly to a P ₁ −N ₁ −
This invention relates to improving the gate characteristics of a thyristor having a P ₂ −N ₂ four-layer structure.

In conventional thyristors with a P ₁ −N ₁ −P ₂ −N ₂ structure, impurities such as boron and _gallium are diffused at high temperature from both sides of an N ₁ type substrate to form the P _{1 and} P ₂ layers. and P ₂ layers are provided, and an impurity such as phosphorus is further diffused from one side to form an N ₂ layer.

Considering the Fermi level of P-type semiconductors and N-type semiconductors, the higher the impurity concentration, the higher the Fermi level is in the valence band in P-type semiconductors, and in the conduction band in N-type semiconductors, so the contact potential difference V ₀ of the PN junction is P In both cases, as the impurity concentration increases, V ₀ tends to increase. Therefore, considering a P ₂ −N ₂ diode, if the impurity concentration gradient of the N ₂ layer is almost equal in the horizontal and vertical directions near the surface-periphery junction, then the forward rise voltage will be higher if the impurity concentration of the P ₂ layer is higher. _V0 is high.

In this case, since the P-type impurity is diffused inward from both main surfaces of the silicon substrate, the concentration of the diffused impurity decreases as it goes inward from the surface. Therefore, the impurity concentration of the P 2 region near the junction where the cathode N ₂ region crosses the P ₂ region at the deepest position in the vertical direction is lower than the impurity concentration near the surface of _the gate P ₂ region. Therefore, positive to the gate,
When a negative voltage is applied to the cathode, current begins to flow through the internal PN junction farther from the surface layer and electrons are emitted inward. For this reason, the minority carriers emitted from the emitter N ₂ of the N ₂ P ₂ N ₁ transistor effectively work as an emitter current, and the gate current, which is a very small base current, causes P ₁ −N ₁ −
The P ₂ −N ₂ thyristor is brought into conduction. Therefore, the gate trigger current (I _GT ), which is the minimum gate current required to bring the thyristor into conduction, is extremely small, less than 10 A. Conventionally, when forming the cathode _N2 region by a diffusion method in order to increase I _GT , an oxide film is selectively left in dots on the silicon oxide film using optical means, and then the _N2 region becomes phosphorous. By diffusing N, etc., a region is created where N does not enter, and this region becomes a type in which the P ₂ layer in the gate region is exposed at the surface. When an electrode was then formed on this, a so-called shot emitter structure was adopted in which P ₂ -N ₂ was connected by the electrode and shot. Since the current flowing between the gate and the cathode in this shot region flows as a reactive current, I _GT can be increased by the amount of current determined by the shot resistance. However, it has been extremely difficult to manufacture a device with a high reproducibility of several μA to 1 mA due to the combination of the precision of the optical method and the precision of diffusion control.

Therefore, it is an object of the present invention to provide a thyristor manufactured with good reproducibility so that I _GT is, for example, about several μA to 1 mA.

In order to solve the above drawback, it is sufficient to actively flow a reactive current through the surface layer, so that P ₂ − near the surface
The forward rising voltage V ₀ of the N ₂ junction is expressed as the internal P ₂ −N ₂
It is sufficient if the voltage is lower than the junction rise voltage V ₀ .
Therefore, the gate electrode is provided for the same reason as before.
The impurity concentration of the P ₂ region surface layer is reduced by diffusion method or heat treatment to reduce the impurity concentration of the P ₂ region layer at the junction position where the N ₂ region layer where the cathode electrode is provided intersects with the P ₂ region layer at the deepest vertical position. Make it lower than the impurity concentration. In this way, P ₂ near the surface layer
The rising voltage of the −N ₂ diode is low and in the low current region, current first flows through this portion, so it becomes a reactive current and no minority carriers are emitted toward the inside. Therefore, I _GT can be precisely controlled to about several μA to 1 mA.

For example, in the present invention, a first impurity having a conductivity type opposite to that of the substrate impurity is diffused from both sides of a semiconductor substrate, and an impurity having the same conductivity type as the substrate is partially diffused from one side of the _{semiconductor} substrate. −N ₁ −P ₂ −
In a thyristor having an _N2 structure, the impurity concentration of the surface layer of the _P2 region where the gate electrode is provided is reduced by a diffusion method or heat treatment at the deepest vertical position of the _N2 region layer where the cathode electrode is provided. The thyristor is characterized in that the impurity concentration is lower than the impurity concentration of the P ₂ region layer at a junction position that intersects with the P ₂ region layer.

Next, one embodiment of the present invention will be described using FIG. 1, FIG. 3, etc. First, an N-type silicon substrate 1 with a specific resistance of 30 to 40 Ω・cm is chemically polished to a thickness of
The length should be approximately 250〓m. Next, boron is diffused from both sides of the silicon substrate 1 using Bcl ₃ at 1050° C. for 30 minutes.
Thereafter, it was diffused at 1250°C for 30 hours to form 2 P ₁ and 3 P ₂ layers. After removing only the portion that will become the cathode region from one side of the silicon oxide film produced at this time using an optical method, a region that will become the diffusion layer N ₂ 4 is formed at 1250° C. using phosphorus. After this, once the silicon oxide film is completely removed, it is oxidized again at a relatively low temperature of 1000°C to 1150°C for 8 to 10 hours to form an oxide film. At this time, boron is well absorbed into the silicon oxide film, and the very surface of the P ₂ layer becomes a P ^- layer 5 with a low impurity concentration. If the above is insufficient, heat the temperature at around 1000℃ for an additional 10 to 50 minutes.
The effect will be greater if the heat treatment is carried out for a longer period of time. The silicon substrate obtained in this manner was constructed into a device using a conventional method, and an anode electrode 6, a gate electrode 7, and a cathode electrode 8 were provided, and the I _GT was measured.
I _GT of 50〓 ^A was obtained. When oxidized at high temperatures, a diffusion profile as shown in Figure 2 is obtained. That is,
The characteristic curve 10 is drawn for the P ₂ layer, and the characteristic curve 11 is drawn for the N ₂ layer. However, when heat treated at a low temperature, the diffusion profile as shown in Figure 4, that is, each characteristic curve 1
0', the characteristic curve is 11', and the impurity concentration at the surface is lower than the impurity concentration at the point where the PN junction occurs in the figure. Furthermore, I _GT is determined by the point where the forward current flowing through the PN junction in the surface layer matches the forward current flowing through the internal PN junction, so if the P ^- layer is made thicker, I _GT becomes too large.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional thyristor, Fig. 2 is a characteristic diagram showing the diffusion concentration profile of the thyristor of Jukyo, Fig. 3 is a cross-sectional view of a thyristor according to an embodiment of the present invention, and Fig. 4 is a sectional view of a thyristor according to an embodiment of the present invention. FIG. 4 is a characteristic diagram showing a diffusion concentration profile of the thyristor of FIG. 3; In the figure, 1...N-type silicon substrate, 2
...Anode P-type layer, 3...Gate P-type layer, 4...
...Cathode N-type layer, 5...Gate P ^- layer, 6...
Anode electrode, 7...gate electrode, 8...cathode electrode.

Claims (1)

[Claims] 1 In a semiconductor substrate, a first region of one conductivity type, a second region of the opposite conductivity type, a third region of one conductivity type, and a fourth region of the opposite conductivity type are bonded in this order, and the The region No. 3 and the fourth region each have a gate electrode and a main electrode on their main surfaces, and the impurity concentration of the third region in contact with the gate electrode is as follows:
A semiconductor device characterized in that a portion having a main junction with the fourth region is lower than that of the third region.