JPS61287269A - Semiconductor element - Google Patents

Abstract

PURPOSE:To obtain a thyristor having high withstand voltage in a semiconductor element for turning OFF by applying a reverse bias between a gate and a cathode by composing the gate layer of the first epitaxial layer of high impurity density of substrate side and the second epitaxial layer of low impurity density of cathode side, and intruding the cathode to the first layer. CONSTITUTION:An n<-> type layer and a P-type layer having a P<+> type buried gate layer are laminated and epitaxially grown on a P-type semiconductor substrate, and an n<+> type cathode layer is diffused in the P-type layer on the P<+> type buried gate layer. Then, an anode electrode A is formed on the back surface of the substrate, a cathode electrode K is formed on the cathode layer, and a gate electrode G is formed on the P-type layer for surrounding the elec trode K to form a GTO thyristor. In this construction, when a P-type layer is formed of an epitaxial layer grown on the buried gate layer, it is formed of a high impurity density P<->1 type layer and a relatively low impurity density P<->2 from the substrate side, the n<+> type cathode layer is intruded into the P<->1 type layer, thereby obtaining a stable gate and cathode withstand voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor device, such as a GTO (gate turn-off) thyristor, which is turned off by applying a reverse bias between a gate and a button.

B0 Summary of the Invention The present invention provides a G
In semiconductor devices such as TOSIRISK, the gate layer has a two-layer structure with different impurity concentrations, and by forming the gate layer using an epitaxial growth method in which the layer on the cathode surface side has a high resistance, the breakdown voltage at the cathode-emitter junction surface is shifted to the substrate side. It is designed to be stable and to obtain a nine-junction withstand voltage.

C6 Conventional Technology As is well known, the GTO thyristor is a self-extinguishing semiconductor device, which eliminates the need for a commutation circuit required for general thyristors, and its applications are rapidly expanding. To turn off the GTO thyristor, a reverse bias is applied between the gate and cathode of the GTO thyristor to draw a turn-off gate current. The higher this reverse bias voltage (hereinafter referred to as off-gate voltage) is, the more rapidly excess carriers in the P base layer of the GTO thyristor can be drawn out, improving the turn-off ability by reducing the turn-off time and increasing the controllable current. can be achieved.

However, the off-gate voltage is limited by the breakdown voltage of the GTO thyristor's cathode-emitter junction. Therefore, as a GTO thyristor that achieves a large off-gate voltage and improves turn-off characteristics, the cathode-emitter junction is formed by epitaxial growth.
A p-junction structure has been proposed. Examples of this structure are shown in Figures 5 (4) and (B).

Figure (4) shows the case of a buried gate type with a buried gate layer P+, in which a high resistance P layer is formed by epitaxial growth after the formation of the P gate layer, and an n cathode layer is diffused into this epitaxially grown layer P−. form, n −p
The withstand voltage against the off-gate voltage is ensured by the negative cathode-e emitter junction.

Figure (B) shows the case of a surface gate type structure in which the divided metal gate is exposed on the element surface, in which a high-resistance P layer is formed on the P base layer by epitaxial growth, and an n+ cathode layer divided into this P layer is used. Formed by diffusion, n-p-
A cathode-emitter junction is obtained.

Note that in FIGS. 4(4) and (B), A is an anode electrode, K is a cathode electrode, and G is a gate electrode.

With these structures, the breakdown voltage of the cathode-emitter junction, which was conventionally about 20V, can be increased to 100V or more.

Problems that the D0 invention aims to solve: 90TOT by increasing the voltage resistance of the conventional cathode-emitter junction
In thyristors, there is a problem in that breakdown at the exposed junction between the n layer and the p layer limits the ability to increase the breakdown voltage. This breakdown of the exposed junction is a problem even in the buried gate type, but especially in the surface gate type, which has a structure in which many cathodes and emitters are arranged, the actual length of the exposed junction is small, and the junction surface Breakdown is likely to occur, which limits the off-gate voltage of the device despite its large bulk breakdown voltage.

In this way, the breakdown caused by the exposed junction, the breakdown of the junction during breakdown, the decrease in the junction breakdown voltage, and the increase in the leakage current reduce the yield of the device and limit the improvement of the turn-off ability. Ta.

Means and operation for solving the E0 problem In view of the above problems, the present invention provides a semiconductor device in which turn-off is performed by applying a reverse bias between the gate and the cathode, in which the gate layer is formed by epitaxial growth having two layers with different impurity concentrations. of the two layers, the impurity concentration of the first layer on the substrate side is higher than the impurity concentration of the second layer on the cathode side, and the cathode layer can be diffused from the surface of the second layer. The breakdown voltage of the cathode-emitter junction is lowered by increasing the breakdown voltage of the cathode-emitter junction from the substrate side (bulk side). It's on the side.

F. Embodiment FIGS. 1 and 2 are structural diagrams of a GTO thyristor element showing an embodiment of the present invention. FIG. 1 shows a buried gate type GTO thyristor, and FIG. 2 shows an fI! This is a case where each is applied to a plane gate type GTO thyristor.

In FIG. 1, a single P layer formed by epitaxial growth on a buried gate layer P+ is separated into a layer P1- with a low impurity concentration and a layer P2- with an even lower impurity concentration on this layer P1-. , the cathode layer n is formed to a depth that reaches the P layer.

In this way, two epitaxial growth layers p, -, p, - with different impurity concentrations are formed, and the growth layer P forming the bonding surface is lower than the impurity concentration of the growth layer PL- on the substrate (bulk) side.
The impurity concentration of 2″″ is lowered, and the cathode layer n is changed to the layer P.
The cathode-emitter junction is formed by diffusion to a depth reaching the knee, and a cathode-emitter junction is formed between the Pl layer in the element and the P2 layer in the exposed surface area.

With this configuration, n+
The p2-junction has a higher breakdown voltage than the n+++ pl-junction. Therefore, the off-gate voltage can be increased until breakdown of the cathode-emitter junction occurs at the n-Pl- junction (bulk part), and since the n+ pl- junction is not exposed to the surface, the effect of the junction surface can be avoided. I won't be able to receive it anymore. By making the impurity concentration of the P layer and the impurity concentration of the P-type wave diffusion layer sufficiently low, a junction breakdown voltage of 100 V or more can be easily achieved.

Similarly, in the surface gate type GTO thyristor shown in FIG. 2, the epitaxially grown layer P- formed on the base layer P includes a P1'''' layer with a low impurity concentration, and a layer on top of this with a low impurity concentration. The divided cathode layer n+ is formed by diffusion to a depth reaching the Pl layer. This prevents the cathode emitter junction from breaking down on the device surface.
Achieve stable junction breakdown voltage by breaking down in bulk.

Next, a method for manufacturing a GTO thyristor in an example will be described.

Figure 3 shows the manufacturing procedure of the buried gate type GTO thyristor (Figure 1).First, as shown in Figure 3(a), a 70Ω
-yt, 400μ thick n-substrate by diffusing gallium from both sides to obtain a Pn-P structure with a surface sheet resistance of 150, Q/l], depth) μm) Next, as shown in (b), Boron is selectively diffused at a high concentration using the oxide film to form a P buried gate layer. Next, as shown in (C), a single PL layer is formed on the buried gate layer P+ side by epitaxial growth. The impurity concentration of this P layer is 4XLOcm and the thickness is 15 μm.

Next, as shown in (d), a single layer of P2 is formed by epitaxial growth. The impurity concentration of this P2 layer is Pl
The height is also lowered to 2XlOcm and the thickness is 8 μm. Finally, as shown in (e), phosphorus is selectively diffused using an oxide film to form an n+ cathode layer. The surface sheet resistance is 1.0 so that this diffusion depth reaches the Pl layer.
The structure shown in FIG. 1 is obtained through a lifetime control process and an electrode attaching process.

The breakdown voltage of the cathode-emitter junction using this manufacturing method is 110
On the other hand, the breakdown voltage of the n-P2- junction is approximately 200V, which is a sufficiently large withstand voltage.
There is no breakdown at the exposed surface of the nP2-junction.

Figure 4 shows the manufacturing procedure of the surface gate type GTO Zyristor (Figure 2), in which a high resistance P2 layer is formed on the Pl layer, and the divided cathode layer n is made into a P layer in the same way as in Figure 3. Form until reaching.

In addition to forming the single Pl layer and the single P2 layer by epitaxial growth separately, the doping amount may be changed sharply during one epitaxial growth process.

In addition to the effects of the G1 invention, according to the present invention, the gate layer has a two-layer structure with different impurity concentrations, and the impurity concentration of the layer on the cathode side is lowered to lower the breakdown voltage of the cathode-emitter junction surface on the bulk side. Since the structure is made higher than that, the junction surface will not be destroyed due to breakdown even if the protection of the exposed junction part is incomplete, and stable gate and cathode withstand voltage can be secured and maintained on the bulk side. effective.

[Brief explanation of drawings]

Fig. 1 is an element structure diagram showing embodiments of the present invention, Fig. 2 is an element structure diagram showing another embodiment of the invention, Fig. 3 is a manufacturing process diagram of Fig. 1, and Fig. 4 is a diagram showing the manufacturing process of Fig. 1. Manufacturing process diagram in Figure 2, Figure 5 (
4) and FIG. 5(B) are conventional device structure diagrams. 1. P+...buried gate layer, PI r P2-... epitaxial growth layer, n... cathode layer, K...
Cathode breakdown voltage, G...gate electrode, A...anode electrode. Figure 1: Daiko? J's construction crane 2nd figure 2 husband 〉 example - ＾ 9 shame ＾ ＾ , Oυ d - 9 I - ~ 〆1N
Φ Ichino -no Figure 5 (A) Conventional Seikenkyo Figure 5 (B)

Claims (1)

[Claims] In a semiconductor device that performs turn-off by applying a reverse bias between the gate and cathode, the gate layer is an epitaxially grown layer having two layers with different impurity concentrations, and of the two layers, the impurity concentration of the first layer on the substrate side is lower than that of the other layer. The impurity concentration is higher than that of the second layer on the cathode side, and the cathode layer is formed by diffusion from the surface of the second layer, and the diffusion depth is set to reach the first layer. Semiconductor device.