JPS6115367A - Manufacture of gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To improve the reverse withstand voltage at junctions by a method wherein the surface of a P type semiconductor layer is provided with a P type expitaxial layer of low impurity concentration, and an N type impurity is deposited on its surface and then diffused by intrusion into the boundary region of said epitaxial layer. CONSTITUTION:A P type semiconductor layer P2 (gate layer) is formed by diffusing a P type impurity from the surface of an N type semiconductor layer N1. Next, the P type epitaxial layer P<-> of low P type impurity concentration is formed on the surface on this semiconductor layer P2. Then, a deposition layer N<+> is formed by depositing an N type impurity on the surface of this epitaxial layer P<->; thereafter, this impurity is diffused by intrusion to the boundary region between the semiconductor layer P2 and the epitaxial layer P<->. Thereby, an N type semiconductor layer N2 serving as the cathode layer is formed by junction on one surface side of the semiconductor layer P2. Since this manner enables the layer P2 to have the peak of impurity concentration at the part other than the end in the thickness dcirection, the reverse withstand voltage VGR can be increased with the reduction in resistance of the semiconductor layer P2.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing gate turn-off (GTO) thyristors.

For example, the conventional GTO iris transistor has a P-type semiconductor layer P+-N-type semiconductor layer N1, which is an anode layer, as shown in FIG.
, a P-type semiconductor layer Pt as a gate layer, an N-type semiconductor layer N2 as a cathode layer, are provided in this order, an anode electrode A on the surface of the anode layer 21, a gate layer as a cando electrode on the surface of the cathode layer N1. P.

Gate lightning and polar G are provided on the surface. In the GTO thyristor, from the anode layer P to the cathode layer N2
A load current flows toward the semiconductor layers N, , P.

The load current is cut off by passing a gate current between the electrodes in a direction that reverse biases the junction.

Here, if the maximum breaking current of the GTO4) Iristor is (■), then AmaX is given by the following formula.

工AmaX″ 工 grma
) ・(il where G is the turn-off gain, voK is the breakdown voltage (reverse withstand voltage) between the gate canads, R,1 is the internal impedance of the gate cap, F is the maximum turn-off gain - max current, αnpn, αpnp are the GTO thyristor voltages, respectively) This is the DC current amplification base of an NPN transistor and a PNPI-Ranristor when approximated by a two-transistor model.As seen from equation (1), in order to increase the maximum breaking current, voK must be increased or Rg In order to reduce Rg, it is necessary to reduce the resistivity of the gate layer P2, that is, to increase the concentration of P-type impurities in the gate layer P2.By the way, the gate layer P is normally required. Because it is formed by thermally diffusing P-type impurities such as gallium, boron, or aluminum into a silicon substrate, which is an N-type semiconductor with a specific resistance of The distribution is such that the concentration decreases in the depth direction (usually by a complementary error function).Then, the semiconductor 1-N2 has a higher concentration of N such as phosphorus than the surface after the semiconductor layer P is formed. On the other hand, vGK is the impurity concentration Cj of the semiconductor layer P at the junction between the semiconductor layer P and the semiconductor layer N (see FIG. 5).
In order to increase vGk, it is necessary to lower the impurity concentration.

However, in the concentration profile shown in Figure 5, vG
If Cj is lowered to increase k, R6
becomes large.

For this reason, in order to increase IAmaX, it is desirable that the concentration profile of the semiconductor layer P2 has a concentration peak in the thickness direction or in a region excluding both ends, as shown in Figure 6. . The reason is vG
This is because R6 can be made small without making k large.

In order to obtain the concentration profile as shown in FIG. 6, there is a conventional manufacturing method called the out-diffuse method. In this manufacturing method, as shown in FIG. 7, an N-type semiconductor layer N,
In order to diffuse P-type impurities on one side of the (dotted chain line in Figure 7),
After further in-diffusion for a long time (dotted line section in Figure 7), N-type impurities are diffused from the surface side so that the surface concentration of the impurities in the semiconductor layer N becomes the required level, thereby forming the semiconductor layer P2,
This is a method of forming the semiconductor layer N2.

In this method, the P-type impurity can be out-diffused and its surface concentration can be lowered in the forced diffusion step, but in the next step, the N-type impurity is In order to perform diffusion, the semiconductor layer N2
, P-type impurity concentration [Oj at the junction of P2 cannot be made so low, and the magnitude of vGk is about 20 to 25 V at a practical level.

Moreover, in order to obtain the concentration profile shown in FIG. 6, in addition to the conventional out-diffuse method, it is necessary to
After diffusing P-type impurities from both sides of the N-type semiconductor layer N, a P-type semiconductor layer P'''' is formed on one surface by an epitaxial method, and its thickness becomes the final dimension including the semiconductor layer N. The epitaxially grown layer P7 is grown to a certain size, and then an N-type impurity is diffused from the surface of the epitaxially grown layer P7 to a position shallower than the depth of the grown layer P' to form a semiconductor layer N,
There is a way to form. Although such an epitaxial method has the advantage of being able to control the concentration of impurities in the semiconductor P with a large degree of freedom,
There are the following problems. That is, this method allows the thickness of the epitaxially grown jd P- to be considerably large (10 to 2
58 m), otherwise the depletion layer, that is, the junction portion would collide with the dark red part of the semiconductor layer P2, resulting in a high reverse breakdown voltage V. k
I can't hope for it. For this reason, the thickness of the epitaxially grown layer P- becomes large, and therefore the thickness of the entire gate layer becomes large. Further, when forming the semiconductor layer N by a Brenner junction as shown in FIG. 9, the electric field at the surface of the planar junction (indicated by a dotted circle) is the strongest, making it difficult to protect the surface.

This is particularly difficult when several hundred island-like slits are formed in one element in the semiconductor layer N, and it is necessary to provide a field ring or the like. This problem also occurs in the out-diffuse method described above.

Problems to be Solved by Hikama The present invention was developed based on these circumstances, and it reduces the resistance of the gate layer while suppressing its thickness, and also reduces the resistance at the junction of the semiconductor layers P, N, The object of the present invention is to provide a method for manufacturing a GTO thyristor that can increase the reverse breakdown voltage and also weaken the electric field on the surface of the junction when a 4kHz semiconductor is formed by a Brenner junction. .

Means for Solving the Problems The present invention includes a step of diffusing a P-type impurity from the surface of an N-type semiconductor layer N into the layer to form a P-type semiconductor layer P, and a step of forming a P-type semiconductor layer P on the surface of this semiconductor layer 220 A step of forming a P-type epitaxial growth layer with a low concentration of P-type impurities by an epitaxial method, a step of deboding KNW impurities on the surface of this P-type epitaxial growth layer, and a step of depositing the deposited N-type impurities in the above steps. This step includes a step of performing intrusion diffusion to the boundary region between the semiconductor layer P and the Evita Kinoyal growth layer.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 (Al to C'D) is a characteristic diagram of the a-degree distribution of impurities in each step of the method according to the embodiment of the present invention.

In the embodiment, an N-type semiconductor layer N1, for example, a 7 silicon layer I-- with a predetermined resistivity is used, and a P-type impurity such as gallium, boron, or aluminum is added from the - side of the N-type semiconductor layer N1.
For example, surface concentration 1 x 10 to 2 x 10 atm/d% depth 1
Diffusion is performed so that the thickness is 0 to 70 μm, and as a result, a P-type semiconductor layer P, which will become a gate layer, is formed on one side of the semiconductor layer N.
, to obtain the concentration distribution characteristics as shown in FIG. P-type impurities are thermally diffused to the other side of N, thereby forming a P-type semiconductor layer P which is an anode layer.
1 may be formed simultaneously. Next, a low concentration of P-type impurity is epitaxially grown on the surface of the semiconductor layer P by an epitaxial method. P- is several microns thicker than the thickness of the N-type semiconductor layer N, which will be the cathode layer formed as the primary layer.
m thick (see Fig. 1 (Bl)).

Then, an N-type impurity is deposited on the surface of the epitaxial growth layer P- to form a deposition layer N (see Figure 1 (see 01)). region, i.e. semiconductor layer P,
The P-type impurity is forced into the layer diffused into the epitaxially grown Je'r P-.

As a result, the N-type semiconductor layer N2, which is the cathode layer, is bonded to one surface side 1/I of the semiconductor layer P2.

FIG. 1 (Di is the impurity concentration distribution characteristic diagram of GTO+IRISK obtained in this way. As can be seen from this figure, the peak of the P-type impurity concentration of the semiconductor layer P, is the peak of the P-type impurity concentration of the semiconductor layer P! In places other than both ends in the thickness direction, for example near the center, the total amount of P-type impurities in the semiconductor layer P becomes large, and the internal impedance Rg of the semiconductor layer P2 becomes small.
Furthermore, P at the junction between the semiconductor layer P2 and the semiconductor layer N7
The type impurity concentration is quite low.

FIG. 2 is a structural diagram of a GTO thyristor in which a Brenner junction is formed by the method of the present invention, and this GTO thyristor is selected by using a mask on the surface of the epitaxially grown layer P- when forming the semiconductor layer N. Specifically, N-type impurities were deposited and then intrusion-diffused. AA' line, BB' line in Fig. 2,
The impurity concentration distribution along the c-c' line is shown in Figure 1 (D
), Figure 3 [A1, Figure 3 (Bl).

Next, a specific example of the method of the present invention will be explained.

A 100Ω・- N type 7 silicon wafer is used as the semiconductor layer N.

using GaGe as a diffusion source and 120
Ga is diffused into the wafer at 0''C for 18 hours by porridge scattering, thereby bonding and forming a semiconductor layer P on the surface of the semiconductor layer N2.At this time, the surface concentration of Ga is 5x I.
Q+? atn/cr/l. Next, the surface of the semiconductor layer P is coated with a resistivity of 2o by an epitaxial method.
A P-type epitaxial growth layer P- with a thickness of 15 μm was formed, and then phosphorus was selectively deposited onto the surface of the growth layer P- using a mask made of a silicon oxide film. The diffusion conditions at this time were that poc17 was used as the diffusion source, the temperature was 1200° C., and the time was 10 minutes. In addition, the surface concentration of phosphorus is approximately I x 1.0” atm/(y/
It was l.

Furthermore, after removing the phosphorus glass layer, it was heated at 120°C in an oxidizing atmosphere.
Intrusion diffusion of phosphorus was performed at 0'C for 7 hours to form a GTOe iristor with a planar junction as shown in FIG. When the reverse breakdown voltage VGk of this GTO thyristor was measured, it was 70 to 72V. This is more than twice the vGk obtained by the conventional out-diffuse method.

Effects of the Invention As described above, the present invention forms a P-type epitaxial growth layer with low P-type impurity *#[ on the surface of a P-type semiconductor layer p, and forms an N-type impurity on the surface of this epitaxial growth layer. Deposit the N-type impurity into the semiconductor layers P and P.
The boundary between the type of Ebi-taki and the 7-year growth layer is 'E〒Suppressed 1. We are trying to spread the word.

Therefore, according to the present invention, the P-type semiconductor layer P2 has a peak of impurity concentration at a location other than the end portion in the thickness direction.
Reverse breakdown voltage ■ while reducing the resistance of the semiconductor layer P2. k can be increased, thereby increasing the maximum breaking current. Since the N-type impurity is deposited and then forced diffusion is performed, the thickness of the epitaxial growth layer can be reduced, and the N-type impurity is forced into the boundary region.
There is no need to increase the thickness of the gate layer. Since the semiconductor layer Pt1 and the semiconductor layer N are bonded in the boundary region, the electric field on the surface of the shelf and planar junction where the semiconductor 4N* is formed by the planar junction becomes considerably weaker than that inside. Therefore, since the breakdown of the junction occurs preferentially inside the semiconductor layer N, there is no need to pay special consideration to the formation of field rings when a large number of island-like slits are formed, so that the surface of the planar junction can be protected. It's convenient.

Historically, the junction between the cathode layer and the gate layer is a large-area Zener structure, which improves reliability.

[Brief explanation of drawings]

Figure 1 (Al~Figure 1 (DI) is a characteristic diagram of impurity concentration distribution in each step of the embodiment of the method of the present invention, and Figure 2 is a graph of the gate turn-off thyristor obtained in the embodiment of the method of the present invention. Structural diagram showing a part, Fig. 3 fAl, (Bl
are B-B' of the gate turn-off thyristor in Fig. 2, respectively.
# degree distribution characteristic diagram of impurities along line and c-c' line,
Figure 4 is a structural diagram of a conventional gate turn-off thyristor%
5 to 8 are impurity concentration distribution characteristic diagrams of conventional gate turn-off thyristors, and chain diagram 9 is a structural diagram showing a part of the conventional gate turn-off thyristor. P, P-type semiconductor layer which is an anode layer, N,...N-type semiconductor layer, P,...P-type semiconductor layer which is a gate layer, N
, N-type semiconductor layer which is a cathode layer, A... anode electrode, G... gate electrode, K cathode electrode. Figure 1 <A) Figure 1 (B) Figure 1 (C)
Figure 1 CD) Figure 2 B'! Yapporo Δjo-P! -Toichi Fig. 4 Fig. 5 Fig. 6, Thickness - Western grass - Thick knee F! -za- Figure 9

Claims (1)

[Claims] A gate turn-off thyristor consisting of a P-type semiconductor layer P_1 serving as an anode layer, an N-type semiconductor layer N_1, a P-type semiconductor layer P_2 serving as a gate layer, and an N-type semiconductor layer N_2 serving as a cathode layer in this order. In the manufacturing method, a step of diffusing a P-type impurity from the surface of the N-type semiconductor layer N_2 into the N-type semiconductor layer N_2 to form a P-type semiconductor layer P_2;
A step of forming a P-type epitaxial growth layer with a low concentration of P-type impurities on the surface of this semiconductor layer P_2 by an epitaxial method, and a step of depositing an N-type impurity on the surface of this P-type epitaxial growth layer. A method for manufacturing a gate turn-off thyristor, comprising the steps of: pushing and diffusing the deposited N-type impurity to a boundary region between the semiconductor layer P_2 and the epitaxial growth layer.