CN113658922A - JBS silicon carbide diode device structure for enhancing reliability and manufacturing method - Google Patents
JBS silicon carbide diode device structure for enhancing reliability and manufacturing method Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
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Abstract
The invention provides a JBS silicon carbide diode device structure for enhancing reliability and a manufacturing method thereof, wherein the JBS silicon carbide diode device structure comprises a silicon carbide substrate, a plurality of epitaxial layers, a front electrode, a barrier layer, an N-type silicon atomic layer, a P-type diffusion region, a P-type voltage division ring, an N-type stop ring, a composite terminal passivation layer, an ohmic contact layer and a back electrode; the double-layer silicon carbide epitaxial layer with the isolation buffer layer is formed, so that the defects of a silicon carbide substrate are reduced, and the yield and the reliability of products are improved; the N-type stop ring can effectively stop leakage current generated by a leakage channel, and is beneficial to reducing the occurrence of large leakage amount at the edge of a device; through the N-type silicon atomic layer, the N-type silicon atomic layer and the metal form a silicon-based barrier alloy layer, high barrier caused by the silicon carbide alloy layer is avoided, the barrier height during forward conduction is reduced, the forward opening voltage VF of the JBS silicon carbide diode is greatly reduced, the opening loss of the diode is reduced, and the system reliability is improved.
Description
Technical Field
The invention relates to the technical field of JBS silicon carbide diode structure design, in particular to a JBS silicon carbide diode device structure for enhancing reliability and a manufacturing method thereof.
Background
Since SiC (silicon carbide) has a band gap of 3 times that of silicon atoms, a high breakdown field strength (0.8E 16-3E 16V/cm) of 10 times that of Si, and a high thermal conductivity (4.9W/cmK) of about 3.2 times that of Si, it is also called a wide band gap semiconductor material, and is called a third-generation semiconductor material in the industry, and can normally exhibit device performance in a high-temperature, high-power, and high-frequency operating environment. Therefore, the third generation semiconductor-SIC (silicon carbide) is an ideal semiconductor material for manufacturing high-temperature, high-frequency, radiation-resistant and high-power electronic devices due to its characteristics such as high forbidden band width, high blocking voltage and high thermal conductivity.
At present, common planar diodes and JBS diodes exist in the market, and the common planar diodes are widely applied to the field of direct-current low-voltage large current due to the fact that forward voltage is reduced, power is low, switching speed is high. However, the low voltage drop and low power consumption of the conventional planar diode are based on the low barrier. Lower barrier heights increase device reverse leakage current and lower peak operating temperatures.
The JBS diode is different from a common planar diode in that the JBS integrates a plurality of comb-shaped P-type diffusion regions in an N-drift region of the common planar diode. The current path between adjacent P-type regions is designed to ensure that it is not pinched off at zero and positive bias, allowing forward current to flow from the anode to the cathode of the device through the inter-gate current path. At reverse bias, when the reverse bias exceeds a certain voltage, adjacent junction depletion regions overlap, causing the depletion layer to punch through. The depletion layer will form a barrier in the channel after punch-through and spread the depletion layer towards the N-substrate. Therefore, the barrier layer shields the influence of the external voltage on the barrier, prevents the barrier from lowering, reduces reverse leakage current and improves the withstand voltage of the device.
The prior Chinese patent with publication number CN112289848A discloses a super junction JBS diode with low power consumption and high performance and a manufacturing method thereof. The super junction JBS diode with low power consumption and high performance is manufactured by using the traditional silicon-based process technology, and the manufacturing cost is low; the P heavily doped column region and the N column drift region which have the characteristics of large area, high concentration and large junction depth are adopted, so that the forward on-resistance is reduced; forming super junction, and realizing good reverse blocking characteristic by optimizing electric field distribution; by optimizing the parameters of the super junction, higher blocking withstand voltage can be realized, and the on-state power consumption and the off-state power consumption of the device are reduced.
The inventor considers that the JBS diode in the prior art is easily affected by substrate defects and interface instability, so that the reliability of the device is poor, and when the silicon carbide device works in a reverse direction, particularly under a high-temperature condition, when the surface charge on an oxide layer is enough to cause a larger leakage channel in an n-type semiconductor, the problem that the leakage at the edge of the device is large easily occurs, and the improvement is needed.
Disclosure of Invention
In view of the deficiencies in the prior art, it is an object of the present invention to provide a JBS silicon carbide diode device structure and method of fabrication for enhanced reliability.
The JBS silicon carbide diode device structure for enhancing reliability comprises a silicon carbide substrate, a plurality of epitaxial layers, a front electrode, a barrier layer, an N-type silicon atomic layer, a P-type diffusion region, a P-type voltage division ring, an N-type stop ring, a composite terminal passivation layer, an ohmic contact layer and a back electrode; the back electrode, the ohmic contact layer and the silicon carbide substrate are sequentially overlapped from bottom to top, the multilayer epitaxial layer is arranged above the silicon carbide substrate, the P-type diffusion area, the P-type voltage division ring and the N-type stop ring are all arranged in the epitaxial layer on the uppermost layer, the P-type diffusion area is arranged in the middle of the epitaxial layer on the uppermost layer, the P-type voltage division ring is arranged on the outer side of the P-type diffusion area, and the N-type stop ring is respectively provided with one or more groups on the inner side and the outer side of the P-type voltage division ring; the barrier layer and the front electrode are sequentially stacked on the multilayer epitaxial layer from bottom to top, the N-type silicon atomic layer is arranged in the barrier layer, the composite terminal passivation layer is arranged on the multilayer epitaxial layer, and the composite terminal passivation layer partially surrounds the front electrode and partially exposes the upper surface of the front electrode.
Preferably, the composite terminal passivation layer comprises a silicon dioxide layer, a silicon nitride layer and a polyimide layer, the silicon dioxide layer, the silicon nitride layer and the polyimide layer are sequentially stacked on the multilayer epitaxial layer from bottom to top, and the silicon dioxide layer is located below the front electrode.
Preferably, the silicon nitride layer and the polyimide layer both cover the edge of the upper surface of the front electrode.
Preferably, the multilayer epitaxial layer includes isolation buffer layer, first epitaxial layer and second epitaxial layer, isolation buffer layer, first epitaxial layer and second epitaxial layer three from up stack in proper order down on the carborundum substrate.
Preferably, the isolation buffer layer comprises N-type silicon carbide conductive material, the thickness is between 0.5um and 1.5um, and the resistivity is 1016-1017In the meantime.
Preferably, both the first epitaxial layer and the second epitaxial layer comprise an N-type silicon carbide conductive material; the thickness of the first epitaxial layer is between 0.5um and 5um, and the resistivity of the first epitaxial layer is 1016-1017To (c) to (d); the thickness of the second epitaxial layer is between 2um to 50um, the resistivity of the second epitaxial layer is at 10um15-1016In the meantime.
According to the invention, the manufacturing method of the JBS silicon carbide diode device for enhancing the reliability comprises the following steps: s1, preparing the silicon carbide substrate, and growing an isolation buffer layer on the upper surface of the silicon carbide substrate; s2, depositing for two times or more times on the upper surface of the isolation buffer layer to form a multilayer epitaxial layer; s3, generating a silicon dioxide protective layer on the outer surface of the uppermost layer of the multi-layer epitaxial layer through deposition, etching through a photoresist coating, exposing and developing process to form an N-type area window, and then forming an N-type stop ring through multiple N-ion implantation; s4, removing the silicon dioxide protective layer and drying; s5, generating a silicon dioxide protective layer on the outer surface of the silicon carbide epitaxial layer on the uppermost layer through deposition, carrying out etching treatment through a coating, exposing and developing process of photoresist to form a P-type voltage division ring window and a P-type diffusion region window in the active region, and then forming a P-type voltage division ring and a P-type diffusion region through multiple times of P ion implantation; s6, removing the silicon dioxide protective layer and drying; s7, depositing a carbon film in a sputtering or PR glue coating mode, then carrying out high-temperature annealing activation, and then removing the carbon film; s8, growing a silicon dioxide layer by thermal oxidation above the uppermost silicon carbide epitaxial layer, and S9, etching the silicon dioxide layer by a coating, exposing and developing process of photoresist to form an electrode window; s10, depositing Si material above the multilayer epitaxial layer by adopting an atomic layer deposition process or a molecular beam epitaxy process to form an N-type silicon atomic layer; s11, etching through a coating, exposing and developing process of the photoresist to enable the N-type silicon atomic layer to cover the active region and avoid the P-type diffusion region; s12, depositing metal at the electrode window to form the barrier layer; s13, depositing metal or composite metal on the barrier layer, and etching by the coating, exposure and development process of photoresist to form the front electrode; s14, depositing a silicon nitride layer and a polyimide layer above the silicon dioxide layer in sequence, and etching by a coating, exposing and developing process of photoresist to expose partial area on the top of the front electrode; s15, thinning the thickness of the silicon carbide substrate to 100-300 um through grinding; s16, depositing metal nickel on the back of the silicon carbide substrate to form the ohmic contact layer, and performing laser annealing; and S17, depositing metal or composite metal on the back of the ohmic contact layer to form a back electrode.
Preferably, for step S3, the N-type ion implantation is performed by nitrogen ions, the implantation temperature is 300-700 ℃, and the implantation energy is 300-600 kev.
Preferably, for step S5, the P-type ion implantation is AL ion or boron ion, the implantation temperature is 300-.
Preferably, for step S8, the hot oxygen temperature is between 1300-2000 degrees and the oxidation thickness is 10-1000 angstroms.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the invention, through the double-layer silicon carbide epitaxy with the barrier buffer layer, the defect of the silicon carbide substrate is reduced and extends to the silicon carbide epitaxy during homoepitaxy, and the defect of the silicon carbide substrate is reduced, so that the yield and the reliability of the product are improved; the N-type stop ring can effectively stop leakage current generated by a leakage channel, so that the phenomenon of large leakage amount at the edge of a device is reduced;
2. according to the JBS silicon carbide diode, the thin N-type silicon atomic layer is deposited on the surface of the second epitaxial layer, so that the N-type silicon atomic layer and metal form a silicon-based barrier alloy layer, a high barrier caused by the silicon carbide alloy layer is avoided, the barrier height during forward conduction can be effectively reduced, the forward opening voltage VF of the JBS silicon carbide diode is greatly reduced, the opening loss of the diode is reduced, and the system reliability is improved;
3. according to the invention, a multilayer composite terminal passivation layer structure is formed by the silicon dioxide layer, the silicon nitride layer and the polyimide layer, so that the overall protection effect on the terminal is improved; the problem of large stress among different films and the problem of unmatched expansion coefficient with a metal layer material are solved, the internal stress among the films is reduced, the packaging resistance of a product is improved, the core breaking rate in the wafer processing and packaging processes is reduced, and the reliability of a device is enhanced.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic layer structure diagram of an overall cross section of a JBS silicon carbide diode embodying the invention;
fig. 2 is a flow chart of a method for fabricating a JBS silicon carbide diode according to the present invention.
Shown in the figure:
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 1, the JBS silicon carbide diode device structure for enhancing reliability according to the present invention includes a silicon carbide substrate 1, a multi-layer epitaxial layer 98, a front electrode 70, a barrier layer 40, an N-type silicon atomic layer 90, a P-type diffusion region 10, a P-type grading ring 20, an N-type cut-off ring 30, a composite passivation layer 99, an ohmic contact layer 100, and a back electrode 110.
As shown in fig. 1, the back electrode 110, the ohmic contact layer 100 and the silicon carbide substrate 1 are stacked in sequence from bottom to top. The silicon carbide substrate 1 is a layer structure made of an N-type conductive material, and the thickness of the silicon carbide substrate 1 is 200-400um, preferably 200 um. The ohmic contact layer 100 is formed by depositing metallic nickel on the back surface of the silicon carbide substrate 1, and the thickness of the ohmic contact layer 100 is between 50nm and 1000nm, preferably 1000 nm. The back electrode 110 is formed by depositing a metal or a composite metal on the back of the ohmic contact layer 100, the back electrode 110 includes, but is not limited to, an alloy layer formed by combining a titanium metal layer, a nickel metal layer, a silver metal layer, and a continuous multi-layer metal, and the thickness of the back electrode 110 is between 1-10um, preferably 5 um.
As shown in fig. 1, the multilayer epitaxial layer 98 includes an isolation buffer layer 11, a first epitaxial layer 12 and a second epitaxial layer 13, the isolation buffer layer 11 is grown on the upper surface of the silicon carbide substrate 1, the isolation buffer layer 11 is an N-type silicon carbide conductive material layer, and the thickness of the isolation buffer layer 11 is between 0.5um and 1.5um, preferably 1 um; resistivity of 1016-1017In the meantime. The first epitaxial layer 12 and the second epitaxial layer 13 grow on the upper surface of the isolation buffer layer 11 from bottom to top in sequence, and the first epitaxial layer 12 and the second epitaxial layer 13 are both made of N-type silicon carbide conductive materials.
The thickness of the first epitaxial layer 12 is between 0.5um and 5um, preferably 5um, and the first epitaxial layer12 has a resistivity of 1016-1017In the meantime. The thickness of the second epitaxial layer 13 is between 2um and 50um, preferably 20um, and the resistivity of the second epitaxial layer 13 is 1015-1016In the meantime. The use has the multilayer epitaxial layer 98 of keeping apart buffer layer 11, first epitaxial layer 12 and second epitaxial layer 13, can reduce carborundum substrate 1 defect and extend to the carborundum epitaxial layer when homoepitaxy, has reduced carborundum substrate 1's defect, has promoted the yields and the reliability of product.
P type diffusion zone 10, P type partial pressure ring 20 and N type stop ring 30 three all install the upside at second epitaxial layer 13, P type diffusion zone 10 inlays at the equidistant symmetry in middle part of second epitaxial layer 13 and establishes and installs six groups, P type partial pressure ring 20 installs five through ion implantation concentric interval in second epitaxial layer 13, and five P type partial pressure rings 20 all are located the outside of P type diffusion zone 10, N type stop ring 30 inlays through ion implantation and establishes on second epitaxial layer 13 and installs two, two N types are by lieing in the inboard and the outside of five P type partial pressure rings 20 respectively, and two N type stop rings 30 all are concentric with five P type partial pressure rings 20. At the N type stop ring 30 of second epitaxial layer 13 outermost side, the oxide layer edge that can the depletion layer outside acts as the electric leakage passageway and stops the effect, can effectually block the electric leakage that the electric leakage passageway produced to the damage of the P type partial pressure ring 20 that leads to under the multiple circumstances can be effectual reduced.
The barrier layer 40 is a schottky barrier layer and the barrier layer 40 is grown by deposition on the middle of the top wall of the second epitaxial layer 13. the barrier layer 40 includes, but is not limited to, a titanium layer, a nickel layer, a molybdenum layer, a platinum layer, a chromium layer, and an alloy layer. The front electrode 70 is grown by deposition over the schottky barrier layer 40. the front electrode 70 includes, but is not limited to, a layer of titanium, nickel, molybdenum, platinum, chromium, and alloy, and the front electrode 70 has a thickness of between 1-10um, preferably 5 um. The N-type silicon atomic layer 90 has a thickness of 50-300nm and a resistivity of 1017-1018Seven N-type silicon atomic layers 90 are embedded in the barrier layer 40, the seven N-type silicon atomic layers 90 are all in contact with the second epitaxial layer 13, and the seven N-type silicon atomic layers 90 are all kept away from the P-type diffusion region 10.
Through depositing the thin N-type silicon atom layer 90 on the surface of the second epitaxial layer 13, the N-type silicon atom layer 90 and metal form a silicon-based barrier alloy layer, a high barrier caused by a silicon carbide alloy layer is avoided, the barrier height during forward conduction can be effectively reduced, the forward opening voltage VF of the JBS silicon carbide diode is greatly reduced, the opening loss of the diode is reduced, and the system reliability is improved.
The composite terminal passivation layer 99 includes a silicon dioxide layer 50, a silicon nitride layer 60, and a polyimide layer 80, the silicon dioxide layer 50, the silicon nitride layer 60, and the polyimide layer 80 are sequentially stacked from bottom to top on the upper surface of the second epitaxial layer 13, and the composite terminal passivation layer 99 partially surrounds the front electrode 70 and exposes a part of the upper surface of the front electrode 70. The silicon dioxide layer 50 is between 10-1000 angstroms thick, preferably 1000 angstroms thick. The silicon nitride layer 60 and the polyimide layer 80 both cover the edge portion of the front electrode 70, and the thickness of the silicon nitride layer 60 is between 1000-10000 angstroms, preferably 5000 angstroms; the thickness of the polyimide layer 80 is between 1um and 5um, preferably 3 um.
The composite terminal passivation layer 99 formed by the silicon dioxide layer 50, the silicon nitride layer 60 and the polyimide layer 80 surrounds the front electrode 70, so that the overall protection degree of the terminal is improved, the problems of large stress existing among different film layers and unmatched expansion coefficients of metal layer materials are solved, the internal stress among the film layers is reduced, the anti-packaging capacity of a product is improved, the core breaking rate in the wafer processing and packaging processes is reduced, and the reliability of a device is enhanced.
As shown in fig. 2, the method for manufacturing a JBS silicon carbide diode device for enhancing reliability according to the present invention includes the above-mentioned JBS silicon carbide diode device structure for enhancing reliability, and the manufacturing method includes the following steps:
s1, forming the isolation buffer layer 11: a silicon carbide substrate 1 is prepared, and an isolation buffer layer 11 is grown on the upper surface of the silicon carbide substrate 1, the isolation buffer layer 11 having a thickness of 1 um.
S2, generating a silicon carbide epitaxial layer: depositing a first epitaxial layer 12 and a second epitaxial layer 13 on the upper surface of the isolation buffer layer 11 for two times; the thickness of the first epitaxial layer 12 is 5um and the thickness of the second epitaxial layer 13 is 20 um.
S3, forming the N-type cutoff ring 30: and generating a silicon dioxide protective layer on the outer surface of the second epitaxial layer 13 by deposition, wherein the thickness of the silicon dioxide protective layer is between 1 and 2 um. Etching by a coating, exposing and developing process of photoresist to form an N-type area window, and then forming an N-type stop ring 30 by multiple N-ion implantation; the N-type ion implantation is nitrogen ion, the implantation temperature is 300-700 ℃, and the implantation energy is 300-600 kev.
S4, removing the silicon dioxide protective layer: and removing the silicon dioxide protective layer and drying, cleaning by using a cleaning solution after removing the silicon dioxide protective layer, and repeatedly cleaning by using deionized water, blow-drying by using nitrogen, drying and the like.
S5, forming the P-type voltage division ring 20 and the P-type diffusion region 10: and generating a silicon dioxide protective layer on the outer surface of the second epitaxial layer 13 by deposition, wherein the thickness of the silicon dioxide protective layer is between 1 and 2 um. Etching by a photoresist coating, exposing and developing process to form a P-type voltage division ring window and a P-type diffusion region 10 window in the active region, and then forming a P-type voltage division ring 20 and a P-type diffusion region 10 by multiple times of P ion implantation; the P-type ion implantation is Al ion or boron ion, the implantation temperature is 300-.
S6, removing the silicon dioxide protective layer: and removing the silicon dioxide protective layer and drying, cleaning by using a cleaning solution after removing the silicon dioxide protective layer, and repeatedly cleaning by using deionized water, blow-drying by using nitrogen, drying and the like.
S7, high-temperature annealing activation: depositing a carbon film by sputtering or coating PR glue, wherein the thickness of the carbon film is 10-500nm, then performing high-temperature annealing activation at the temperature of 1300-2000 ℃, using inert gas as protective gas, and then removing the carbon film;
s8, growing the silicon dioxide layer 50: and performing thermal oxygen growth on the silicon carbide epitaxial layer 50 positioned on the uppermost layer, wherein the thermal oxygen temperature is between 1300 ℃ and 2000 ℃, and the oxidation thickness is 10-1000 angstroms.
S9, forming an electrode window: the silicon dioxide layer 50 is etched by a coating, exposing and developing process of a photoresist to form an electrode window.
S10, forming an N-type silicon atomic layer 90: an atomic layer deposition process or a molecular beam epitaxy process is used to deposit a Si material over the multilayer epitaxial layer 98 to form an N-type silicon atomic layer 90.
S11, etching through a photoresist coating, exposing and developing process to make the N-type silicon atomic layer 90 cover the active region and avoid the P-type diffusion region 10.
S12, growth barrier layer 40: and depositing a metal at the electrode window to form a barrier layer 40, wherein the temperature of the deposited metal and the N-type silicon atomic layer 90 is 500-600 ℃.
S13, growth front electrode 70: depositing metal or composite metal on the schottky barrier layer 40, and etching by a coating, exposing and developing process of photoresist to form a front electrode 70; the front electrode 70 has a thickness of between 1-10 um.
S14, growing silicon nitride layer 60 and polyimide layer 80: depositing a silicon nitride layer 60 and a polyimide layer 80 in sequence above the silicon dioxide layer 50, and etching by a coating, exposing and developing process of photoresist to expose a partial area on the top of the front electrode 70; the thickness of the silicon nitride layer 60 is between 1000-10000 angstrom, and the thickness of the polyimide layer 80 is between 1um-5 um.
S15, grinding silicon carbide substrate 1: the thickness of the silicon carbide substrate 1 is thinned to 100um to 300um by grinding.
S16, forming the ohmic contact layer 100: and depositing metal nickel on the back of the silicon carbide substrate 1 to form the ohmic contact layer 100, wherein the thickness of the ohmic contact layer 100 is between 50nm and 1000nm, and annealing by using laser.
S17, forming the back electrode 110: and depositing metal or composite metal on the back surface of the ohmic contact layer 100 to form a back electrode 110, wherein the thickness of the back electrode 110 is between 1 and 10 um.
Principle of operation
In the work, workers sequentially generate an isolation buffer layer 11, a first epitaxial layer 12 and a second epitaxial layer 13, form an N-type stop ring 30, remove a silicon dioxide protective layer, form a P-type protection ring and a P-type diffusion region 10, remove the silicon dioxide protective layer, activate by high-temperature annealing, grow a silicon dioxide layer 50, form an electrode window, form an N-type silicon atomic layer 90, etch, grow a barrier layer 40, grow a front electrode 70, grow a silicon nitride layer 60 and a polyimide layer 80, grind a silicon carbide substrate 1, form an ohmic contact layer 100, form a back electrode 110 and the like to manufacture a double-layer silicon carbide epitaxial layer with the isolation buffer layer 11, and arrange the N-type stop ring 30 in the second epitaxial layer 13, so that the defects of the silicon carbide substrate 1 are reduced, the yield and the reliability of products are improved, and the leakage current generated by a leakage channel can be effectively cut off, and damage to the P-type grading ring 20 caused in various situations can be effectively prevented.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. A JBS silicon carbide diode device structure for enhancing reliability is characterized by comprising a silicon carbide substrate (1), a multilayer epitaxial layer (98), a front electrode (70), a barrier layer (40), an N-type silicon atomic layer (90), a P-type diffusion region (10), a P-type voltage division ring (20), an N-type stop ring (30), a composite terminal passivation layer (99), an ohmic contact layer (100) and a back electrode (110);
the back electrode (110), the ohmic contact layer (100) and the silicon carbide substrate (1) are sequentially stacked from bottom to top, the multilayer epitaxial layer (98) is arranged above the silicon carbide substrate (1), the P-type diffusion area (10), the P-type voltage division ring (20) and the N-type stop ring (30) are all arranged in the epitaxial layer on the top layer, the P-type diffusion area (10) is arranged in the middle of the epitaxial layer on the top layer, the P-type voltage division ring (20) is arranged on the outer side of the P-type diffusion area (10), and the N-type stop ring (30) is respectively provided with one or more groups on the inner side and the outer side of the P-type voltage division ring (20); the barrier layer (40) and the front electrode (70) are sequentially stacked on the multilayer S3 epitaxial layer (98) from bottom to top, the N-type silicon atomic layer (90) is arranged in the barrier layer (40), the composite terminal passivation layer (99) is arranged on the multilayer epitaxial layer (98), and the composite terminal passivation layer (99) semi-surrounds the front electrode (70) and partially exposes the upper surface of the front electrode (70).
2. The JBS silicon carbide diode device structure for enhanced reliability of claim 1, wherein the composite termination passivation layer (99) comprises a silicon dioxide layer (50), a silicon nitride layer (60), and a polyimide layer (80), the silicon dioxide layer (50), the silicon nitride layer (60), and the polyimide layer (80) are sequentially stacked from bottom to top on a multi-layer epitaxial layer (98), and the silicon dioxide layer (50) is located below the front electrode (70).
3. The JBS silicon carbide diode device structure for enhanced reliability of claim 2, wherein the silicon nitride layer (60) and the polyimide layer (80) both cover edges of the upper surface of the front side electrode (70).
4. The JBS silicon carbide diode device structure for enhanced reliability of claim 1, wherein the multi-layer epitaxial layer (98) comprises an isolation buffer layer (11), a first epitaxial layer (12) and a second epitaxial layer (13), and the isolation buffer layer (11), the first epitaxial layer (12) and the second epitaxial layer (13) are sequentially stacked from bottom to top on the silicon carbide substrate (1).
5. The JBS silicon carbide diode device structure for enhanced reliability of claim 4 wherein the isolation buffer layer (11) comprises an N-type silicon carbide conductive material with a thickness between 0.5um and 1.5um and a resistivity of 1016-1017In the meantime.
6. The JBS silicon carbide diode device structure for enhanced reliability of claim 4 wherein the first epitaxial layer (12) and the second epitaxial layer (13) both comprise an N-type silicon carbide conductive material;
the thickness of the first epitaxial layer (12) is between 0.5um and 5um, the resistivity of the first epitaxial layer (12) is 1016-1017To (c) to (d);
the thickness of the second epitaxial layer (13) is between 2um to 50um, the resistivity of the second epitaxial layer (13) is at 10um15-1016In the meantime.
7. A method of fabricating a JBS silicon carbide diode device for enhanced reliability, comprising the JBS silicon carbide diode device structure for enhanced reliability of any of claims 1-6, the method comprising the steps of:
s1, preparing the silicon carbide substrate (1), and growing an isolation buffer layer (11) on the upper surface of the silicon carbide substrate (1);
s2, depositing twice or more times on the upper surface of the isolation buffer layer (11) to form a multi-layer epitaxial layer (98);
s3, generating a silicon dioxide protective layer on the outer surface of the uppermost layer of the multilayer epitaxial layer (98) through deposition, etching through a photoresist coating, exposing and developing process to form an N-type area window, and then forming an N-type stop ring (30) through multiple N-ion implantation;
s4, removing the silicon dioxide protective layer and drying;
s5, generating a silicon dioxide protective layer on the outer surface of the silicon carbide epitaxial layer on the uppermost layer through deposition, carrying out etching treatment through a coating, exposing and developing process of photoresist to form a P-type voltage division ring window and a P-type diffusion region (10) window in an active region, and then forming a P-type voltage division ring (20) and a P-type diffusion region (10) through multiple times of P ion implantation;
s6, removing the silicon dioxide protective layer and drying;
s7, depositing a carbon film in a sputtering or PR glue coating mode, then carrying out high-temperature annealing activation, and then removing the carbon film;
s8, carrying out thermal oxygen growth of a silicon dioxide layer (50) above the uppermost silicon carbide epitaxial layer,
s9, etching the silicon dioxide layer (50) through a coating, exposing and developing process of photoresist to form an electrode window;
s10, depositing Si material above the multilayer epitaxial layer (98) by adopting an atomic layer deposition process or a molecular beam epitaxy process to form an N-type silicon atomic layer (90);
s11, etching is carried out through the coating, exposing and developing process of the photoresist, so that the N-type silicon atomic layer (90) covers the active region and avoids the P-type diffusion region (10);
s12, depositing metal at the electrode window to form the barrier layer (40);
s13, depositing metal or composite metal on the barrier layer (40), and etching by a coating, exposing and developing process of photoresist to form the front electrode (70);
s14, depositing a silicon nitride layer (60) and a polyimide layer (80) above the silicon dioxide layer (50) in sequence, and etching by a coating, exposing and developing process of photoresist to expose partial area on the top of the front electrode (70);
s15, thinning the thickness of the silicon carbide substrate (1) to 100um-300um through grinding;
s16, depositing metal nickel on the back of the silicon carbide substrate (1) to form the ohmic contact layer (100), and performing laser annealing;
and S17, depositing metal or composite metal on the back of the ohmic contact layer (100) to form a back electrode (110).
8. The method as claimed in claim 7, wherein for step S3, the N-type ion implantation is nitrogen ion, the implantation temperature is 300-.
9. The method as claimed in claim 7, wherein for step S5, the P-type ion implantation is AL ion or boron ion, the implantation temperature is 300-.
10. The method of claim 7 wherein for step S8, the thermal oxygen temperature is between 1300-2000 degrees and the oxidation thickness is 10-1000 angstroms.
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