JPS58176971A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain planer junction structure which assures stable current amplification factor and minimum gate arc current by applying a forward bias to p-n junction formed by n-emitter layer and p-base layer. CONSTITUTION:A thin gallium deposited layer in high impurity concentration is formed by heat processing of an n type silicon with gallium and a p-base layer 4 is also formed by driving under the oxygen ambient in such a manner that the peak of impurity concentration appears at the depth of about 15-20mum from the surface. Then, a window is opened to a n<+>-emitter layer 3 by the photo etching, phosphorus is deposited by driving, a window is opened by the photo etching keeping a certain distance therefrom, boron is deposited and a p<+> layer 5 is formed by driving. Thereafter, the entire part of SiO2 formed on the surface is removed, a P base region 4 in comparatively low concentration exposed on the surface is compensated, and an n-layer 10 in such a low concentration as resulting in the n type is formed in the thickness of about 0.5mum or more by ion implantion of the arsenic or phorphorus. Finally, an oxide film 9 is formed again on the surface, a window is opened by the photo-etching and electrodes 7, 8 are formed by photo etching after vacuum deposition of electrode of aluminium, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a planar junction structure that has excellent forward and reverse physical properties, stable current amplification factor, and minimum gate firing current.

Conventionally, as an example of the structure of the n emitter layer and the p base layer, which are turned on and turned off by a gate signal, the p
The non-S steep concentration distribution within the base is constructed as follows. In other words, the impurity concentration in Table 1 in the area where the gate electrode is not provided is lowered to 11016ato 1", the internal peak area of 101011BtO! 151" 6 is lowered, and the electrode is A region of high IML concentration is selectively provided at a certain distance from the periphery of the n emitter layer to ensure low resistance contact with the n emitter layer.

For a thyristor that has a 1-1 density distribution, Table (3)
Since the t-field strength at part (C) is lower than that at part (c), the withstand voltage of the n pn imager composed of the n emitter layer and the p base layer is affected by the nine planes because it is broken internally. <<, it seems to be stable.

However, relatively low impurities exposed on the surface
When the p-base layer is formed on top of the p-base layer, if the insulating film is made of ordinary silicon dioxide, the p-base layer becomes depleted due to the presence of positive charges in the film. Cheap. In other words, it means that the reconsolidation current is easy to form on the surface of the p-base layer.In other words, there is an alternate leakage current path through which the current flows on the surface reconsolidation in the pnm layer consisting of the p-base layer and the n-emitter layer. This means that n has been added. This will be expressed equivalently by the resistance Rspm of tfL.

The more positive charges in the film and the lower the impurity level of the surface p base layer, the smaller RI P m becomes, leading to undesirable problems such as a decrease in the current amplification factor hv1 and an increase in the minimum gate ignition current R'zt. It had the disadvantage of causing

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device storage having a planar junction structure with stable dielectric current amplification factor and minimum gate firing current, taking into consideration the compatibility between the planar stabilizing film and the junction structure.

The present invention solves these conventional problems and provides an n-emitter that exhibits excellent characteristics in both forward and reverse directions.

The n-layer or p-layer, which has a p-base junction and is interposed between the n-emitter layer with a high impurity concentration and the 20-layer resistive contact layer, connects the cathode electrode and the cathode electrode at the interface with the insulating film. Sometimes it becomes an accumulation type, and even if the charge in the insulating film on the surface is positive, no surface recombination current flows, the minimum gate firing current is small and stable, and the current amplification factor is high and stable. Yes 1 Also, when the reverse bias is applied, the above ntvit or p layer is depleted, the optical surface electric field is relaxed, and the gate and
The feature is that the breakdown voltage between the cathode and cathode electrodes is higher than that inside.

A first embodiment of the present invention will be described below with reference to FIG.

Figure 1 shows n-base J@31. px transmitter layer 2. n9 emitter layer 3. p base layer 4. P9 layer 51 anode electrode for low resistance fitting 6. Cathode electrode7. Gate 1 8. The insulating film 91 is composed of an n-layer 10 for preventing surface recombination. Figure 2 shows the king II shown in Figure 1! Figure 2(a) shows the impurity concentration distribution in the vertical direction.

(b) and (C) are lines A-A and B-B in Figure 1, respectively.
line.

This is a cross section taken along line C-C.

Next, the operation of the present invention will be explained. In the state where the ridge direction is blocked, the voltage at which the anode electrode 6 is positive and the cathode electrode 7 is negative is ! is applied. In VA, a pn junction consisting of an n-base layer 1 and a p-base layer 4 is mainly formed with a slope, and depletion skins are formed on both sides of this junction.

The operation in this forward direction blocking state is the same as in the vertical direction example. The turn-on operation for transitioning from the forward blocking state to the conducting state will be described. When applying a gate voltage such that gate electrode &8 is positive and cathode electrode 7 is negative while applying the anode/cathode voltage KUA5, positive holes are injected from the po layer 5 to the p base layer 4tA and n''' emitter. Pour the n0 directly under the layer 30, and form the n0 base layer 3 and the p base layer 4.
The injection of electrons from the n+ emitter is promoted by the pnn junction S bias consisting of the n- beta layer 3. p-pace layer 4
゜Npll consisting of a low base layer 1) 7 transistors work.

Subsequently, the electrons injected from the r emitter pass through the p-base layer and into the n-base layer, promoting the injection of holes from the p-emitter layer, and these holes enter the p-base layer. 4
The thyristor is turned on due to positive Al1 action.

In the conventional structure, that is, in the absence of n-10, the p-base layer with a relatively low impurity concentration is exposed, and the p-base layer is depleted on the surface due to positive charges in the 1-layer film. Gate electric &8. Even if the cathode 1 is turned on with a bias voltage of 7, the p base layer 4 becomes a depleted drift region, and the holes injected from the layer 5 are transferred to the p base layer 4. It is difficult to pass through the s of the
) becomes a noble coupling current. A 1V hexagonal recombination current is added to the electron injection from this friend n0 process layer 3, and a gate current of I is required, so that npn )> ILNt increase rate hF11
decreases, and the minimum gate firing torque flL'tt increases.

That is, equivalently, the expression th+recombination current is l5tf'L
The path of the leakage current, Rapm is added due to the resistance.
The structure is as follows. The cause of Rspm is that when the charge in the insulating film is positive, the substrate is p-type, and the lower the impurity concentration, the smaller it is, and the easier it is to form a leaf current path.

nml O jar ft for next plane recombination prevention according to the present invention is 1
Since layer 10 does not become a depletion layer but an accumulation layer in the outer area with iP3 hoe gland 9, the electric current does not flow, and 111, fl
Since the rate hyl is increased in the L increase 411, the minimum gate firing current i5t is small, and these process variations are almost eliminated.

In addition, even in the case of turn-on and constant conduction state, there are no additional gate-cathode Rats.
Since the holes injected from the p-type transistor layer 2 cause positive return and effectively drive the npn transistor, the on-state voltage can be lowered.

Furthermore, when turning off, the gate electrode 8 is negative.

A positive gate voltage is applied to the six-sword electrode 7, but a reverse negative voltage is applied to the pn junction consisting of the tip'' layer 5 and the first layer 1o on the surface. The electric field is relaxed.Inside the pn layer, which consists of an n+ emitter layer 3 and a p base layer 4,
A reverse bias is applied to the junction, and the depletion layer has a low impurity concentration -
However, the electric field strength at that time is higher than that at the surface.

In this way, the reverse breakdown voltage between the gate and cathode is determined internally rather than on the surface, making it more stable than the conventional structure.

Next, the first manufacturing method of the first embodiment of the present invention will be described.

First, nM&silicon with a 50 to 100 Ω flaw is sealed together with gallium in a true wall, and heat treated at high temperature to form a thin gallium devo layer tSX with a high impurity concentration layer. Next, if driven in an oxygen atmosphere, gallium easily passes through the silicon oxide film, which has a large diffusion coefficient, and the surface diffusion rate is 10's to 10" at
A low concentration layer of approximately 0.0 ms is formed, and the impurity concentration peaks (approximately 101?~10").
FF+") is formed at a distance of about 15 to 20 μm from the surface. Next, a 10-emitter mt window is opened using a well-known photoetching method, and phosphorus is deformed and driven to form it. Then, it is covered with an n0 emitter layer. distance ll1t- apart,
A window is opened using known photoetching, and boron is debossed and driven to form 20 layers. After that, the entire surface formed on the red surface is removed with hydrofluoric acid, and the relatively low concentration p base layer exposed on the red surface is compensated for and the low llI of S degree is converted to n-type.
α5 degree N layer is implanted using T ion implantation method using arsenic or phosphorus
Formed with a diameter of μm or more. After IIk, a plated film is formed on the surface, a window is opened by photo-etching at the ninth stage to take out the electrode, and an electrode of aluminum or the like is formed by photo-etching.

Next, the second manufacturing method of the first embodiment of the present invention will be explained. The difference in the first manufacturing method is that n*xo is used to prevent next-plane recombination.
This is the formation method. As explained in the first l1Ii method, a p base layer is formed by diffusion of gallium, and then phosphorus is doped so that the conger crystal concentration is about 101' to 101@lt
oms /3” ty) n MJi low impurity 11tJ
It is to be formed on i110 by epitaxial growth. The manufacturing process is the same as that described in the first manufacturing method, so it will be omitted here. Even if the first method is 2 if the second method is used! ! The n-layer 10 for preventing planar recombination current has a high current amplification factor hFI and a minimum gate firing current of 111 gt.
This is a powerful means to reduce the size of

FIG. 3 shows a second embodiment of the invention. cathode 1 7
is 111 on the p base layer 4! ! It is distinctive in that it covers the edges. In other words, if the gate-cathode connection is biased, the MOB structure consisting of the cathode electrode 7, the p-base layer 4, and the peritoneal membrane 9 will have an electric field effect, and the p-base red will shift to the accumulation m, resulting in a narrow surface. The recombination current is current n
The current amplification factor hFm becomes high, and the minimum gate firing current No. 11 becomes stable at a low value. 9 gate ° Cathode both electrodes 8.7 When the reverse bias is applied to n, the p-space layer 4 capsule surface is easily depleted due to the electric field effect opposite to the above, and the surface voltage y1
- has the characteristic that the stylus pressure is improved by relaxation.

As described above, according to the present invention, when the n emitter layer and the p base layer are formed and removed, j1
When a bias voltage is applied, the p-base layer is not depleted in the iron direction, and therefore there is no surface current, so the current amplification factor hr is
There are no problems such as a decrease in x or an increase in the minimum gate ignition voltage AIga, and it is possible to exhibit extremely stable characteristics with respect to process fluctuations.

In addition, when performing a turn-off operation, a reverse bias voltage is applied to the gate and cathode, but in the present invention, Table 1i
Since two layers extend over the n layer with low impurities and the surface electric field is relaxed, the gate/cathode breakdown voltage on one surface can be made higher than that on the inside, and is stable.

This is mainly turned on by the gate signal.

□ We have explained about thyristors that can be turned off.
The effects of the present invention are not limited to thyristors, but are also effective in transistors. That is, the p-electrode 6 may be used as the collector electrode, and the gate electrode 8 may be used as the base electrode. In this case, the pace electrician is 151 tft.

As described in the present invention for the calling line, there is no reactive leakage current Rn which becomes the surface precious coupling current. It is clear that a transistor with a high current amplification factor and stability can be obtained.

[Brief explanation of drawings]

#! Figure 1 is a cross-sectional view showing the first embodiment of the present invention, Figure 2 is a diagram showing the impurity concentration along the 1-A line, B-B@, and C-C edge markings, Figure 3. FIG. 2 is a sectional view showing a second embodiment of the present invention. l...n-base layer, 2...p emitter layer, 3...
・n emitter layer, 4... p base layer, 5... 20 layers for low resistance contact, 6... anode as pole, 7... cathode electrode, 8... gate electrode, 9... Insulating film, 10.
...N layer for preventing surface recombination.

Claims (1)

[Claims] 1. A second semi-dedicated layer of a second conductivity type is formed by instantaneous contact with the 10,000-square-foot surface of a semiconductor substrate of a first conductivity type; A third semiconductor layer of the 14th electric type with a high impurity concentration is formed, and a first electrode is provided in ohmic contact with the third semiconducting body so as to surround the third semiconductor layer. A fourth semiconductor layer of high impurity concentration of the 224th conductor type is formed in isolation from C1.A second electrode is provided in ohmic contact with the fourth semiconductor layer C1, and a third conductor layer and a fourth conductor layer are formed. The hexagonal part of the nine semiconductor layers intervening in the darkness becomes an accumulation type V (lt
L accent amplification factor is high <, Xfc is minimum gate ignition current is small 6
A semiconductor device characterized by a relatively stable structure, less depletion when reverse biased, and a surface electric field that is lower than the internal electric field. 2. In claim 1, the surface portion of the semiconductor layer located between the third semiconductor layer 1- and the fourth semiconductor layer has the same conductivity type as the third semiconductor layer, and has a lower impurity concentration than the third semiconductor layer. A semiconductor device that is a semiconductor layer. 7F. The semiconductor device according to claim 1, wherein a sixth semiconductor layer having conductive wrinkles is formed adjacent to the other main surface of the C1 sixth semiconductor layer, and a third electrode is in ohmic contact with the sixth semiconductor layer C1. 4. Wait #! In claim 1, a seventh semiconductor layer having a higher impurity concentration than the first conductivity type semiconductor substrate is formed adjacent to the other main surface, and a fourth electrode is in ohmic contact with the seventh semiconductor layer. semiconductor devices.