JPS59195867A - Thyristor - Google Patents

Abstract

PURPOSE:To increase gate trigger currents IGT by forming a gate region surface layer in structure in which a low-concentration P2 layer is held by upper and lower concentration P2 layers. CONSTITUTION:Ga is used and diffused to both surfaces of an N type silicon substrate 1 to form P1, P2 layers 2, 3, a cathode region N2 layer 6 is diffused by using phosphorus, phosphorus is implanted to the whole surface by employing ion implantation and a P<-> layer 4 is formed to a section in the vicinity of the surface layer of the P2 layer 2 through thermal diffusion, boron is used selectively and diffused to shape a P<+> layer 5, and an anode electrode 9, a gate electrode 7 and a cathode electrode 8 are formed. The threshold voltage of a P2-N2 diode formed by the low-concentration P2 layer shaped near the surface and the N2 layer is low, currents flow through a small current region first and arr changed into reactive currents in the small current region, and IGT can be controlled with high accuracy in approximately several muA-1mA.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvement of gate characteristics of a thyristor having a Pl-N, -P2-N, 4# structure.

In conventional thyristors with P1-N and -P2-N structures, impurities such as boron and gallium are diffused at high temperature on both sides of a kN1 type substrate to form 22 Pl layers.
Form two layers.

Considering the Fermi level when a P-type semiconductor and an N-type semiconductor are in contact, in a semiconductor with a high impurity concentration, the position of the Fermi level is closer to the conduction band in an N-type semiconductor, and closer to the conduction band in a P-type semiconductor. Since it approaches the electron band, a P-N junction with high concentration impurities has a contact potential difference of ■ compared to a P-N junction with low-intensity impurities. becomes larger. Therefore, when considering diode forward characteristics, the former combination has a higher forward rising voltage.

In this case, P is inward from both main surfaces of the silicon substrate.
Since the impurity serving as the mold is diffused, the impurity concentration decreases as it goes inward from the surface. Therefore, the impurity concentration of the P region layer near the junction where the cathode region crosses the P2 region layer at the deepest position in the vertical direction is lower than the impurity concentration near the surface of the gate P2 region. Therefore, when a positive voltage is applied to the gate and a negative voltage is applied to the cande, a current begins to flow through the internal PN junction far from the surface layer, and electrons are emitted inward. For this reason, the minority carriers released from N2P2N, ) run risk emitters and RI N2 effectively act as emitter currents, and P, -N, -P2-N2 run risks conduct with a very small gate current, which is a base current. The gate trigger current IGT, which is the lowest gate current required to bring the thyristor into the conducting state, is very small and has a value of less than lOμ8.

In order to reduce the influence of noise, the conventional method of increasing k IGT is to leave a dot-like silicon oxide film in the cathode N2 region using known optical means and diffuse it. However, N is not diffused only in the areas where the oxide film remains in the form of dots, and the 22nd layer of the gate region is exposed on the surface.When an electrode is formed on this later, P2-N2 is connected by the electrode and a short circuit occurs. , a so-called shorted emitter structure was used.

Since the current flowing between the gate and the cathode in this short region flows as a reactive current, 'GT can be increased by the amount of current determined by the short resistance. However, it has been extremely difficult to manufacture IGTs with an IGT of several μA to 1 mA with good reproducibility due to the combination of the precision of the optical method and the diffusion control mill.

Therefore, it is an object of the present invention to provide a method for manufacturing IGT with good reproducibility so that the IGT has a current of several microns to about 1 mA.

In order to solve the above-mentioned drawback, it is better to actively flow a reactive current in the surface layer, so the forward rising voltage vFo of the P2-N2 junction near the surface can be made to be higher than the rising voltage VFO of the internal P2-N2 junction. Low and low is good. However, when 22 layers of low impurity concentration layers are exposed on the surface, the surface layer becomes N due to the diffusion process.
There is a high risk of reversal, which could cause fluctuations in IGT. Therefore, by epitaxial method, ion implantation method, or diffusion method, a high concentration of P is formed in the surface layer of the short region.
Two regions are provided, and the layer immediately below has a lower concentration of P than the surface layer.
Two area layers are provided, and in the layer immediately below, a high concentration P22 area is provided again, and 12 low concentration layers are provided above and below with high concentration P.

It has a structure sandwiched between layers. If arranged like this, P2-
The rising bit pressure of the N2 diode ■Fo is the diode forward characteristic vF1 caused by the low concentration P2 layer and N2 layer sandwiched between the upper and lower layers, and the diode forward characteristic vF2 caused by the 22 layer and the N2 layer in both the upper and lower layers. This produces the same effect as when the two are connected in parallel, and the reactive current flows at the lower vFl, and the IGT is determined by F1 instead of vFo.

That is, the rising voltage V of the P2-N2 diode is generated by the low-level P2 layer and N2 layer provided near the surface. is low, and in the small current ML region, current flows first in this part and no minority carriers are released inside, so it is a reactive current. T can be precisely controlled to about several μA to 1 mA.

Next, one embodiment of the present invention will be described using the drawings.

- First, a Nu silicon substrate 1 with a resistivity of 30 to 40 Ω is chemically polished to a thickness of about 250 μm.6 Next, Got is used on both sides of the silicon substrate 1 to diffuse it at 1250'0.
,, Since a silicon oxide film is formed on the surface of PJiJ', a layer of oxide film is formed using a known optical method. After removing the portion that will become the cathode region N2 layer, phosphorus is removed. to diffuse the N2 layer at 1250°C. Thereafter, ion implantation is used to implant phosphorus into the entire surface and thermal diffusion is performed. In this way, a P layer 4 is produced in a portion close to the surface layer of the 22nd layer. Furthermore, a P+ layer is selectively diffused on the P layer 4 using boron, and the P+ layer is spread on the surface.
Layer 5 is provided. The silicon substrate obtained in this manner was constructed into a device using a conventional method, and an anode electrode 9, a gate electrode 7, and a cathode electrode 8 were provided, and the IGT was measured. IG of about 100μ8
I got T.

Although the case has been described above using ion implantation, a single P layer may be provided as an epitaxial layer, or a single P layer may be provided using a diffusion method.

[Brief explanation of the drawing]

FIG. 1 shows a sectional view of a conventional thyristor, and FIG. 2 shows a sectional view of a thyristor according to the present invention. 1...Silicon substrate, 2...Gate P
Type layer, 3... Anode P type layer, 4...
Goo) P 1st layer, 5...Gate 2nd layer, 6...
Cando N-type layer, 7...Goo 1 cage pole, 8...
...Cand electrode.

Claims (1)

[Claims] A semiconductor substrate of one conductivity type has first and second regions of another conductivity type on both sides, and the surface of the first region is further provided with the -
In a thyristor having a Pl-N1-P, -N structure having a third region of conductivity type, the impurity concentration profile of the first region where the gate electrode is provided is as follows: The concentration is lower than that of the surface layer.
Furthermore, the thyristor is characterized in that the lower layer has a high concentration higher than the low concentration.