JPH0117267B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the gate characteristics of a thyristor having a four-layer structure of P ₁ --N ₁ --P ₂ --N ₂ .

In conventional thyristors with the P ₁ -N ₁ -P ₂ -N ₂ structure, impurities such as boron and gallium are diffused at high temperatures from both sides of the N ₁ type substrate to form the P ₁ P ₂ layer.
P ₁ and P ₂ layers are provided, and an impurity such as phosphorus is further diffused from one side to form an N ₂ layer.

Considering the Fermi level of P-type semiconductors and N-type semiconductors, the higher the impurity concentration, the higher the Fermi level is in the valence band in P-type semiconductors, and in the conduction band in N-type semiconductors, so the contact potential difference V ₀ of the PN junction is P In both cases, as the impurity concentration increases, V ₀ tends to increase. Therefore, when considering a P ₂ - N ₂ diode, assuming that the impurity concentration gradient of the N ₂ layer is almost equal in the horizontal and vertical directions near the surface periphery, the forward rise voltage will be higher if the impurity concentration of the P ₂ layer is higher. V is high.

In this case, since the P-type impurity is diffused inward from both main surfaces of the silicon substrate, the concentration of the diffused impurity decreases as it progresses inward from the surface. Therefore, the impurity concentration of the P 2 region near the junction where the cathode N ₂ region intersects with the P ₂ region at the deepest position in the vertical direction is lower than the impurity concentration near the surface of _the gate P ₂ region. Therefore, when a positive voltage is applied to the gate and a negative voltage is applied to the cathode, current begins to flow through the internal PN junction far from the surface layer, and electrons are emitted inward. For this reason
The electrons, which are minority carriers, emitted from the emitter N ₂ of the N ₂ P ₂ N ₁ transistor effectively act as an emitter current, and the gate current, which is a very small base current, increases P ₁ ―N ₁ ―P ₂ ―N. ₂ thyristors are brought into conduction. Therefore, the gate trigger current (IGT), which is the minimum gate current required to bring the thyristor into conduction, is very small.
It becomes less than 10μA. Conventionally, when forming a cathode region by a diffusion method in order to greatly control IGT, a well-known optical method is used in advance to selectively leave dots on the silicon oxide film to form phosphorus which will become _N2 regions. etc., partially N
There is a region where the gate region does not enter, and this region
The _P2 layer is exposed on the surface. Thereafter, when forming an electrode on this, P ₂ --N ₂ was connected by the electrode and shot, creating a so-called shot emitter structure. Since the current flowing between the gate and the cathode in this short region flows as a reactive current, IGT can be increased by the amount of current determined by the short resistance. However, it has been extremely difficult to manufacture a device with a high reproducibility of several μA to 1 mA due to the combination of the precision of the optical method and the precision of diffusion control.

Therefore, it is an object of the present invention to provide a method for manufacturing IGT with good reproducibility so that the IGT is on the order of several μA to 1 mA.

In order to solve the above drawback and increase the IGT, it is sufficient to actively flow a reactive current through the surface layer, so that the forward rising voltage V ₁ of the P ₂ - N ₂ junction near the surface
should be lower than the rising voltage V ₂ of the internal P ₂ - N ₂ junction. Therefore, for the reasons mentioned above, the impurity concentration of the surface layer of the _P2 region where the gate electrode is provided is reduced to _P2 at the deepest vertical position of the _N2 region layer where the cathode electrode is provided by ion implantation or diffusion method. The impurity concentration is set to be lower than the impurity concentration of the P ₂ region layer at the junction position where it intersects with the region layer. In this way, P ₂ near the surface layer -
The rise voltage of the N ₂ diode is low, and in the low current region, current first flows through this portion, resulting in a reactive current, and no minority carriers are emitted inward. Therefore, IGT can be precisely controlled to about several μA to 1 mA. However, if a junction with a low impurity concentration region is provided in the surface layer, there is a risk that the diode P ₂ -N ₂ will produce a channel waveform in its reverse characteristics. Therefore, in order to avoid this, the junction created by the cathode _N2 layer and the gate _P2 layer is separated from the line exposed on the surface, and the gate _P2 surface has a P type and highly concentrated impurity region P ⁺ By applying the layers, the channels are broken. However, if this continues, a potential difference will occur due to the P layer and the P ^- layer, making it difficult for the surface current to flow.
P ₂ directly from the N ₂ layer directly below the P ⁺ layer without passing through the P ^- layer
One release of minority carriers into the layer occurs, and the IGT becomes small. Therefore, by providing an N-type inversion layer or a buried region directly under the P-type high concentration impurity region, the emission of minority carriers from the _N2 layer through the P ⁺ layer and the P2 layer is eliminated, and only between the ^P- layer and the _N2 layer _. In this case, a reactive current flows, and IGT control can be performed without the channel phenomenon of the P _{2 -N} layer.

Next, one embodiment of the present invention will be described with reference to the drawings. First, an N-type silicon substrate 1 having a specific resistance of 30 to 40 Ω·cm is chemically polished to a thickness of about 250 μm. Next, gallium was diffused from both sides of the silicon substrate 1 using sealed tube diffusion at 1250°C for about 20 hours.
Provide P ₁ (2) P ₂ (3) layers. Oxidize the wafer at high temperature,
After a silicon oxide film is provided and only the portion that will become the cathode region is removed by a known optical method, a region that will become the diffusion layer N ₂ (4) is provided using phosphorus at 1250° C. Similarly, after selectively providing a portion that will become the N-type buried region 10 by ion implantation or diffusion, a shallow N-type layer is provided on the entire surface by ion implantation or diffusion, and diffusion is performed to invert the region. A surface layer 8 which becomes a P ^- region is provided. Furthermore, in the same manner, boron is selectively diffused into the portion that will become the P ⁺ region 9. At this time, the order can be changed by appropriately selecting the impurity concentration and depth.

The silicon wafer obtained in this manner was constructed into a device using a conventional method, and an anode electrode 5, a cathode electrode 6, and a gate electrode 7 were provided, and the IGT was measured.Ion implantation was performed to provide a P ^- layer. IGT can be freely controlled in the range of 1 μA to 1 mA depending on the conditions, and
Good results were obtained with no channel in the reverse waveform of the P ₂ N _two- layer diode.

[Brief explanation of drawings]

FIG. 1 shows a sectional view of a conventional thyristor, and FIG. 2 shows a sectional view of a thyristor according to the present invention. In the figure, 1... silicon substrate, 2...
Anode P-type layer, 3... Gate P-type layer, 4... Cathode N-type layer, 5... Anode electrode, 6... Cathode electrode, 7... Gate electrode, 8... P ^- gate layer, 9... P ⁺ gate layer, 10 . . . N type gate buried layer.

Claims (1)

[Claims] 1. A semi-moving body substrate of one conductivity type, a first impurity region of another conductivity type provided on one main surface of the semi-moving body substrate, and the other conductive region provided on the other main surface of the semiconductor substrate. a second impurity region of the type, a third impurity region of the one conductivity type provided on the one main surface side of the first impurity region, and a third impurity region of the one conductivity type provided on the one main surface side of the first impurity region. a fourth impurity region of the other conductivity type that is provided in contact with the third impurity region and has an impurity concentration lower than an impurity concentration in a region of the first impurity region that is in contact with the third impurity region; a high concentration fifth impurity region of the other conductivity type provided on the one main surface side of the first impurity region in contact with the fourth impurity region and spaced apart from the third impurity region; a sixth impurity region of one conductivity type provided in the first impurity region in contact with the bottom of the fifth impurity region; a gate electrode provided in contact with the fifth impurity region; A thyristor comprising: a first main electrode connected to the third impurity region; and a second main electrode connected to the second impurity region.