JPS62208492A - Storage device - Google Patents

Abstract

PURPOSE:To continuously output the same contents by providing a timing generator which modifies the transmission destination of a lock signal from a down counter to an address counter based on a control signal and transmits a latch release signal to a latch circuit. CONSTITUTION:According to the flag bit of data written at the prescribed address in a storage circuit 29 the address counter stops its jogging, and subsequent n-bit data is set to the down counter 33 to count down based on the clock signal transmitted from the timing generator 27. It transmits a preset pulse (q) to a loop counter 33, causes the loop counter 33 to preset iteration number data outputted from a main storage circuit 29, transmits the clock signal CL2 to the loop counter 33 after outputting the preset pulse (q), and counts down the preset iteration number data. When the iteration number comes to zero, a counted value again jogs. Thus the same data can be continuously outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a storage device, and more particularly to a storage device that can repeatedly output the same data by adding a simple configuration.

[Conventional technology]

Conventional storage devices of this type include those shown in FIGS. 3 and 4, and this conventional example will be explained first. The address counter 1 is applied to the reset terminal 3, and the reset signal hole S1 causes the sicant value to be "0" (Fig. 4 An) 10)
and the clock signal CL supplied to the clock terminal 5
1 is supplied via the control circuit 7 (C1,
11~eL14) Increment the count value (ADZ 1
-ADI4). The cant value is sent to the main memory circuit 9 as address No. 11, and from the main memory circuit 9 data (1
)'r10~1)T14) is output. The control circuit 7 sends a clock signal C to the address counter 1.
In addition to transferring LI, it is also used when repeatedly reading the same data from the main memory circuit 9. That is, when repeatedly reading the same data, the control circuit 7 determines whether or not a pre-specified count value has been reached, and the control circuit 7 determines whether or not the specified count value (for example, point A in FIG. 4) is reached. When the clock signal CLI reaches the address counter 1, the control circuit 7 stops sending the clock signal CLI to the address counter 1 (CL1
4 and later), after sending out the repeat data a pre-specified number of times, the clock signal CL is sent to address counter 1 again.
15 is transferred and the count value (AD15) is incremented. The control circuit 7 needs to discriminate the count value and is composed of a central processing unit, a program ROM, a RAM, etc.

[Problem to be solved by the invention]

In the conventional storage device described above, when outputting the same content continuously, the control circuit 7 controls the address counter 1.
Since it stops the progress of and outputs data continuously,
Although the storage capacity of the main memory circuit 9 can be saved, if the control circuit 7 is composed of a central processing unit, ROM, RAM, etc., the control circuit 7 becomes complicated, and it becomes necessary to write program instructions etc. to the ROM. There was a problem that the device was expensive. Therefore, it is an object of the present invention to provide a storage device capable of continuously outputting the same content with an inexpensive and simple configuration.

[Means, operations, and effects for solving the problem] In the storage device according to the present invention, the increment of the address counter is stopped based on the flag bit of data written to a predetermined address of the storage circuit, and the subsequent n-bit data is downgraded. Set the counter to count down (by the clock signal sent from the timing generator). When the result becomes a constant value, the timing generator is caused to send the clock signal to the address counter again. While the down counter is counting down, the data including the flag bit is latched in the latch circuit, so the same data will be output continuously, and when the clock signal is supplied to the address counter again, the data will be output sequentially. Data that has been written to the address indicated by the incrementing counter value can now be read out. Therefore, according to the present invention, the repeat request flag and the repeat count data can be stored in the memory circuit that stores the data, and there is no need to provide a separate dedicated memory circuit. Moreover, since repeated requests and the like are determined by dedicated hardware, a central processing unit is not required, and the configuration can be simplified and the price can be reduced.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment.
The figure is a timing chart diagram.

The address counter 21 is reset by a reset signal R82 supplied to the reset terminal 23, and the count value r
Become an O.J. In a normal read operation, the timing generator 27 transfers the clock signal CL2 supplied to the clock terminal to the address counter 21, and the count value of the address counter 21 is incremented. address cuff/
The controller 21 sends an m-bit address output to the main memory circuit 29 based on the count value, and the main memory circuit 29 outputs the n-bit data stored at the address designated by the address output. When the least significant bit of the n-bit data output is "0", it is a normal read operation, so (n-1) bits of this n-bit output excluding the most significant bit are sent to the plurality of latch circuits 31. Latch pulse P
While is at low level, (n-1) bits of data are output as they are.

On the other hand, in the case of continuous output of the same content, the main memory circuit 29
"1" is written in the most significant bit of the n-bit data (see M8B at timing C in FIG. 4). Then, the timing generator 27 shifts the latch pulse Pf to high level at the rising edge of timing d, and the queen 1:
C. The data output of the circuit 29 is latched by the latch circuit 31. The timing generator 27 generates rlJ of the most significant bit.
After detecting (M2R), one pulse of the clock signal CI,2 is sent to the address counter 21 (timing d), and the count value of the address counter 21 is incremented by "1".

Since the data of the number of repetitions is stored in this address incremented by "1", the timing generator 27 sends the preset pulse q to the loop counter 33, and the data of the number of repetitions output from the main memory circuit 29 is stored. (n bits)
is preset in the loop counter 33. After outputting the preset pulse q, the timing generator 27 sends the clock signal CL, 2 to the loop counter 33, and counts down the repetition number data preset in the loop counter 33 (from timing e to timing i).
). In this embodiment, the number of repetitions is 7, and two clock pulses are required after the data is output at timing C until the countdown of the repetition data starts.
The repetition data is set to a value that is 2 less than the actual number of repetitions (a value corresponding to the decimal value "5"). timing l
When the preset number of repetitions reaches "0" at the falling edge of the loop counter 33, the tie generator 27
The timing generator 27 sends the control signal CkL to the address counter 21 again (after timing i), and the timing generator 27 starts to send the clock signals C1 and 2 again to the address counter 21 (after timing i), and the count value starts to increment again.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a timing chart of one embodiment, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a timing chart of a conventional example. be. 21...Address counter, 27...
Timing generator, 29... Memory circuit, 31.
... Latch circuit, 33 ... Down counter (loop counter). Agent Patent Attorney Susumu Uchihara C Otsu 2 Figure 1

Claims (1)

[Claims] In a storage device comprising an address counter that sequentially increments a count value based on a clock signal, and a storage circuit that outputs n-bit data stored at an address specified by the count value, the n-bit data a down counter that presets the data, counts down the preset data using a clock signal, and outputs a control signal when the result reaches a constant value; a latch circuit that latches data other than the flag bit among the n-bit data; and a flag. Based on the bit, the destination of the clock signal is changed from the address counter to the down counter, and a latch signal is sent to the latch circuit. Based on the control signal, the destination of the clock signal is changed from the down counter to the address counter, and the latch is released by the latch circuit. A storage device further comprising a timing generator that sends a signal.