JPH05313836A - Data transfer system - Google Patents

Abstract

PURPOSE:To set the timing of a control signal in accordance with the characteristic of each device by optionally changing the timing of the control signal in response to the characteristic of each device. CONSTITUTION:The timing of a control signal is optionally changed in accordance with the characteristic of each device in a data transfer system where the data transfer speed is determined by the timing of the control signal. For instance, a parallel interface circuit 2 provided at the side of a printer is provided with a control means which outputs a busy signal to a computer in the set prescribed timing and a means which optionally changes the timing. In other words, the control means contains a counter 3 allows the output of a busy signal to show that the printer is unable to receive the data before the count value of basic clocks reaches a set level. Meanwhile, the timing changing means contains a latch circuit 5 which latches the set value data received from the printer and outputs these data to the counter 3 as the set value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system in which data transfer between devices is performed based on a control signal created by hardware, and the data transfer rate is determined by the timing of the control signal.

[0002]

2. Description of the Related Art Conventionally, for example, data transfer from a personal computer (hereinafter referred to as "personal computer") to a printer is performed by a strobe (STROBE) signal and a busy (BUSY) signal via a Centronics interface which is an 8-bit parallel interface. Alternatively, a handshake is performed using a control signal such as an ACK (ACKNOWLEDGEMENT) signal.

That is, the strobe signal informs the printer side that the data has been output from the personal computer side, the busy signal informs the personal computer side that the printer is not receiving data due to printing, etc. By informing the PC side that the data reception was completed normally, the data transfer was performed while confirming the status of the other party.

[0004]

However, in such a conventional data transfer method, when the busy or ACK signal is created by hardware instead of software, the timing of the busy and ACK signals BUSY and / ACK (that is, active The pulse width of the period is, for example, as shown in FIG. 5, one kind (in this case, 10 μsec and 2.5 μse).
Since c) is rarely fixed to two types, the user cannot select a busy or ACK signal having a pulse width most suitable for the characteristics (that is, performance) of his or her personal computer or printer. Therefore, the data transfer efficiency from the personal computer to the printer and the printer performance (that is, processing performance)
Was deteriorated and its performance could not be fully brought out.

The present invention has been made in view of the above circumstances, and when data transfer between devices is performed based on a control signal created by hardware, the device is adapted to the characteristics of each device. An object of the present invention is to provide a data transfer method capable of setting the timing of control signals.

[0006]

In order to achieve the above object, according to the present invention, data transfer between devices is performed based on a control signal created by hardware, and the data transfer rate is controlled at the timing of the control signal. In the determined data transfer method, the timing of the control signal is arbitrarily changed according to the characteristics of each device. For example, it is a data transfer method between a computer (in this case, a personal computer) and a printer. Is a busy signal indicating that the printer cannot receive data, and a control means for outputting the busy signal to the computer side to the parallel interface circuit equipped on the printer side at a set predetermined timing. A means provided with variable means for arbitrarily changing the timing set in the control means A. Specifically, the control means is
The variable means has a counter that allows the printer to output a busy signal indicating that the printer cannot receive data until the count value reaches the set value. It has a latch circuit for latching the set value data sent from the central processing unit and outputting it to the counter as the set value.

[0007]

With this configuration, the timing of the busy signal output to the personal computer side can be arbitrarily changed by the set value data sent from the central processing unit on the printer side. The timing of the busy signal can be set according to the characteristics of each of the devices involved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transfer system of the present invention will be described below with reference to the drawings. FIG. 1 shows a block circuit configuration for realizing the data transfer system of the present invention between a personal computer and a printer. Reference numerals 1 and 2 denote an input / output port (that is, a Centronics connector) and an interface circuit of a Centronics interface provided on the printer side. , Its input / output port 1 is connected to the personal computer side through a connection cord, and 8-bit parallel data or strobe signal / STB from the personal computer side (in this case, it becomes active in the L state and has a meaning (that is, valid) Signal is displayed, a bar is displayed next to the signal symbol and a bar is displayed in the figure), and a busy signal BU from the printer side is received.
It is designed to deliver SY and the like.

The interface circuit 2 is constructed as follows, and 3 is a pulse width setting for starting the counting operation at the rising edge of the busy signal BUSY input to the input / output port 1 from the personal computer side. The pulse width setting counter 3 is a basic clock CLOCK generated by a clock generation circuit on the printer side.
When the count value reaches a set value, the carry signal / CARRY that is being output is lowered from H and is set to L for a predetermined period. The set value is set by a set value latch circuit described later. It is a so-called programmable counter that can be arbitrarily changed by the output. A control unit 4 outputs a busy signal BUSY to the personal computer side via the input / output port 1. The control unit 4 falls at the falling edge of the strobe signal / STB input to the input / output port 1 to cause the busy signal BUSY to fall. And carry signal / CARR output from the pulse width setting counter 3
When Y becomes L, the busy signal BUSY is made to fall to L at the fall, and the timing of the busy signal output from the control unit 4 (that is, the pulse width during the H period in the active state). Is determined by the set value of the pulse width setting counter 3.

Reference numeral 5 latches set value data sent from a central processing unit (hereinafter referred to as "CPU") on the printer side via a data bus based on a latch signal WR1 and sets it in a pulse width setting counter 3. The set value latch circuit that outputs as the value data allows the user to arbitrarily change the set value data sent from the CPU with the operation unit, and the pulse width setting counter 3
Is designed to read the set value data from the set value latch circuit 5 based on the load signal / LOAD and hold it as the set value. Reference numeral 6 is an input data latch circuit for latching 8-bit parallel data D0 to D7 input from the personal computer side to the input / output port 1 for each byte. The input data latch circuit 6 is a strobe signal input to the input / output port 1. When / STB becomes L, the input data is latched at the falling edge and the latched data is output from the read data bus to the CPU on the printer side based on the data read signal / READ.

An address decoder 7 outputs a latch signal WR1, a load signal / LOAD, and a data read signal / READ based on the address data sent from the CPU on the printer side via an address bus. The latch signal WR1 The load signal /
The LOAD is output to the pulse width setting counter 3, and the data read signal / READ is output to the input data latch circuit 6. At the fall of the strobe signal / STB, a Centronics interrupt is applied to the CPU on the printer side to notify that data has been input from the personal computer side.

Therefore, first, 8-bit parallel data is output from the personal computer side to the input / output port 1 (see FIG. 2A), and the strobe signal input to the input / output port 1 to inform the printer side. When / STB falls to L for a predetermined period (see FIG. 2 (b)), the printer cannot receive the data immediately, so the control unit 4 sets the busy signal BUSY to H at the fall of the strobe signal / STB. Notify the PC that the printer is not ready to receive data when it is started up (Fig. 2
(See (c)), so that the personal computer cannot send the next 8-bit parallel data immediately, and at the rising edge of the busy signal BUSY, the pulse width setting counter 3
To start the counting operation of the basic clock CLOCK. At the same time, at the falling edge of the strobe signal / STB, the input data latch circuit 6 inputs 8
It causes the bit parallel data to be latched and causes the CPU on the printer side to make an interrupt request.

When the count value of the pulse width setting counter 3 reaches the set value and the carry signal / CARRY falls to L (see FIG. 2D), the carry signal / CARRY falls. Then, the busy signal BUSY output from the control unit 4 falls to L, the printer side is notified that the printer is ready to receive the next data, and the personal computer confirms the fall of the busy signal BUSY and 8-bit parallel data transfer is started. When the busy signal BUSY becomes L, the pulse width setting counter 3 is reset to stop counting, and the data latched by the input data latch circuit 6 becomes L before the busy signal BUSY falls. It is read at the falling edge of / READ (see FIG. 2E), and the CPU on the printer side
Will be sent to.

Then, when the next 8-bit parallel data is output from the personal computer side, the strobe signal falls to the predetermined period L again, and the same operation is repeated thereafter, whereby data transfer for each byte is performed. Will be The data transfer rate can be optimized by arbitrarily changing the timing of the busy signal BUSY with the setting value of the pulse width setting counter 3.

FIG. 4 shows a concrete example of the circuit configuration. The set value latch circuit 5 includes two 8-bit shift registers 8,
When the latch signal WR1 corresponding to the address data sent from the CPU is input from the address decoder 7, the 16-bit set value data D0 to D15 from the CPU is latched and pulsed. It is designed to output to the width setting counter 3.

The pulse width setting counter 3 is formed by combining four 4-bit counters 10, 11, 12, and 13, and sets the set value data D0 to D15 latched by the set value latch circuit 5 to an address decoder. When the busy signal BUSY is L, L is input to each clear terminal CLR, so that the count is in a stopped state where the count is cleared and the busy signal is busy. When the signal BUSY becomes H, H is input to each clear terminal CLR, so that the count operation is started and the basic clock CLO is started.
The CK is counted, and when the count value reaches the set value, the carry signal / CARRY in the L state is output from the 4-bit counter 13 at the final stage for a predetermined period.

Further, the control section 4 is configured by combining a D flip-flop circuit 15 having preset / clear terminals PR and CL and a NOR circuit 17 for holding, and the preset terminal PR of the D flip-flop circuit 15 has a power source. When the power is turned on, a reset signal / RESET (see FIG. 3 (b)) is input, which goes into the H state after the power supply voltage is in the steady state (see FIG. 3 (a)), and the power of the D flip-flop circuit 15 is turned on. When the strobe signal input to the clear terminal CL becomes L, the busy signal BUSY output from the output terminal / Q is immediately set to the H state. Also. The NOR circuit 17 for holding holds the output from the output terminal Q of the D flip-flop circuit 15 and the carry signal / CARRY from the pulse width setting counter 3.
Is input and the carry signal / CARRY in the L state is output from the pulse width setting counter 3, D
System clock SYSC for the flip-flop circuit 15
The busy signal BUSY output from the output terminal / Q of the LK is latched at the rising timing of LK to immediately set to L, and the state is held until L is input to the clear terminal CL next time.

Here, it is assumed that the system clock SYSCLK has a fairly early cycle so that the carry signal / CARRY having a relatively short pulse width can be latched. The 8-bit input data latch circuit 6 can also be configured by a shift register like the set value latch circuit 5, and 8-bit Centronics data sent from the personal computer every time the strobe signal / STB becomes L. Is read out by the data read signal / READ from the address decoder 7.

In this embodiment, the case where the handshake is performed with the strobe signal and the busy signal has been described above. However, an ACK signal is added to this to perform the handshake with the strobe signal, the busy signal, and the ACK signal. However, in this case, the timing of the ACK signal can be arbitrarily changed like the busy signal. Further, in this embodiment, the CPU of the printer is also used as the CPU of the Centronics interface, but different CPUs may be used.

[0020]

As described above, according to the data transfer method of the present invention, the data transfer between the devices is performed based on the control signal created by the hardware, and the timing of the control signal is controlled by the device. Since it can be arbitrarily changed and set according to each characteristic, the load on the CPU can be reduced as compared with the case of being created by software, that is, the program can be simplified and the processing efficiency can be improved. Moreover, it is possible to eliminate adverse effects on data transfer efficiency and device performance.

[Brief description of drawings]

FIG. 1 is a diagram showing a block configuration example of the present invention.

FIG. 2 is a signal waveform diagram thereof.

FIG. 3 is a waveform diagram of the reset signal.

FIG. 4 is a diagram showing a specific circuit configuration example.

FIG. 5 is a diagram showing an example of a conventional signal waveform.

[Explanation of symbols]

 2 Interface circuit 3 Pulse width setting counter 4 Control unit 5 Set value latch circuit 6 Input data latch circuit 7 Address decoder

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[Procedure amendment]

[Submission date] July 2, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

Further, the control section 4 is constructed by combining a D flip-flop circuit 15 having preset and clear terminals PR and CL and a NOR circuit 17 for holding, and the clear terminal CL of the D flip-flop circuit 15 is powered by a power source. ON
Sometimes the power supply voltage goes into a steady state (see FIG. 3 (a)) and then goes into H state.
(See (b)) is input, and the strobe signal input to the preset terminal PR of the D flip-flop circuit 15 becomes L when the power is ON, the busy signal BUSY output from the output terminal Q is immediately set to the H state. It is supposed to do. Further , the holding NOR circuit 17 has an output from the output terminal Q of the D flip-flop circuit 15 and a carry signal / CARRY from the pulse width setting counter 3.
Is input and the carry signal / CARRY in the L state is output from the pulse width setting counter 3, D
System clock SYSC for the flip-flop circuit 15
The busy signal BUSY output from the output terminal Q of the LK is latched at the rising timing of LK to immediately set to L, and the state is held until L is input to the preset terminal PR next time.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

Claims (3)

[Claims] 1. In a data transfer system in which data transfer between devices is performed based on a control signal created by hardware, and the data transfer rate is determined by the timing of the control signal, the timing of the control signal is determined by the characteristics of each device. A data transfer method characterized in that it can be arbitrarily changed according to. 2. A data transfer system between a computer and a printer, wherein the control signal is a busy signal indicating that the printer cannot receive data, and is set in a parallel interface circuit equipped on the printer side. The control means for outputting a busy signal to the computer side at a predetermined timing, and the variable means for arbitrarily varying the timing set in the control means are provided. Data transfer method described in. 3. The control means has a counter which counts the basic clock and permits the output of a busy signal indicating that the printer is in a state of not receiving data until the count value reaches a set value. 3. The variable means has a latch circuit for latching set value data sent from a central processing unit on the printer side and outputting the set value data to a counter as a set value. Data transfer method.