JPS6072057A - Dma controller - Google Patents

Abstract

PURPOSE:To expand a use range by outputting an interrupting signal, when a DMA transfer data is latched temporarily and coincides with the final data code set and stored in advance, or when an end signal of a transfer data number counter is outputted. CONSTITUTION:The forward address of a DMA transfer and the number of transfer data are stored and counted up by an address counter 1, the maximum data transfer number and an EOD code for showing the end of the DMA transfer are set in advance to a transfer data number counter 2 and a final data code register 3, respectively, and the data is latched and stored temporarily at each cycle of the DMA transfer in a data latch register 6. Subsequently, outputs of the register 3 and 6 are inputted to an NAND gate 4 through a comparator 5 together with an output of the counter 2, and an interrupting signal INT is generated. In this way, the end of the DMA transfer, etc. by an EOD code designated to a character string can be executed.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention is directed to DMA (Direct Memory Access) which realizes high-speed data transfer in electronic computers.
) Regarding the controller.

[Prior art]

Conventionally, DMA directly transfers data between memories or between a memory and an input/output device without being controlled by a processor, and thus can transfer data faster than a program-controlled method. DMA controller 1 controls this direct data transfer. conventional DMA
In order to perform this data transfer, the controller sets a transfer address register and a transfer data count register to 4J.The CPU (Central Processing Unit) sets the transfer address and transfer data count in these registers in advance, and the number of data transfers is determined. The process was completed when the process was completed for the number of data to be transferred.

If the transfer liquid is a character string, it is encoded as H OD (E, nd 0fl
) ata door can be specified, and R at the end of the string.
Although it is easy to transfer data by placing an OD code, conventional DMA controllers cannot terminate DMA transfer using an EOD code. Therefore, in conventional DMA controllers, the number of characters to be transferred and the CPU
This was inconvenient as it required a person to count and set up the counter in advance. Furthermore, in the case of DMA transfer from the external I10 port to the internal memory, if the number of data to be transferred from the external I10 port is not known in advance, 1) the MA controller cannot be used.

As described above, the conventional DMA controller has the disadvantage that it is not possible to terminate a DMA transfer using an EOD code, and the KitDΔ4A controller cannot be used if the number of data to be transferred is not known in advance.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to automatically detect the code indicating the end of DMA transfer when the number of transferred data is not known in advance or in case of character transfer by specifying the code. D that can terminate the DMA transfer by
B. (A) To provide a controller.

[Structure of the invention]

The DMA controller of the present invention is a DMA controller that performs data transfer between memory servers or between memory output ports.
An address counter that records and counts up the start address of A transfer and the number of transferred data, a transfer data number counter that counts the transferred data, and a final data code that sets and stores a code indicating after M of the transfer data group. A register, a data latch register that temporarily latches the DMA transfer data, a comparator that compares the output of the final data code register, the output of the comparator, and the output of the previous 5 transfer data counter. and a gate for outputting an interrupt signal when the comparator outputs a match signal or the transfer data number counter outputs a transfer end signal. Ru.

[Explanation of Examples]

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This example is a DMA transfer that transfers data between memory memos 98 or between memory ports, the start address of the transfer, 1x sending data AI, the address counter 1 that counts up after writing 1 word, and the number of transferred data. 1) A data number counter 2, a final data code register 3 that sets and stores a code indicating the end of the transfer data 1, and a data latch register 4 that temporarily latches the MA transfer data. , a comparator 5 that compares the output of the final data code register 3 and the output of the data latch register 4, and the output of this comparator 5 and the output of the transfer data number counter 2 as inputs, and the comparator 5 detects coincidence No. 18. A NAND gate 4 outputs an interrupt signal INT when the transfer data counter outputs a transfer end signal.

To explain in more detail, address counter 1 is DM
It stores the start address of A transfer and generates an address signal for DMA execution. Address counter 1 has DMA
A transfer request signal DRQ is input, and upon receiving this signal, the address is incremented and an address signal AO-15 is outputted to the outside through the control logic and mode set register 9. Further, the address counter 1 returns a DMA transfer end confirmation signal DACK.

The transfer data number counter 2 is
The maximum number of data transfers is set from If the set value is O'', the maximum number of data transfers is infinite.

Final data code register 3 is KCP before DMA transfer execution.
An EDO code indicating the end of fiDMA transfer is set in U and stored. Data latch register 6 is DM
Data is latched every cycle of A transfer, temporarily stored, and compared with the final data code register.

Comparator 5 compares the contents of the final data code register with the contents of the data latch register, and outputs a low level signal if the contents match, and outputs a high level signal if they do not match.

NAND gate 4 receives DM from transfer data number counter 2
The A end signal and the DMA end signal from the comparator 5 are ANDed and output. This becomes an interrupt signal INT to the CPU. When the CPU receives this signal, it generates an interrupt confirmation signal INTA, and the DMA controller inputs this signal to cancel the interrupt signal INT.

In this embodiment, the output signal of the transfer number data counter is set to active low, that is, the transfer end signal is set to 0''.The match signal of comparator 5 is also set to active low. Therefore, if either the output of the transfer data number counter 2 or the output of the comparator 5 is at a low level, the NAND gate 4 outputs an active high interrupt signal INT.

The method of generating the interrupt signal INT is not limited to the above method. In short, a gate may be provided so that an interrupt signal is generated when the comparator 5 outputs a match signal or when the transferred data number counter 2 outputs a signal indicating that the transfer has been completed.

Next, the operation of this embodiment will be explained.

There are two modes of operation for this embodiment. That is, a mode in which the conventional technology has a register for setting the transfer start address and the number of data to be transferred, and performs DMA transfer using the same parameters (hereinafter, this mode will be referred to as mode 1). and,
This mode has registers for setting the transfer start address and transfer final data code, and performs DMA transfer using the same parameters (hereinafter, this mode will be referred to as mode 2).

These two modes are selectable and are selected by setting a mode selection code in the control logic and mode set register 9. Control logic and mode set register 9 is D? 1 (generates control signals for executing A transfer; that is, address signal AO-15, which is an execution address signal for DMA transfer, memory read signal MBMR,
- Generates a memory write signal MEMW and an address enable signal AFiN indicating the stapling period of the address signal. Further, the control logic and the code set in the mode set register in the mode set register 9 generate a control signal for controlling each block to the mode 1 or mode 2 operation mode.

The mode set is performed by: 1) Before MA transfer, the CPU (central processing unit) side activates the selection signal C8 of the DMA controller to access the DMA controller and set the mode set register. This mode code is set in the mode set register from the data bus buffer 7 via the internal bus IO. The read/write sync 8 is a circuit that processes signals for accessing the DMA controller, outputs the status of the DMA controller, and controls the transmission and reception of data with each block.

The signals input to this block are the selection signal C8, the reset signal that returns the DMA controller to its initial state, and the RESET signal.
, a block CLK that is the basic operation of the DMA controller, in the input direction it serves as a read signal for the status of the DMA controller, and in the output direction it serves as a DM to the external I10 port.
A bidirectional I10 device read signal that becomes the A access signal 110R In the input direction, it is a data write signal to the internal register of the DMA controller, and in the output direction, it is the external I10 device read signal.
The bidirectional I10 device write signal l10W is the DMA access signal for the 10 port.

Reference numeral 11 denotes an internal register control signal for accessing and controlling internal registers.

FIG. 2 is a flowchart illustrating a procedure for selecting and setting an operating mode according to an embodiment of the present invention.

This flowchart shows the procedure for initializing mode 2 of the above two modes. In step 31, a code indicating mode 2 is written into the mode set register. Next, in step 32, DMA is sent to the att/counter/register.
Transfer start address and write, D Ai in step 33
A code indicating the end of A transfer is set in the final data code register 3. Next, in step 34, the maximum number of data transfers is set to the same t/register 3. The above is the procedure before DMA transfer, and then the generation of DMA transfer request signal DRQ becomes a trigger signal and a DMA transfer cycle begins.

FIG. 3 is a timing chart when the embodiment shown in FIG. 1 is operated.

D from the external I10 boat to the memory using Figure 3.
The case where MA transfer is performed will be explained as an example.

In FIG. 3, cycle 21 is I) the DMA transfer cycle immediately before the end of MA transfer, and cycle 22 is the last J)
MA transfer cycle, cycle 23 is ;q1] transfer 1
This indicates the cycle in which No. 8 INT is output and I) MA transfer is completed.

In cycle 21, first DM from the external 110 boat
When the A transfer request signal 1) RQ is issued, the address value of the address counter 1 is communicated with the internal bus 10 and enters the control logic and mode set register 9, from which the memory selection address signal AO-15 is externally transmitted. Served. [Next] Address enable No. 1d A indicating the stable period of the address signal from the wholesale logic and mode set register
HN is issued. Furthermore 1. Memory light 1B-? Country 1
4EMVV signal is issued. Writing of data 2 begins in the memory.

DMA transfer confirmation signal DAcK from the DMA controller
is output to the external I10 port, and the external I10 port finishes outputting data to the data bus.

In cycle 22, DM from the external i10 boat again.
A transfer request signal 1) RQ is issued, address enable signal MΔ memory write signal MEMW from D and MA controller is issued. On the other hand, data from the data bus is temporarily stored in the data latch register 6 via the data buffer 7 and the internal bus 10. Then, the contents of the final data code register 3 and the contents of the data latch register 6 are input to the comparator. If they match, a low level signal is output and passes through NAND gate 4 to interrupt signal I.
NT is output to CP TJ.

In cycle 23, 61 of the DMA controller
When the CPU receives the J interrupt signal INT, the CPU issues an interrupt confirmation number B1. Output NTA to DMA controller and roller. When the DMA controller receives the interrupt confirmation signal INTA, it outputs and releases the interrupt signal INT. Now D
MA transfer is terminated.

〔Effect of the invention〕

As explained in detail above, according to the present invention, in the case of a call or a character string transfer where the number of data to be transferred is not known in advance, if the 1 role end code of the DMA transfer is specified, the own QJ
A DMA controller is obtained that can automatically detect this code and terminate the DICIA transfer. Furthermore, it is possible to apply this method to search an address containing a specific data code from a certain memory area.

[Brief explanation of the drawing]

1st r'<l is a pronk diagram of an embodiment of the present invention, ri8
Figure 2 is a flowchart illustrating the procedure for selecting and setting the operating elements of an embodiment of the present invention, and Figure 3 is a timing diagram when changing the operation mode 1 shown in Figure 1. be. 1...Address counter, 2...Small i
:TI'H data (counter, 3...most, I side gate code register, 4...NAD gate, death...comparison 45.6...・Data latch register, 7...Data bus buffer 1.8・
・・・・・・Read/Write logic, 9°” ”' ′
Li river official magic mode set register, 10...
... Internal bus, 11゜12 ... Internal register control signal, 21, 22, 23゜ ... Transfer cycle, AO-15 ... Address signal, AFiN ...
...Address enable signal, CI, K...
・Clock, D7-0...Data signal, DAC
k...DMA transfer end confirmation signal, DRQ...
...DMA transfer request signal, l10R...
・I10 device read signal, l10W...I10
Device write signal, IN'l'... Interrupt signal,
INTA...Interrupt hra acknowledgment signal, λili:
Ml<...Memory read signal, 1'vjE1~
lv/...Memory write signal, RESET...
mark/reset signal. /NTA vJI Kabuto Z diagram

Claims (1)

[Claims] An address counter that stores and counts up the start address of DMA transfer and the number of transferred data that transfers data between memories or between memory and output boats, a transfer data number counter that counts the number of transferred data, and a group of transferred data. a final data code register that sets and stores a code indicating the end of the data, a data latch register that temporarily latches the DIVfA transfer data, and a ratio Y' that compares the output of the final data code register with the output of the data latch register. l'b%, the output of the ratio: 16 unit, and the output of the transfer data number counter are input, and an interrupt is generated when the comparator outputs a match signal or the transfer data number counter outputs a transfer end signal. A hanging L controller characterized by controlling a gate that outputs a signal.