JPH0448262B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory access control device that continuously controls access to data consisting of a plurality of elements in an information processing device.

(Prior Art) In a memory access control device for an information processing device, it is assumed that a plurality of elements are respectively arranged at regular intervals on a memory. Conventionally, the method of accessing data consisting of multiple elements is to test whether the memory unit to be accessed element by element is in a used state, and if this memory unit is not in a used state, an access request to the memory is issued. A method of transmitting a signal has been proposed. for example,
According to this method in Special Publication No. 57-56751,
If the number of memory units is small, the amount of hardware will be small, but if the number of memory units is large, the amount of hardware will be large.

Devices that handle data consisting of a plurality of elements generally tend to increase the number of memory units to avoid contention within the memory units, resulting in a noticeable increase in the amount of hardware. As a method to solve this increase in hardware amount, a method has been proposed in which all memory units are kept in use and the sending of access request signals to the memory is restricted to prevent contention within memory units. ing.

(Problems to be Solved by the Invention) In the above-mentioned conventional technology, after sending an access request signal to the final element in the preceding data, all memory units are in a used state for the cycle time of the memory unit. Even when an attempt is made to access a memory unit that has not been accessed by the preceding data by accessing subsequent data, there is a problem in that performance deteriorates because the user is forced to wait for the cycle time of the memory unit.

The purpose of the present invention is to calculate the address information of the last element of the first data, compare this address information with the address information of the first element of the second data, and calculate the relationship between the address information and the cycle time of the memory unit. It is an object of the present invention to provide a memory access control device configured to eliminate the above-mentioned drawbacks and shorten waiting time by making it possible to calculate the number of waiting clock cycles from the data.

(Means for Solving the Problems) A memory access control device according to the present invention provides a memory access control device which can be accessed independently of each other and which is arranged at regular intervals on the memory for each of the memories that are addressed in the order of a plurality of memory units. The device is capable of controlling access to data consisting of a plurality of elements arranged in the first and second supply means, the first calculation means, the address holding means, and the distance information holding means. , and second calculation means.

The first supply means is for supplying the number of data elements, and the second supply means is for supplying address information to the memory unit of the first element.

The first calculating means is for calculating the address information of the memory unit of the last element from the number of data elements, the address information of the memory unit of the first element, and the interval information between elements.

The address holding means is for holding address information of the memory unit of the final element.

The distance information holding means is for holding information that provides an inter-element distance for specific data.

The second calculation means calculates the memory unit address information of the final element for the specific data held in the address holding means and the first element of the second specific data to be accessed subsequent to the specific data. and the address information of the memory unit to calculate the time interval during which an access element based on the second specific data can be sent to the memory unit that is in use due to the access of the specific data. It is.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory access control device according to the present invention. Referring to FIG. 1, the embodiment of the present invention includes first to fourth adder circuits 2, 6, 12, and 13, first and second registers 4 and 5, and first and second shift registers. It is composed of circuits 1 and 9, first to third two's complement circuits 3, 10 and 11, a comparison circuit 7, a subtraction circuit 8, and a gate circuit 14.

In FIG. 1, the first shift circuit 1 has a number of elements VL supplied from a signal line 102 and a signal line 103.
The data length (VL-1)×D is calculated from the inter-element distance D supplied from the signal line 104, and is supplied to the first conversion circuit 2 from the signal line 104. The first adder circuit 2 adds the address information of the first element supplied from the signal line 101 and the data length supplied from the signal line 104, obtains the address information of the last element, and adds the address information of the first element supplied from the signal line 105 to the first register. Supply to 4.

The first two's complement circuit 3 calculates the two's complement of the address information of the leading element supplied from the signal line 101 and supplies it to the second adder circuit 6 from the signal line 106.

The first register 4 holds address information of the final element of data that is the output of the first adder circuit 2,
The signal is supplied to the second addition circuit 6 from the signal line 107.
The second adder circuit 6 adds the two's complement of the address information of the head element supplied from the signal line 106 and the address information of the last element of the data supplied from the signal line 107, and adds the address information of the last element of the data supplied from the signal line 107 to and the address information of the first element of the data is calculated and output from the signal line 110.

The second register 5 holds the inter-element distance D supplied from the signal line 103 and supplies it to the comparison circuit 7 from the signal line 108. The comparator circuit 7 compares the inter-element distance held by the second register 5 and the signal line 10.
3 and sends an equal or larger value E to the second shift circuit 9 via the signal line 111.

The subtraction circuit 8 subtracts the cycle time information value TC of the memory unit supplied from the signal line 109 by 1 to generate TC-1, and the subtraction circuit 8 subtracts by 1 the value TC of the cycle time information of the memory unit supplied from the signal line 109, and generates TC-1 from the signal line 112. Send it to 11. The first shift circuit 9 calculates [(difference in the address information)÷E] based on the difference between the output E of the comparison circuit supplied from the signal line 111 and the address information supplied from the signal line 110, Signal line 1
Send from 13.

The second two's complement circuit 10 calculates the two's complement of [(difference in the above address information)÷E] supplied from the signal line 113 and supplies it to the third adder circuit 12 from the signal line 114. The third three's complement circuit 11 calculates the two's complement of the TC-1 supplied from the signal line 112, and the fourth adder circuit 13 is connected to the signal line 115.
Send to. The third adder circuit 12 uses the signal line 114
The output of the second 2's complement circuit 10 supplied from the circuit 10 and the above-mentioned TC-1 supplied from the signal line 112 are added, and the result is output from the signal line 116 to the gate circuit 14.

The fourth adder circuit 13 adds [(difference in the above address information)÷E] supplied from the signal line 113 and the two's complement of the above TC-1 supplied from the signal line 115, and calculates the most significant bit. It is sent to the gate circuit 14 from the signal line 117. Gate circuit 14 is connected to signal line 1
Depending on the logic value of the signal provided by line 17, it will output either the data provided by signal line 116 or a "0", said output giving the number of clock cycles required for queuing.

Next, the operation in the above configuration will be explained in detail.

In this embodiment, it is assumed that the number of memory units is 64, the cycle time of the memory unit is 16 clock cycles, and the number of data elements is up to 64. First, a case where both the inter-element distance of the first data and the inter-element distance of the second data are "1" will be described.
When a first data access request is issued, the number of elements is supplied to the first shift circuit 1 from the signal line 102, and the inter-element distance D (=1) is supplied from the signal line 103.
is supplied, the data length is calculated, and the signal line 104 is
This data length is supplied to the first adder circuit 2. The first adder circuit 2 calculates the address information of the last element of the first data by adding the above data length and the address information of the first element supplied from the signal line 101. Supplied to register 4. The first register 4 holds the address information of the final element until a second data access request is issued.

The second register 5 is connected to the first register by a signal line 103.
An inter-element distance D=1 of the data is supplied, and this data is held in the second register 5 until a second data access request is issued. When the sending of the first data access request to the memory is started, a second data access request is issued.
When a second data access request is issued, the address information of the leading element sent from the signal line 101 is added to the first two's complement circuit 3, and after obtaining the two's complement, the address information of the first element is sent from the signal line 106 to the The signal is supplied to the adder circuit 6 of No.2. The second adder circuit 6 calculates the difference between the address information of the last element of the first data held in the first register 4 and the address information of the first element of the second data.

The comparator circuit 7 receives the inter-element distance (“1”) of the first data held in the second register 5 and the distance (“1”) between the second data elements supplied from the signal line 103. is input, and when the above two are equal or larger, “1” is input to the second shift circuit 9.
supplied to The second shift circuit 9 outputs [(difference in the address information)/E] obtained by the second adder circuit 6, that is, the difference in the address information, from the signal line 113.

The fourth adder circuit 13 adds the difference in address information output from the second shift circuit 9 and the two's complement of TC-1 obtained by the third two's complement circuit 11. The difference in the address information and the most significant bit indicating the magnitude relationship of the normalized cycle time information are supplied to the gate circuit 14 from a signal line 117 as a control signal for controlling the gate circuit 14. In other words, the difference in the above address information is
When there is TC-1, that is, "15" or more, the output of the gate circuit 14 becomes "0". Therefore, the first
As soon as access to the data memory is completed, it is possible to send an access request signal to the second data memory. Figure 2A
is an explanatory diagram showing a data state when the difference in address information is "15". If the difference in address information is less than "15", the fourth adder circuit 13 subtracts "15", so the output of the fourth adder circuit 13 becomes negative, and the signal line 117 outputs "1". is output. Therefore, the contents of the third adder circuit 12 are sent out from the gate circuit 14 via the signal line 119. The third adder circuit 12 outputs the output of the second shift circuit 9 from TC-1, that is, the value obtained by subtracting the difference in the address information. For example, if the difference in address information is "14", the output of the third adder circuit 12 is "15" as shown in FIG. 2B.
-14=1", the output of the fourth adder circuit 13 becomes "14-15=-1", and the output of the most significant bit becomes "1". Therefore, the output of the gate circuit 14, i.e. The clock cycle required for queuing is one clock cycle.The access request signal to the memory for the second data is sent from the timing when the access request signal for the final element of the first data is sent to the memory. It starts after the number of waiting clock cycles plus one clock cycle.

In this case, the sending of the access request signal to the memory is started two clock cycles after the timing at which the access request for the last element of the first data is sent to the memory. Furthermore, since addition is performed modulo 64 even when the difference in address information is negative, the output of the third adder circuit 12 can be used as is and handled in the same way.

Next, a case where the inter-element distance of the first data and the inter-element distance of the second data are different will be described.

For example, if the inter-element distance of the first data is "2" and the inter-element distance of the second data is "1", the comparator circuit 7 outputs "2",
From the second shift circuit 9 [difference in address information]
÷2] is output. The difference in the above address information is 30
With the above, the output of the second shift circuit 9 is 30÷
2, that is, 15 or more, and the fourth addition circuit 13
The value of the control signal sent from the controller becomes "0". Therefore, the gate circuit 14 outputs "0" as the number of waiting clock cycles. That is, as soon as the access to the memory for the first data is completed, it becomes possible to send an access request signal to the memory for the second data. FIG. 3A is an explanatory diagram showing a state when the difference in address information is 30. If the difference in address information is less than 30, the value output from the second shift circuit 9 is 15
Therefore, the output of the fourth adder circuit 13 becomes negative, and "1" is output from the signal line 117 as a signal for controlling the gate circuit 14. Now, assuming that the difference in address information is 26, the second shift circuit 9 outputs 26÷2, that is, 13, so the adder circuit 12 supplies "15-13=2" to the gate circuit 14. . The gate circuit 14 outputs the above value 2 as the clock cycle necessary for waiting. Therefore, after the access request for the final element of the first data is sent to the memory, 2+
After 1=3 clock cycles, the sending of the access request signal to the memory is started. here,
FIG. 3B is an explanatory diagram showing the above state.

(Effects of the Invention) As explained above, the present invention calculates the access information of the last element of the first data, compares this address information with the address information of the first element of the second data, and calculates the access information of the last element of the first data. By being able to calculate the number of waiting clock cycles from the relationship and the cycle time of the memory unit, it is possible to predict the timing when the memory unit will no longer be in use, and it is possible to accelerate the access request signal for the second data. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory access control device according to the present invention. FIGS. 2 and 3 are explanatory diagrams showing the relationship between address information and the timing of sending an access request signal, respectively. 1, 9...shift circuit, 2, 6, 12, 13...
...Addition circuit, 3, 10, 11...2's complement circuit,
4, 5...Register, 7...Comparison circuit, 8...Subtraction circuit, 14...Gate circuit.

Claims (1)

[Claims] 1. For memory that can be accessed independently of each other and that is addressed in the order of multiple memory units,
A memory access control device capable of controlling access to data each consisting of a plurality of elements arranged at regular intervals on the memory, a first supply means for supplying the number of elements of the data; a second supply means for supplying address information to a memory unit of a first element; and an address of a memory unit of a final element based on the number of elements of the data, address information of the memory unit of the first element, and interval information between elements; a first calculation means for calculating information, an address holding means for holding address information of the memory unit of the final element, and a distance for holding information giving an inter-element distance for specific data. information holding means, address information of a memory unit of a final element for the specific data held in the address holding means, and a first element of second specific data to be accessed subsequent to the specific data; and the address information of the memory unit, to calculate a time interval during which an access element based on the second specific data can be sent to the memory unit that is in use due to the access of the specific data. Second
1. A memory access control device comprising: calculation means.