JPS61255448A - Memory access control device - Google Patents

Abstract

PURPOSE:To forecast the timing in which the memory unit comes to be the nonuse condition and to hasten the access by calculating the number of the waiting clock cycle from the relation between the final address information of the first data and the head address information of the second data, and the cycle time of the memory unit. CONSTITUTION:By the access of the first data, the number of factors and a distance D between factors are supplied to the first shifting circuit 1, the data length is calculated, and further, the address information of the final factor of the first data is calculated at the first adder circuit 2. By the access of the second data, the final and head address information difference of both data is calculated at the second adder circuit through a complement circuit 3, and the address information difference is outputted from the second shifting circuit by the relation of the distance between factors of the first and second data obtained from a comparing circuit 7. The fourth adder circuit 13 outputs the control signal of a gate circuit 14 from the difference the highest order bit to show the size relation of the regularized cycle time information and the address information, and outputs and controls the adder value of the output of TC-1 from the third adder circuit 12 and the complement circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a memory access control device that continuously controls access to data consisting of a plurality of elements in an information processing device.

(Prior Art) In a memory access control device for an information processing device, it is assumed that a plurality of elements are respectively arranged at regular intervals on a memory. Conventionally, the method of accessing data consisting of multiple elements is to test whether the memory unit to be accessed element by element is in the used state, and if this memory unit is not in the used state, access to Memo 'JK is performed. A method has been proposed in which a request signal is sent. For example, according to the method disclosed in Japanese Patent Publication No. 57-56751, if the number of memory units is small, the amount of hardware is small, but if the number of memory units is large, the amount of hardware is increased.

Devices that handle data consisting of a plurality of elements generally tend to increase the number of memory units to avoid contention within the memory units, resulting in a noticeable increase in the amount of hardware. As a method to solve this increase in the amount of hardware, a method has been proposed in which all memory units are kept in use and the sending of access request signals to the memory is restricted to prevent contention within memory units. I'm here.

(Problems to be Solved by the Invention) In the above-mentioned conventional technology, the highest number in the preceding data!
After sending an access request signal to an element, all memory units are in use for the memory unit cycle time, and subsequent data accesses attempt to access memory units that are not accessed by previous data. Even in this case, there is a problem that the performance deteriorates because the user is forced to wait for the cycle time of each memory unit.

The purpose of the present invention is to calculate the address information of the last element of the first data, compare this address information with the address information of the first element of the second data, and calculate the relationship between the address information and the cycle time of the memory unit. It is an object of the present invention to provide a memory access control device configured to be able to calculate the number of waiting clock cycles from the above, thereby eliminating the above-mentioned drawbacks and shortening the waiting time.

(Means for Solving the Problems) A memory access control device according to the present invention provides a memory access control device that can be accessed independently of each other and that is arranged at regular intervals on the memory for each memory that is addressed in the order of a plurality of memory units. The device is capable of controlling access to data consisting of a plurality of elements arranged in the first and second supply means, the first calculation means, the address holding means, and the distance information holding means. , and second calculation means.

The first supply means is for supplying the number of data elements, and the second supply means is for supplying the number of data elements, and the second supply means is for supplying the number of data elements.
It is for supplying address information.

The first calculating means is for calculating the address information of the memory unit of the last element from the number of data elements, the address information of the memory unit of the first element, and the interval information between elements.

The address holding means is for holding address information of the memory unit of the final element.

The distance information holding means is for holding information that provides an inter-element distance for specific data.

The second calculation means calculates the memory unit address information of the final element for the specific data held in the address holding means and the first element of the second specific data to be accessed subsequent to the specific data. This method is for calculating the time interval at which an access element based on a second specific data can be sent to a memory unit that is in use due to an access of specific data by calculating the difference between the address information of the memory unit and the address information of the second specific data. It is.

(Example) Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory access control device according to the present invention. Referring to FIG. 1, the embodiment of the present invention includes first to fourth adder circuits 2, 6, 12, . and 13, first and second registers 4 and 5, first and second shift circuits 1 and 9, first to eighth two's complement circuits 3, 10 . and 11, and comparison circuit 7
, a subtraction circuit 8, and a gate circuit 14.

In FIG. 1, the first shift circuit 1 calculates the data length (VL-1)XD from the number of elements VL supplied from the signal line 102 and the distance between elements supplied from the signal line 103, and The signal is supplied to the first adder circuit 2 through the signal line 104. The first adder circuit 2 adds the address information of the first element supplied from the signal line 101 and the data length supplied from the signal line 104, obtains the address information of the last element, and adds the address information of the first element supplied from the signal line 105. is supplied to register 4 of.

The first two's complement circuit 5 calculates the two's complement of the address information of the leading element supplied from the signal line 101, and
06 is supplied to the second adder circuit 6.

The first register 4 holds the address information of the final element of the data output from the first adder circuit 2, and supplies it to the second adder circuit 6 via the signal line 107.

The second adder circuit 6 adds the two's complement of the address information of the head element supplied from the signal line 106 and the address information of the last element of the data supplied from the signal line 107, The difference between the address information of the last element and the address information of the first element of the data is calculated, and the signal line 11
Outputs more than 0.

The second register 5 holds the inter-element distance supplied from the signal line 103 and supplies it to the comparison circuit 7 via the signal line 10B. The comparison circuit 1 compares the inter-element distance held by the second register 6 and the inter-element distance supplied by the signal line 105, and selects an equal or larger value E to the signal line 1.
11 to the second shift circuit 9.

The subtraction circuit 8 subtracts by 1 the value TC of the cycle time information of the memory unit supplied through the signal line 109 to generate TC-1, and the subtraction circuit 8 generates TC-1 by subtracting the value TC of the cycle time information of the memory unit supplied through the signal line 109.
2's complement circuit 11. The first shift circuit 9 calculates [(difference in the address information)÷E] based on the difference between the output E of the comparison circuit supplied from the signal line 111 and the address information supplied from the signal line 110, Signal line 1
13, send it out.

The second two's complement circuit 10 calculates the two's complement of [(difference in the above address information)÷E] supplied through the signal line 113 and supplies it to the eighth adder circuit 12 through the signal line 114. . The eighth 8's complement circuit 11 calculates the 2's complement of the TC-1 supplied from the signal line 112, and
The signal is sent to the adder circuit 15. The eighth adder circuit 12 adds the output of the second two's complement circuit 10 supplied from the signal line 114 and the above-mentioned TC-1 supplied from the signal line 112, and outputs the result to the gate circuit 14 from the signal line 116. do.

The fourth adder circuit 13 is supplied with signal line 113 [(
The difference in address information (10E) is added to the two's complement of TC-1 supplied from the signal line 115, and the most significant bit is sent to the signal line 117 to the siggate circuit 14. The gate circuit 14 outputs the data supplied by the signal line 116 or %Ol depending on the logical value of the signal supplied by the signal line 117, and the above output is necessary for waiting and provides the number of lock cycles. .

Next, the operation in the above configuration will be explained in detail.

In this embodiment, it is assumed that the number of memory units is 64, the cycle time of the memory unit is 16 clock cycles, and the number of data elements is up to 64. First, both the inter-element distance of the first data and the inter-element distance of the second data are %11.
The case will be explained below. When a first data access request is issued, the signal line 102 is connected to the first shift circuit 1.
The number of elements is supplied, and the distance D between the elements is supplied to the signal line 105.
(=1) is supplied, the data length is calculated, and the signal line 10
This data length is supplied to the first adder circuit 2.

The first adding circuit 2 adds the above data length and the address information of the leading element supplied from the signal line 101,
calculates the address information of the final element of the data, and connects the signal line 1
05 to the first register 4. The first register 4 holds the address information of the final element until a second data access request is issued.

The inter-element distance D=1 of the first data is supplied to the second register 5 via the signal line 10M, and this data is held in the second register 6 until a second data access request is issued. When the sending of the first data access request to the memory is started, a second data access request is issued.

When a second data access request is issued, signal line 10
The address information of the first element sent from 1 to 2 is the first 2.
is added to the complement circuit 3, and after obtaining the two's complement, is supplied to the second adder circuit 6 via the signal line 106. In the second adder circuit 6, the first
The difference between the address information of the last element of the data and the address information of the first element of the second data is calculated.

The comparison circuit T has the first data held in the second register 5.
The distance between elements of the data (% 1 #) and the signal line 105
Distance between second data elements supplied by (% 1 #)
is input, and when the above two are equal or larger, %11 is supplied to the second shift circuit 9. In the second shift circuit 9, the [
(0 difference in address information) 10E], that is, the difference in address information is output to the signal line 113.

The fourth adder circuit 13 adds the difference in address information output from the second shift circuit 9 and the two's complement of TC-1 obtained by the third two's complement circuit 11. The difference in the address information and the most significant bit indicating the magnitude relationship of the normalized cycle time information are supplied to the gate circuit 14 through the signal line 117 as a control signal for controlling the gate circuit 14. In other words, the difference in the above address information is T
C-1, that is, %151 or more, the output of the gate circuit 14 becomes %Ol. Therefore, as soon as the access to the memory for the first data is completed, it is possible to immediately send an access request signal to the memory for the second data. Figure 2 (A) shows that the difference in address information is 11.
51 is an explanatory diagram showing a data state in case of No. 51. FIG. If the difference in address information is less than β151, the fourth adder circuit 1
To subtract %151 by 3, the fourth adder circuit 13
The output is negative, and all is output from the signal line 117.

Therefore, the contents of the third adder circuit 12 are the same as those of the gate circuit 1.
4 via the signal [119.

The third adder circuit 12 outputs the output of the second shift circuit 9 from TC-1, that is, the value obtained by subtracting the difference in the address information. For example, the difference in address information is 114
1, as shown in FIG. 2 ('B), for example, if the distance between elements of the first data is %21 and the distance between elements of the second data is %11, then is%21
is output, and the second shift circuit 9 outputs [(difference in address information)→2]. If the address information O difference is 30 or more, the output of the second shift circuit 9 is 80÷
2, that is, 16 or more, and the value of the control signal sent from the fourth adder circuit 13 is %Ol. Therefore, the gate circuit 14 outputs %O as the number of waiting clock cycles.
l is output. That is, as soon as the access to the first data memory is completed, it becomes possible to send an access request signal to the data memory of gK2.

FIG. 8(A) is an explanatory diagram showing a state when the difference in address information is 30. If the difference in address information is less than 80, the value output from the second shift circuit 9 is less than 15, so the output of the fourth adder circuit 13 is negative.
%11 is output from the signal line 117 as a signal for controlling the gate circuit 14. Now, the difference in address information is 26
Assuming that the output of the eighth adder circuit 12 is 115 as shown,
-14=1', the output of the fourth adder circuit 13 is %1
4-15=-1# and the most significant bit output is 111
becomes. Therefore, the output of the gate circuit 14, that is, the lock cycle required for waiting is one clock cycle. Sending of the access request signal to the memory for the second data starts after the number of waiting clock cycles plus one clock cycle from the timing at which the access request signal for the final element of the first data is sent to the memory.

In this case, the sending of the access request signal to the memory is started two clock cycles after the timing at which the access request for the last element of the first data is sent to the memory. Furthermore, even when the difference in address information is negative, since addition is performed modulo 64, the output of the eighth adder circuit 12 can be used as is and handled in the same way.

Next, a case where the inter-element distance of the first data and the inter-element distance of the second data are different will be described.

Then, from the second shift circuit 9, 26÷2, that is, 13
is output, so the addition circuit 12 outputs turtle 15-18=2
# is supplied to the gate circuit 14.

The gate circuit 14 outputs the above value 2 as a lock cycle necessary for waiting. Therefore, after 2+1=8 clock cycles after the access request for the last element of the first data is sent to the memory, the sending of the access request signal to the memory is started. Here, FIG. 3 CB) is an explanatory diagram showing the above state.

(Effects of the Invention) As explained above, the present invention calculates the address information of the last element of the first data, compares this address information with the address information of the first element of the second data, and calculates the address information of the first element of the second data. Make it possible to calculate the number of waiting clock cycles from the relationship and the cycle time of the memory unit, predict when the memory unit will no longer be in use, and #! This has the effect of speeding up the data access request signal in step 2.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory access control device according to the present invention. FIG. 2 and FIG. 8 are explanatory diagrams showing the relationship between address information and the timing of sending an access request signal, respectively. 1.9.Write/Shift circuit 2.8.12.13... Addition circuit! , 10.11...2's complement circuit 4.6φ circuit/Register 7...Comparison circuit 8...Subtraction circuit 14...Gate circuit

Claims (1)

[Claims] A memory capable of controlling access to data consisting of a plurality of elements arranged at regular intervals on each memory, which can be accessed independently of each other and which are addressed in the order of a plurality of memory units. an access control device comprising: a first supply means for supplying the number of elements of the data; a second supply means for supplying address information to a memory unit of a leading element; the number of elements of the data; a first calculation means for calculating memory unit address information of the final element from the memory unit address information of the first element and inter-element interval information; and for holding the memory unit address information of the final element; address holding means, distance information holding means for holding information giving an inter-element distance for specific data, and a memory unit of a final element for the specific data held in the address holding means. By calculating the difference between the address information of the memory unit of the first element of the second specific data that is accessed subsequent to the specific data, the memory unit becomes in use state by accessing the specific data. a second calculation means for calculating a time interval at which an access element based on second specific data can be sent to a memory unit in which the memory access control apparatus is configured.