JPH0436852A - Dma controller - Google Patents

Abstract

PURPOSE:To transfer the data at a high speed without giving any load to a CPU by selecting sequentially the registers holding the page addresses to undergo the accesses and applying these selected registers to a memory as the high order addresses. CONSTITUTION:An address counter 34 generates the addresses in a page as the low order memory addresses, and plural page address registers RG0 - RGn-1 hold the addresses of plural pages to undergo the accesses with the DMA data transfer. Then a high order memory address selection means 30 selects alternatively the page addresses given from those page address registers in a prescribed sequence and outputs these selected addresses as the higher order memory addresses. In such a constitution, the data can be continuously transferred at a high speed even in a DMA data transfer mode for the discontinuous storage area. In addition, the CPU throughput is improved without giving any load to the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for controlling DMA data transfer in a computer system equipped with a virtual memory or address translation mechanism.

[Prior Art] In a virtual memory system, as shown in Fig. 3, a virtual memory space (
A) and the real memory space obtained from the actual storage device (B)
These memory spaces (A) and (B) are pages! It is associated with the 114th position (for example, the 18th byte memory block). Usually, virtual memory space (A
) pages PO, P1 . ．． P2.
... are randomly arranged in the real memory space (B). Then, the address in the virtual memory space (A), 1- is translated into the address in the real memory space (B), 1, by an address translation mechanism during the execution stage of the CPU.

In such a system environment, when data is transferred by MA (random memory access), the program (virtual memory space (A)
)-J-, consecutive pages P+, Pj,...
Even if it is specified that memory access for data transfer is to be performed across discontinuous vanes P I + P j'+ ... in reality (actual memory space (B)), memory access for data transfer is is often done.

A conventional control device for performing such MA data transfer is equipped with an address counter for generating a memory address for the real memory space (B), and has an address counter for generating a memory address for the real memory space (B).
As soon as the memory access for Pl′) is completed, D
M Aborts the data transfer, notifies the CPU of this, and sends the CPU the initial address value A of the next vane (Pj').
J' is set in the address counter and the data transfer request source is reset.

[Problem to be solved by the invention] The CP aborts data transfer every time one page worth of memory access is completed, as in a double case.

Having U perform the setting process does not reduce the speed of DMA data transfer, increases the load on the CPU, and reduces throughput.

The present invention has been made in view of such problems, and is a DMA control method that enables high-speed data transfer without multiplying the CPU in a computer system equipped with a virtual memory or an address conversion mechanism. 3===4 The purpose is to provide a device.

[Means for Solving the Problems] In order to achieve the object described in item 1-, the DMA control device of the present invention provides the following method for storage areas arranged at random addresses in the middle of pages in a storage device: 1) According to M.A. I) M A data transfer control device for controlling data transfer includes an address counter that generates an address within a page as a lower memory address, and an address counter that each holds the addresses of multiple pages to be accessed in DMA data transfer. a plurality of registers, and a second memory address selection means for selectively selecting page addresses respectively given from the plurality of registers in a predetermined order and outputting them as a -1- memory address; The configuration includes the following.

In addition, in order to support DMA data transfer that accesses many pages with a small number of registers, when the address counter finishes outputting one page's worth of addresses, it is detected and the CPU receives a new page address. The configuration includes means for notifying that the data should be loaded into a predetermined register.

In addition, to prevent DMA data transfer when all page addresses held in registers are invalid (used), each page address stored in each register is shown whether or not it is used. Based on the flag bits in the upper address flag register that stores the flag function bit (byy) and the flag bit in the second address Φ flag register, if all page addresses are already used, the The configuration includes means for masking requests.

[Operation] For example, if one page is 16 Kbytes and the real memory space of the storage device is 16 Mbytes, the number of pages in this memory space, that is, the number of page addresses is IK (1024
).

Software-1 Multiple consecutive pages P i, P
When performing DMA data transfer over L...Pq, = 6 - the address of multiple vanes P+', PJ' and one song Pq' in the real memory space corresponding to those pages (usually consecutive (randomly arranged) can be obtained from a page table, etc.

These page addresses are each loaded into a plurality of registers of the control device of the present invention by the CPU. However, 1. I) When performing data transfer by MA, the upper memory write address selection means sequentially selects the 1/sister holding the page Φ address of the page Pxl to be accessed, and provides it to the memory as the 1st address. on the other hand,
The address counter generates an address within a page as a memory address and provides it to memory. −
The switching of the upper address and the generation cycle of the lower address are synchronized, and when the address counter finishes generating addresses for one page (lower address), the upper address selection means changes to 1-
The first address (page address) is switched to the next one-place address, and the address counter starts generating addresses for one page again from the initial value.

As described above, in the control device of the present invention, the addresses of pages to be used for DMA data transfer are held in advance in the register, and they are selectively selected in a predetermined order and the -L upper address is output at the same time. Since lower addresses than the address counter are output periodically for each page, data can be transferred continuously and at high speed without interruption between pages even when transferring data to discontinuous storage areas. Moreover, since no load is placed on the CPU, the throughput can be increased by -1.

Also, each time the address counter finishes outputting a lower address for one page (that is, each time one page is accessed or completed), the CPU should load a new (successful) page address into the register. It is possible to update the page address held in the register by notifying the
It can also handle MA transfer.

In addition, a -7= upper address flag is provided, and based on the contents of the flag, if all of the -7= vane addresses stored in the register are invalid, transfer requests from the transfer request source are masked. By doing so, malfunctions can be prevented and the reliability of DMA control can be maintained.

[Example] Please refer to Figures 1 and 2! ((A) A DMA control device according to an embodiment of the present invention will now be explained.

First, as shown in FIG. 2, the DMA controller 10 of this embodiment connects the CPU 16 . It is connected to the memory 18 and the peripheral device (for example, a floppy disk drive) 20 that is the source of the transfer request, and is also individually connected to the CPU 1f3.
A control line 50°52 is wired between the terminal and the peripheral device 20, and a control line 5415B is wired between the peripheral device 20 and the peripheral device 20. In this computer system, the DMA control device 10 controls the CPU 1 when transferring data from the memory 18 to the peripheral device 20, or conversely from the peripheral device 20 to the memory 18.
An address signal is sent to the memory 18 instead of 6.

This computer system employs a virtual storage mechanism; for example, the real memory space of the memory 18 is 16 MB,
1 Pe-7 is 16 bytes.

Therefore, the address signal is 24 bits, and the address signal is 24 bits.
The second 10 bits give the (starting) address of the page, and the 14th bits give the intra-page address. As will be described later, I) The MA control device 10 separately generates the 1st-order address (10 bits) and the lower address (14 bits), and combines them into a 24-bit address signal.

FIG. 1 shows a specific example of the circuit configuration of the main parts of this DMA control device 10. As shown in FIG.

N page-address registers RGO, RG1 . . . . RGn-1 has its respective input terminals connected to CPUIEf, and its respective output terminals connected to the input terminals of the upper address selector 30.

These page address registers contain each DM
Should be used (accessed) in A data transfer
The page address of each page in real memory space (
10 bits) is loaded from the CPU 1e under the active state of the intoxication control signal WR. At that time, registers RGO and RGI are set according to the order of use (access) of each page.
, . . . Vane fist addresses are loaded in the order of RGn-1. Therefore, if the number of pages used is M, then when M>N (number of page address registers), the trailing registers (RGn-1, etc.) are left over, and M<H
In this case, the l nozzle is insufficient. However, in this latter case, as soon as the first registers RGO, RGI, etc. are used up, the subsequent new page address is loaded into them by the control described below. There is.

Also, each time a Vane fist address is loaded into each Vane address register RGi, the CPU 16 loads that register R
The flag bit of the upper address flag-register 32 corresponding to G+ is set (set to "1"). This flag register 32 is the number (N) of page address registers RGo, RGI, -RGn-1.
It has an N-bit capacity corresponding to .

The 1st to 4th address selector 30 selects one of the vane addresses received from the page address registers RGO, RGI, . . . in accordance with the progress of I) MA data transfer. , and outputs it to the address bus 1.2.1: as the 1st address (10 bit address) of the 24 bit address signal. In this embodiment, the address of each page is held in the registers RGO, RG I, . . . in the order of DMA use (access) as shown in L. It will be switched in the order of RGI, . . . The sequence and timing of this switching is controlled by the -1- position address controller 36, as will be described later.

The lower address counter 34 has one page worth of atto L/
This is an address counter that periodically generates a lower address (14 bits).

The lower address from this counter 34 is applied to the address bus 121-, and
is provided to controller 36.

The −1− address meeting controller 36 sets the lower address to the final value for one page (it On or “16K”).
"), it is detected and a switching signal SW is given to the upper address selector 30. When the selector 30 receives the switching (,;
Switch register RG+ to the next register RG j+I. As a result, the "-" address is switched to the value of the start address of the next page.

If these two successive pages are discontinuous in the memory space, the -higher address will jump from the end address of the previous page to the start address of the next page.

Furthermore, since the upper address for one page has been output, that is, the access for one page has been completed, the controller 36 outputs - upper address - for the page address register RG+ that has become used (accessed). Flag - Set the corresponding flag bit in register 32 to “0”
”. Then, when the number N of page address registers is smaller than the number M of pages used in the DMA data transfer, the controller 36 assigns a subsequent new register to the used register RGi. A page address rewrite request signal is sent to the CPU 16 to load the page address.

On the other hand, the address counter 34 is set when the generation of the upper address for one page is completed, and outputs the lower address for one page again from the initial value. This lower address is combined with the first address output from page address register RG I+1 via upper address register 30 and sent on address bus 12 and then to memory 18.

The transfer request controller 38 controls the transfer request mask circuit 40 based on the flag bit contents of the flag register 32 at the first address. That is, as long as even one of the flag bits is set (as long as there is an unused page address register RGX), when an external transfer request signal RQ is received from the peripheral device 20 that is the source of the transfer request, this In response to =14-, the transfer request mask circuit 40 sends an acknowledge signal ACK back to the peripheral device 20.

A command signal CM for instructing other parts in the control device to perform transfer control is output. However, when all of the flag contention bits are down (when there is no valid vane address register RGX), it acts on the transfer request controller 38 or the transfer request mask circuit 40 to mask the external transfer request signal RQ, Acknowledge signal ACK is also transfer command signal R
Do not output Q either. This causes the vane-address registers RGO,...RG n-
1. When no valid (unused) page address is stored, even if an external transfer request comes from the transfer request source, it will be accepted (it will not be 1 digit).

As described above, in the system of this embodiment, the address of the page in the real memory space to be used in DMA data transfer is
Page address register RGo, R from PU1f3
G+,...RGn-1 is loaded in advance, and during transfer, the address within one page (lower address) is output from the lower address counter 34, and at the same time, the 1st address controller 36 and -1-
Register RGO is controlled by address selector 30.
, RG+, . . . RGn-1 are alternatively selected, and the address of the vane to be accessed is output as a -higher address. As a result, even if the I)AM data transfer is for multiple pages discontinuously arranged in the real memory space of the memory 18, the transfer may be interrupted between pages just by momentarily switching the register. The CPU 1.
e throughput can be increased.

In addition, each time an access for one page is completed, the upper address controller 36 and the CPU 16 are requested to load (replenish) the subsequent page address. or vane address register RGO,
Even if the number of RGI, . . . RGn-1 (number of installed units) is small, no problem will occur.

Furthermore, a "-address Φ flag register 32 is provided, and based on the contents of the flag bit, each page address held in the page address registers RGO, RGI,...RGn-1 is Manage valid (unused)/invalid (used), especially all pages.
When the address is invalid, transfer requests from the transfer request source are masked to prevent malfunctions and
) M A control's 41.: axis property can be ensured.

[Effects of the Invention] By having the above-described configuration, the present invention provides the following effects.

According to the I) MA control device of claim 1, addresses of a plurality of pages to be used for DMA data transfer are held in a plurality of registers in advance, and those page addresses are selected by the first address selection means. By selectively selecting in a predetermined order and outputting the first address, and at the same time outputting lower addresses from the address counter periodically for each page, I
) According to the DMA control device of claim 2, the DMA control device is characterized in that it enables continuous and high-speed data transfer even in MA data transfer, and does not place a burden on the CPU. Every time the output of one page's worth of lower addresses is finished (that is, every time one page's worth of access is completed), the CPU is notified that a new (successful) page address should be loaded into the register. , even when the number of pages used in DMA transfer is large, it can be handled with a small number of registers.

According to the DMA control device of claim 3, when all the page addresses stored in the register are invalid, the transfer request is made based on the contents of the flag contention bit of the upper address flag register. Since the original transfer request is masked, malfunctions can be prevented, and r) MA control
= It is possible to ensure reliability.

= 17

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a specific circuit configuration of the main parts of a DMA control device according to an embodiment of the present invention, and FIG. FIG. 3 is a memory space diagram showing the memory space of the virtual storage system. FIG. 4 is a memory space diagram illustrating DMA data transfer in the virtual storage system. 10...DMA control device, 16...CPU
. 18...Memory, 20...Peripheral device, RG
O~RGni...Page association address register,
30... Upper address register, 32...
” 1st address flag register, 34: address Φ counter, 38: transfer request controller, 40: transfer request mask circuit.

Claims (3)

[Claims] (1) DM for controlling data transfer using DMA (Direct Memory Access) for storage areas arranged at random addresses in page units within a storage device
A control device includes an address counter that generates an address within a page as a lower address, a plurality of registers each holding addresses of a plurality of pages to be accessed by DMA, and a page held in each of the plurality of registers. - A DMA control device comprising: upper address selection means for selectively selecting addresses in a predetermined order and outputting the selected addresses as upper addresses. (2) It includes means for detecting when the address counter has finished outputting addresses for one page and notifying the CPU that a new page address should be loaded into a predetermined register. Characteristic DMA control device. (3) an upper address flag register that stores flag bits indicating whether each of the page addresses stored in the plurality of registers has been used; and a flag bit of this upper address flag register; A DMA control device comprising means for masking a request from a data transfer request source when all page addresses are used based on the above.