JPS622677Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is a key-controlled digital operation system that generates a key input sound to indicate that the key input has been made correctly when information is input into the device as a result of key operation. Regarding equipment.

[Technical background of the invention and its problems]

Generally, electronic calculators are configured to drive a buzzer or the like to generate a key input sound for a certain period of time so that the operator can check whether information has been input correctly when key operations are performed. However, if the keys are operated at a speed faster than the time during which the key input sound is generated, the key input sound continues, making it impossible to confirm the key input.

Therefore, in order to prevent the key input sounds from continuing even if the keys are operated quickly, a system described in Japanese Utility Model Publication No. 1983-344 has been devised. This device is configured so that if the next key is operated while the key input sound of the last key operated is being generated, the previous key input sound is stopped, and then the next key input sound is generated after a certain period of time has elapsed. .

However, in such a configuration, at least when a key is input, a determining means is required to determine whether or not the input sound from the previous key is being generated.
Furthermore, if the next key operation is performed immediately after the key input sound of the previous key ends, the key input sound will be generated for a certain period of time immediately after the key operation, so the key input sound is not continuous, but the stop time Since the sound is short, the operator hears it as a continuous sound.

Furthermore, in order to output the key input sound from the speaker, an oscillation circuit that outputs a drive signal is required, making the circuit configuration complicated.

[Purpose of invention]

The present invention was developed in view of the above-mentioned drawbacks, and when a key operation is performed, it is not necessary to judge whether or not the key input sound caused by the most recently operated key is being generated, and the present invention is made immediately after the key input sound caused by the most recently operated key ends. To provide a key-controlled digital arithmetic device which prevents the inconvenience that a continuous sound is heard even when the next key operation is performed, and which does not require a unique oscillation circuit for outputting a key input sound.

[Summary of the idea]

The key-controlled digital arithmetic device of the present invention has a key for inputting numerical values or information related to arithmetic operations, and when the key is operated, information is introduced and when the key is operated, a key input sound is generated. In a key-controlled digital computing device configured to generate a key input sound, when the key is operated, means for stopping the generation of a key input sound regardless of whether or not a key input sound is being generated; This configuration is characterized by comprising means for generating a key input sound by operating the key after a predetermined period of time has elapsed after the stop operation.

[Example of idea]

Next, one embodiment of the present invention will be described based on the drawings. In this embodiment, the present invention is implemented in an electronic cash register (hereinafter referred to as ECR).

Figure 1 is a configuration diagram of ECR, and in this diagram,
1 is the main central processing unit (hereinafter referred to as MCPU)
ROM 2, RAM 3, keyboard 4, a printer control circuit 6 that controls the printer 5, and a drawer 7.
is under control. 8 is the sub-central processing unit (hereinafter referred to as
The MCPU is connected to four data buses 9, one CS signal line 10 for transmitting data, and one ACK signal line 11 for transmitting data reception.
1, and controls a display unit 12 consisting of a display control circuit and a display device for dynamically displaying based on data transmitted from the MCPU 1, and a buzzer 13 that generates a key input sound.

Figure 2 shows the RAM installed in DCPU8.
It is provided with a display buffer A for storing display data, a digit signal memory B for indicating the display digits of the display, an error flag C for continuously sounding the buzzer 13, and a counter D for sounding the buzzer 13 for a certain period of time.

Next, the operation of this embodiment will be explained.

Transfer data from MCPU1 to DCPU8 in the third
This will be explained based on the diagram.

First, the MCPU 1 sets the first data of the period transfer data shown in parentheses in FIG. The output signal of the signal line 10 is converted from "L" level to "H" level.

When the CS signal rises, the DCPU 8 reads the data set on the data bus 9 as shown by the arrow in FIG. 3d, and then outputs the output signal on the ACK signal line 11 as shown in FIG. Converts from "L" level to "H" level.

Next, MCPU1 ACKs the ACK as shown in Figure 3c.
When the output signal of the signal line 11 rises, the second data of the period transfer data shown in parentheses is set on the data bus 9. Thereafter, this data is repeatedly transferred a predetermined number of times n to the DCPU 8 up to the final data of the transfer data. Note that the CS signal and the ACK signal are converted from "L" level to "H" level in the case of odd numbered data, and from "H" level to "L" level in the case of even numbered data.

The data transferred in this way is transferred to DCPU8.
Stored in RAM.

Next, the operation of the DCPU 8 based on the memory in the RAM will be explained based on FIGS. 4 to 6.

It is assumed that the display section 12 has a 10-digit display, and that the error flag C and buzzer flag are not set at first, so that the counter D is 0.

First, at 21, the digit signal n stored in the digit signal memory of the RAM is set to 10, and at 22, the display buffer A is set to 10.
The display unit 12 is controlled so that the data stored in the n-th digit is displayed in the n-th digit of the display.

Next, in step 23, it is determined whether or not the error flag C is set.
It is determined whether the counter D is 0 or not. Since the counter D is 0, the buzzer signal for operating the buzzer 13 is reset at step 32.

Next, at 27, the display unit 12 is controlled so that the display of the n-th digit is erased, and after that, at 28, the CS signal is monitored to see whether it is at the "H" level, that is, whether data is being transferred from the MCPU 1. Decide whether or not.

Here, if the CS signal is at "L" level, 2
At step 9, calculate n-1, and at step 30, check whether n is 0 or not.
That is, it is determined whether the display of all digits has been completed based on the memory of the display buffer A, and if it has not been completed, the process returns to 22 and displays each digit in sequence.
If it has been completed, the process returns to step 21 and the display operation is repeated again based on the same data.

Further, if the CS signal is at the "H" level at 28, the buzzer signal is reset at 33, and as described above, the transfer data from MCPU1 is input from the first data to the final data at 34 to 39, and the RAM
to be memorized.

Next, the presence or absence of an error flag in the transferred data is determined at 40, and if there is no error flag, 41
After resetting the RAM error flag C with
At 2, it is determined whether there is a buzzer flag in the transferred data, and if there is no buzzer flag, the RAM counter D is cleared at 45, and the process returns to 21. Thereafter, the data stored in the display buffer A is dynamically displayed on the display in the same manner as described above.

Also, if the error flag is set at 40,
After setting the RAM error flag C in step 4, step 2
Return to 1. Since the error flag C has been set, the subsequent operation differs from the above description, and after performing a delay operation at 31, the buzzer signal is inverted at 26. Then, the CS signal becomes “H” level again.
Unless data is transferred from the MCPU 1, the contents of the display buffer A are sequentially displayed digit by digit on the display section 12, and in synchronization with the display of each digit, the buzzer signal is inverted to generate an oscillation waveform. Buzzer 13
drive and notify errors. In addition, the delay operation in 31 determines whether or not the memory content of the counter D is 0 in 24, and in 25 the delay operation is performed by the time that occurs when subtracting 1 from this memory content, and the lighting time of the display is kept constant. This is to keep it safe.

Also, if the buzzer flag is hit at 42, 43
After setting the RAM counter D to an initial value, for example 100, the process returns to step 21. This initial value is buzzer 1
3 for a certain period of time, and can be changed arbitrarily depending on the ringing time; if the initial value is large, the ringing time is long, and if it is small, the ringing time is short. Since the counter D is not 0 in the subsequent operation, unlike the above explanation, 1 is subtracted from the stored contents of the counter D at 25, and the buzzer signal is inverted at 26. Then, the contents of the display buffer A are sequentially displayed digit by digit on the display section 12, unless the stored contents of the counter D become 0 or the CS signal becomes "H" level again and no data is transferred from the MCPU 1. In addition, in synchronization with the display of each digit, the buzzer signal is inverted to generate an oscillation waveform to drive the buzzer 13 and generate a key input sound.

Therefore, normally when the key _K1 of the keyboard 4 is operated as shown in section A of Fig. 6, the MCPU
After the time _t1 required to transfer data to make the buzzer 13 sound for a certain period of time from the DCPU 8 to the DCPU 8, the buzzer 13 starts sounding, and the key input sound is determined by the initial value set at 43 in FIG. time t ₂
only to occur.

Furthermore, as shown in section B of FIG. 6, the key input sound for the operation of the key _K2 is generated before the time _t1 + _t2 has elapsed after the key _K2 of the keyboard 4 is operated. If the key _K3 is operated during this time, the key input sound is temporarily stopped, and after the time _t1 required for the data transfer has elapsed, a key input sound corresponding to the operation of the key _K3 is generated.

In addition, if the key _K4 of the keyboard 4 is operated as shown in section C of FIG. 6, and the key _K5 is operated immediately after the key input sound corresponding to this key _K4 ends, the data transfer is After the required time _t1 has elapsed, a key input sound is generated in response to the operation of the key _K5 .

In this way, when the key input sound is generated due to the previous key operation, or even if the key operation is performed immediately after the key operation has stopped, the sound will always be heard from MCPU1 to DCPU8.
Since the key input sound stops during the time required for the data transfer to occur, the key input sound will not be heard as a continuous sound.

Next, another embodiment will be described based on FIGS. 7 to 9.

Figure 7 is a circuit diagram of the present invention.
1 is a keyboard, 52 is a CPU, and 53 is a display section. The keyboard 51 outputs a key signal based on the operated key, and this key signal causes the CPU to
52 is the digit signal line S ₁ as shown in FIG. 9 T ₁ to _{T o}
The display data of the designated digit is outputted in synchronization with the digit designation signal of the "H" signal which is sequentially outputted to Sn, thereby causing the display section 53 to display the data.

54 is a differentiation circuit that differentiates the key signal and outputs a differential signal; 55 is a first timer circuit that outputs an "H" signal for a predetermined time from the rise of the differential signal; 56
is a retrigger type second circuit which outputs an "H" signal for a predetermined period of time after the fall of the output of the first timer circuit 55.
57 is a flip-flop which is inverted at the rising edge of the digit signal inputted through the diode 58 and outputs the waveform shown in FIG. be.

Next, the operation of this embodiment will be explained based on FIG.

In FIG. 8, K ₁ to _{K 5} are key signals, Q ₀ is the differentiating circuit 54, T ₁ is the first timer circuit 55,
T ₂ is the output of the second timer circuit 56, and _{T 1} is the output of the inverter 59. B is an AND result of the second timer circuit 56 and the inverter 59, and while the B signal is at the "H" level, the AND gate 60 is opened and the output of the flip-flop 57 shown in FIG. During this period, the driver 61 is operated and the buzzer 62 is activated to allow the
is driven and outputs a key input sound.

Normally, as shown in section A, when the key _K1 of the keyboard 51 is operated, one input terminal of the AND gate 60 is connected to the first Since the "L" signal is input during the time _t1 set by the timer circuit 55, the AND gate 60 is closed, and therefore the output of the flip-flop 57 is connected to the driver 6.
1 is not input, and the buzzer 62 is not sounded.

And when t ₁ hour has passed since the operation of key K ₁ ,
The output of the first timer circuit 55 becomes "L" level, and the output of the second timer circuit 56 becomes "H" level, so the two inputs of the AND gate 60 become "H" level, and the output of the flip-flop 57 becomes "H" level. Driver 61 via AND gate 60
This signal drives the buzzer 62 to sound and emit a key input sound. This key input sound is emitted for a time _t2 until the output of the second timer circuit 56 reaches the "L" level.

Further, as shown in section B of FIG. 8, the key _K2 may be pressed before the time _t1 + _t2 has elapsed after the key K2 is operated, that is, while the key input sound for the key _K2 operation is being generated. When operation ₃ is performed, the differential circuit 54
outputs a differential signal, and therefore the AND gate 60 is closed during _t1 via the first timer circuit 55 and the inverter 59. During this period, the output of the flip-flop 57 is not input to the driver 61, so the buzzer 62 is turned off. It doesn't ring. Then, after ₁ hour t, the output of the inverter 59 becomes "H" level and the second timer circuit 56 is retriggered by the fall of the output of the first timer circuit 55, so the key input by operating the key _K3 Sound is generated for t ₂ hours.

Furthermore, as shown in section C in Figure 8, if key K5 is operated immediately after the end of the key input sound due to the operation of key _K4 , _the key input sound due to the operation of key _K5 will be the same as in section A. Since it is the same, the time t set by the first timer circuit 55 is the time after ₁ elapse.
Makes a key input sound for t ₂ .

In this way, even when the key input sound is generated due to the previous key operation, or even if the key operation is performed immediately after the key operation has stopped, the time t ₁ set by the first timer circuit 55 is always the key input sound. stops, so you won't hear the keystrokes as a continuous sound.

[Effect of idea]

According to the present invention, even if a key operation is performed while the key input sound is being generated due to the previous key operation or immediately after the key operation is stopped, the key input sound is always stopped for a certain period of time and then the key input sound based on the next key operation is generated. Therefore, even if the key operation speed is increased, the key input sound will not be heard continuously, and it can be reliably determined whether data by key operation has been input correctly.

Furthermore, by using a signal synchronized with the display digit signal as the buzzer drive signal, there is no need to provide an oscillation circuit to drive the buzzer, and the circuit configuration can be simplified.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an embodiment of the key-controlled digital computing device of the present invention, and Figure 2 is a DCPU.
3 is an explanatory diagram of data transmission between the MCPU and DCPU, FIGS. 4 and 5 are flowcharts showing the operation of the DCPU, FIG. 6 is an explanatory diagram showing the operation of this embodiment, and FIG. FIG. 7 is a block diagram showing another embodiment of the present invention, and FIGS. 8 and 9 are explanatory diagrams showing the operation of the same. 1...Main central processing unit, 4,51...Keyboard, 8...Sub central processing unit, 12,53...
... Display section, 13, 62 ... Buzzer, 52 ... Central processing unit, 54 ... Differentiation circuit, 55 ... First timer circuit, 56 ... Second timer circuit, 57
...Flip-flop, 59...Inverter, 6
0...and gate.

Claims (1)

[Claims for Utility Model Registration] (1) It has a key for inputting information related to numerical values or calculations, and when the key is operated, information is introduced, and when the key is operated, a key input sound is generated. In a key-controlled digital computing device configured to generate a key input sound, when the key is operated, means for stopping the generation of a key input sound regardless of whether or not a key input sound is being generated; A key-controlled digital arithmetic device comprising means for generating a key input sound by operating the key after a predetermined period of time has elapsed after the stop operation. (2) Utility model registration claim 1, characterized in that the key-controlled digital arithmetic device is equipped with a display section that dynamically displays data, and the key input sound is synchronized with the digit signal of the display section. The key-controlled digital arithmetic device described in Section 1.