JPS6220707B2 - - Google Patents
Info
- Publication number
- JPS6220707B2 JPS6220707B2 JP5344481A JP5344481A JPS6220707B2 JP S6220707 B2 JPS6220707 B2 JP S6220707B2 JP 5344481 A JP5344481 A JP 5344481A JP 5344481 A JP5344481 A JP 5344481A JP S6220707 B2 JPS6220707 B2 JP S6220707B2
- Authority
- JP
- Japan
- Prior art keywords
- chips
- substrate
- layers
- chip
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5344481A JPS57166051A (en) | 1981-04-06 | 1981-04-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5344481A JPS57166051A (en) | 1981-04-06 | 1981-04-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57166051A JPS57166051A (en) | 1982-10-13 |
| JPS6220707B2 true JPS6220707B2 (enExample) | 1987-05-08 |
Family
ID=12943019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5344481A Granted JPS57166051A (en) | 1981-04-06 | 1981-04-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57166051A (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139014U (enExample) * | 1985-02-18 | 1986-08-28 | ||
| US4628406A (en) * | 1985-05-20 | 1986-12-09 | Tektronix, Inc. | Method of packaging integrated circuit chips, and integrated circuit package |
| US5014161A (en) * | 1985-07-22 | 1991-05-07 | Digital Equipment Corporation | System for detachably mounting semiconductors on conductor substrate |
| AU598253B2 (en) * | 1986-05-07 | 1990-06-21 | Digital Equipment Corporation | System for detachably mounting semi-conductors on conductor substrates |
| JPH07297560A (ja) * | 1994-04-28 | 1995-11-10 | Hitachi Ltd | 多層プリント配線基板およびその実装構造体 |
| JP3252635B2 (ja) * | 1995-01-13 | 2002-02-04 | 株式会社村田製作所 | 積層電子部品 |
| WO1998004000A1 (fr) * | 1996-07-22 | 1998-01-29 | Honda Giken Kogyo Kabushiki Kaisha | Unite de commande electronique de type enfichable, structure de connexion entre un tableau de connexion et des fiches, unite de connexion entre des pieces electroniques et un tableau de connexion et procede de montage de pieces electroniques |
| US7615476B2 (en) | 2005-06-30 | 2009-11-10 | Intel Corporation | Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages |
-
1981
- 1981-04-06 JP JP5344481A patent/JPS57166051A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57166051A (en) | 1982-10-13 |
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