JPS62204566A - Complementary mos semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a latch up from occurring by preventing the insulation-isolating characteristics from deteriorating while restraining the base node voltage change of parasitic thyristor from occurring by a method wherein impurity regions in the impurity concentration two figures higher than that of a semiconductor substrate and a well region are provided on the interconnection layer insulation-isolating respective MOS transistors and respective boundaries between the semiconductor substrate and the well region. CONSTITUTION:Within a CMOS semiconductor device, polycrystalline interconnections 45-50 formed through the intermediary of a thin oxide film 13 are fixed to a field region at the same potential as that of an N-type semiconductor substrate 11 in a P-type channel MOS side region likewise at the same potential as that of a P-type well region 12 in an N-type channel MOS side region. Furthermore, in the boundary part on the P-type well region 12, N<+> type impurity regions 20, 21 in the concentration two figures higher than that of the N-type semiconductor substrate 11 and at the same potential as that of said substrate 11 are provided likewise in the boundary part on the N-type semiconductor substrate 11, P<+> type impurity regions 22, 23 in the concentration two figures higher than that of the P-type well region 12 and at the same potential as that of said well region 12 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary MO3417J body device, in particular,
Complementary MO with element isolation structure that improves radiation resistance
S related to semiconductor devices.

[Conventional technology]

As a conventional complementary MOS semiconductor device (hereinafter referred to as CMO3), there is one shown in FIG. 3, for example.

In FIG. 3, 111 is an N-type silicon substrate, 112 is a P-type well region, and 113 is an N-type silicon substrate.
S4! Field of l region: f+1 film 114 (
(described later) P as a channel stopper formed at the bottom
The type scattering layer region 114 is a thick field oxide film formed by LOCO3 method, 115.116 is a thin gate oxide film formed by thermal oxidation method, 117.118 is a phosphorus-doped polycrystalline silicon gate electrode, 119 .120.1
21 is an N-type scattering layer region 122.123.1 which becomes the source/drain region of the N-channel MOS transistor.
24 is a P° type scattered layer region 125 which becomes the source/drain region of a P channel MO3 transistor, and a silicon oxide film grown by vapor phase growth as an insulating layer between the eyebrows; 126.1
27 is an aluminum wiring layer.

In the above CMO5I-transistor, the polycrystalline silicon gate electrodes 117 and 118 are connected to the input, and the source and
By connecting the drains of the drain regions 119 to 124 to the output, and connecting one source of the N-channel or P-channel to the voltage RV o o and the other source to the ground, the N-channel and P-channel MOS transistors are connected. A series connection configuration can be obtained. In this configuration, either the N-channel or P-channel MOS transistor can be turned on and the other turned off, allowing use with low power consumption.

[Problem that the invention seeks to solve]

However, according to conventional CMOS semiconductor devices, when used in a radiation environment, electron pairs are generated due to radiation irradiation, and holes among them are transferred to the thermal oxide films of the field oxide film 114 and gate oxide film 115 and 116. When trapped, positive fixed charges increase and interface states are generated at the thermal oxide film/silicon interface, which is disadvantageous. Since this tendency becomes more pronounced as the thermal oxide film becomes thicker, the insulation isolation characteristics of the field oxide film 114 may deteriorate, resulting in an increase in leakage current or even destruction of the device.

In addition, when a large number of electron-hole pairs are generated by the incidence of radiation from high-energy heavy ion particles such as F, a voltage change occurs at the base node of the parasitic zyristor, causing latch-up, until the power supply voltage is disconnected. Because a large current flows, the device may be destroyed.

c. Means for Solving Problems] The present invention has been made in view of the above, and in order to prevent deterioration of insulation isolation characteristics, a first conductivity type semiconductor substrate and a second conductivity type semiconductor substrate formed on this substrate are provided. A thin oxide film is formed at the same position and level as the gate oxide film of the first and second MO3I-transistors of the first and second conductivity types formed in the well regions of the conductivity type, and the semiconductor substrate and the CMOS with a wiring layer connected to the same potential as the well region
The present invention provides a semiconductor device.

In addition, even if a large number of electron-hole pairs are generated, in order to collect them and suppress the voltage change at the base node of the parasitic silicon risk and prevent launch-up, a
and electron-hole pairs of an impurity region having the same electric type and potential as the semiconductor substrate or the well region, and having an impurity concentration at least two orders of magnitude higher than the semiconductor substrate or the well region, at least at the boundary between the semiconductor substrate and the well region. A CMOS semiconductor device provided with a collection layer is provided.

〔Example〕

Hereinafter, the CMOS semiconductor device of the present invention will be explained in detail.

FIG. 1 shows an embodiment of the present invention, in which 11 is an N-type silicon substrate, 12 is a P-type well region, 13 is a thin silicon oxide film formed in the field region, and 20.21 is inside the N-type silicon substrate 11. The substrate 11 formed in the P-type well region in
22.23 is an I] type well 12 formed in the field region at the boundary with the N type silicon substrate 11 within the P type well region 12; P-type well 12 at a concentration more than two orders of magnitude higher than
P゛゛ impurity region with the same potential as 35, 36.37.38
．． 39 is a higher concentration N-type element 97 area than the substrate 11 formed under the thin field oxide film 13 in the P-channel MO3 side region, 40.41.42.43.44
is the thin field oxide film 1 in the N-channel MO3 side region.
P-type impurity regions 45, 46, and 47 with a higher concentration than the P-type well 12 formed under the substrate 1 are formed on the thin field oxide film 13 in the P-channel MO3 side region.
Phosphorus-doped polycrystalline silicon wiring at the same potential as 1, 4
8.49.50 is a phosphorus-doped polycrystalline silicon wiring formed on the thin field oxide film 13 in the N-channel MO3 side region and has the same potential as the P-type well 12, and 52 is a polycrystalline silicon wiring 45 formed by thermal oxidation. .46.47.48
．． 49.50 is a silicon oxide film formed as an interlayer insulating layer, 53.54.55.56 is a thin gate oxide film formed in the element formation region by thermal oxidation, and 57.58 is a phosphorus-doped polycrystalline film. Silicon gate electrode, 59.60
．． 61 is the source of the P-channel MOS transistor.
P1 type diffused M region which becomes the drain region, 62.63.6
4 is a N-type scattering layer region 65, which becomes the source/drain region of the N-channel MO3I-run risk, is a phosphor glass layer grown by vapor phase growth as an insulating layer between the eyebrows, 66.67.6
Reference numerals 8, 69, 70, and 71 are contact openings for taking out electrodes, and 72.73 is an aluminum wiring layer.

In the above CMO3 semiconductor device, the field region connects the polycrystalline silicon wirings 45 to 50 formed through the thin oxide film 13 to P channel MOS (11,!I
The N region is fixed at the same potential as the N-type semiconductor substrate, and the N-channel MO5 side region is fixed at the same potential as the P-type well. In addition, P of the P channel MOS side field area
At the boundary with the N-type well region 12, an N°° impurity region 20.21 is formed which is at least two orders of magnitude higher in temperature than the N-type soil substrate and has the same potential as the N-type semiconductor substrate. Among them, P is located at the boundary with the N-type semiconductor substrate.
P' impurity regions 22 and 23 are formed at a temperature two or more orders of magnitude higher than that of the P-type well region 12 and at the same potential as the P-type well region 12.

Therefore, the field region does not require a thick LOGO3 region and is formed of a thin oxide film 13, so that it is possible to reduce the deterioration of the insulation isolation characteristics due to an increase in the amount of radiation irradiation. In addition, the P-type scattering layer region which becomes the source/drain region of the P-channel MO3I-run risk, the N-type semiconductor substrate, the P-type well region, and the N-channel MO3! -N which is the source train area of run risk
F to the parasitic sirisk composed of the °-type scattering layer region. Even if a large number of electron-hole pairs are generated by the incidence of radiation from high-energy heavy ion particles such as At the same potential, the p-type impurity region 22.23 has a higher concentration than the P-type/shell region by 21j or more, and the N-type impurity region 22.23 formed at the boundary with the P-type well region in the N-semiconductor substrate at the same potential. Since it is collected in the N' impurity regions 20 and 21, which have a temperature two or more orders of magnitude higher than the substrate, it is possible to suppress the voltage change at the base node of the parasitic silicon risk and prevent a launch amplifier.

Next, the method for manufacturing a CMOS semiconductor device of the present invention will be described in a second manner.
This will be explained using figures (al to (hl).

In FIG. 2(a), after forming a P-type well region 12 on an N-type silicon substrate 11, a thin silicon oxide film 13 is formed on the entire surface of the substrate, and a photoresist 1 is formed by photolithography.
4 is patterned, and 3×10 ”cm-”N of phosphorus is applied by ion implantation through the thin oxide film 13 using the photoresist 14 as a mask at the boundary between the field region on the P-channel MOS side and the P-type well region 12.
phosphorus implantation region 15
．． form 16.

FIG. 2 (in BL, after removing the photoresist 14, a new photoresist 17 is patterned by photolithography and the N-channel MO3 side field 11)
Using the photoresist 17 as a mask, thin oxide Jl! Boron is implanted into the 3.times.10@15 cm@-2p type well region 12 by ion implantation through 14 to form implanted regions 18.19.

In FIG. 2 fc), after removing the photoresist 17, a heat treatment is performed to anneal the phosphorus implanted region 15.16 and the boron implanted region 18.19, respectively.
A higher concentration of N than the N type substrate 11 and the P type well region 12
゛ type impurity region 20.21 and P ゛ type impurity region 22
．． form 23. Further, after depositing a silicon nitride film 24 and a polycrystalline silicon layer 25 on the entire surface by vapor phase epitaxy, a photoresist pattern 26 is formed by photoetching, and then a photoresist pattern 26 is formed in the field region using this resist pattern 26 as a mask. Crystalline silicon layer 25 and silicon nitride film 24 are removed by etching.

In FIG. 2 (dl), after removing the photoresist 26, a new photoresist pattern 27 is formed by photolithography.
Using the resist pattern 27 and the polycrystalline silicon layer pattern 25 as a mask, phosphorus is implanted into the P channel MO3 side field region through the thin oxide film 13 by ion implantation to a thickness of about I x 10 Izcm-''N type substrate.
implant regions 28, 29, 30.

In FIG. 2 (el), after removing the photoresist 27, a new photoresist pattern 3 is formed by photolithography, and using this resist pattern 27 and the polycrystalline silicon layer pattern 25 as a mask, an N-channel MO3
Boron is implanted into the P-type well region 12 by approximately I.times.10@12 cm by ion implantation through the thin oxide film 13 in the side field region to form boron implanted regions 32, 33.
form 34.

After removing the photoresist 31 and the polycrystalline silicon pattern layer 25 in FIG. , N-type impurity regions 35, 36, 37, 38, 39 and P-type impurity regions 40, 41, 42, 43, 44 are formed with a higher concentration than the N-type substrate 11 and the P-type well region 12. depositing a phosphorus-doped polycrystalline silicon layer;
After forming a photoresist pattern 51 by photolithography, the phosphorus-doped polycrystalline silicon layer is etched away using the resist pattern 51 as a mask to form a phosphorus-doped polycrystalline 9937 layer pattern 45. in the field region.
Form 46.47.48.49.50.

In FIG. 2(g), after removing the photoresist 51, a silicon oxide film 52 is formed on the surface and side surfaces of the phosphorus-doped polycrystalline 9937 layer pattern 45, 46, 47, 48, 49, 50 by thermal oxidation method, Furthermore, using the silicon oxide film 52 as a mask, the silicon nitride film 24 is removed by etching, and the thin thermal oxide film 13 under the silicon nitride film 24 is further etched and removed, and a thin gate oxide film 53.54 is newly etched using a thermal oxidation method. Form .55.56.

FIG. 2 (in hl, polycrystalline silicon gate electrode 57
．． 5B and become the source/drain regions of the N-channel side MO3I-run lister.
63 and 64 are formed by arsenic ion implantation, and P'-type diffused N regions 59, 60, and 61, which will become the source/drain regions of the P-channel side MOS transistor, are formed by boron ion implantation. A phosphorus glass layer is formed by a growth method and contact openings 66, 67, 68 .
69.70.71 is formed by photoetching method,
The aluminum wiring layers 72 and 73 are formed to complete the CMO3 semiconductor device.

In addition, although the above example shows the case where an N-type semiconductor substrate is used, it is also applicable to a P-type semiconductor substrate, and an N-type epitaxial layer is grown on an N-type semiconductor substrate. The same applies to substrates.

In addition, although polycrystalline silicon is used for the wiring layer formed on top of the thin oxide film in the field region, it is also possible to use a high-melting point metal or a double-layer structure of high-melting point metal and polycrystalline silicon. be.

Furthermore, as a thin insulating film used in the field region,
Although a silicon oxide film formed by thermal oxidation is shown, a silicon oxide film, a silicon nitride film, or the like formed by vapor phase growth may also be used.

〔Effect of the invention〕

As explained above, according to the CMO3 semiconductor device of the present invention, the first conductivity type semiconductor substrate and the first and second conductivity type well regions formed in the second conductivity type well region are respectively formed in the first conductivity type semiconductor substrate and the second conductivity type well region formed in this substrate. A thin oxide film is formed at the same level as the gate oxide film of a conductive type MOS transistor, and a wiring layer connected to the same potential as the semiconductor substrate and the well region is provided on this oxide film, which improves insulation isolation characteristics. Deterioration can be prevented.

Further, below the thin oxide insulating film and at least at the boundary between the half-W body substrate and the well region, the semiconductor substrate or the well region has the same electric type and potential, and is at least two orders of magnitude higher than the semiconductor substrate or the well region. Since we have provided an electron-hole pair collection layer in the impurity region with a large impurity concentration, even if a large number of electron-hole pairs are present, they will be collected, suppressing the voltage change at the base node of the parasitic silicon risk, and latch-up. can be prevented.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing one embodiment of the CMO5 semiconductor device of the present invention, FIG. A cross-sectional view showing a CMO3 semiconductor device.
-------P-type well region 20.21------N-type impurity 5M region with a sufficiently higher concentration than one substrate 22.23----- - P+ type impurity region 13 with a sufficiently higher concentration than the well - -1...- Thin field oxide film 3.5.3
6.37.38.39---N-type impurity regions with higher concentration than the substrate 40.41.42.43.44--P-type impurity regions with higher concentration than the well 45, 46, 4. 7--1--Polycrystalline silicon wiring layer fixed to the same potential as the substrate 4B, 49, 50--Polycrystalline silicon fixed to the same potential as the well wiring layer

Claims (1)

[Scope of Claims] A MOS transistor of a second conductivity type formed in a semiconductor substrate of a first conductivity type, and a MOS transistor of a second conductivity type formed in a well region of a second conductivity type formed in the semiconductor substrate. conductivity type M
In a complementary MOS transistor including an OS transistor, the thin oxide insulating film is provided on a thin oxide insulating film formed at approximately the same position level as the gate oxide films of the first and second conductivity type MOS transistors, and A wiring layer that is connected to the same potential as the semiconductor substrate and the well region and insulates and isolates the MOS transistors, and a wiring layer that is connected to the semiconductor substrate and the well region under the wiring layer via the oxide insulating film, and A complementary MOS semiconductor comprising an impurity region provided at least at a boundary of the corresponding semiconductor substrate or the well region, having the same electric type and potential as the corresponding semiconductor substrate or the well region, and having an impurity concentration that is at least two orders of magnitude higher than that of the corresponding semiconductor substrate or the well region. Device.