JPH0328071B2 - - Google Patents
Info
- Publication number
- JPH0328071B2 JPH0328071B2 JP56073546A JP7354681A JPH0328071B2 JP H0328071 B2 JPH0328071 B2 JP H0328071B2 JP 56073546 A JP56073546 A JP 56073546A JP 7354681 A JP7354681 A JP 7354681A JP H0328071 B2 JPH0328071 B2 JP H0328071B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- memory cell
- semiconductor region
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- 238000003860 storage Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明はMOS半導体装置の製造法に関し、主
にダイナミツクMOSメモリ半導体装置における
メモリ素子を対象とする。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a MOS semiconductor device, and is mainly directed to a memory element in a dynamic MOS memory semiconductor device.
従来の1MOS／セル方式のダイナミツクメモリ
半導体装置においてメモリ素子（セル）の素子分
離にLOCOS（低温選択酸化法）方式による酸化膜
を使用している。このLOCOS方式酸化膜はSi基
板の表面に薄い酸化膜（SiO2）を介して形成し
た窒化膜（Si3N4）をマスクとして選択的に低温
酸化を行なうことによつて厚いフイールド酸化膜
を形成するものであるが酸化膜の周縁部が酸化マ
スク下のまで食いこむためパターニング後の寸法
変換が大きく、メモリセルサイズの縮小に伴ない
活性領域が相対的に小さくなることが欠点であ
る。 In a conventional 1MOS/cell type dynamic memory semiconductor device, an oxide film based on the LOCOS (Low Temperature Selective Oxidation) method is used to separate memory elements (cells). This LOCOS method oxide film is created by selectively performing low-temperature oxidation using a nitride film (Si 3 N 4 ) formed on the surface of a Si substrate via a thin oxide film (SiO 2 ) as a mask to form a thick field oxide film. However, the disadvantage is that the peripheral edge of the oxide film digs into the oxide mask, resulting in large dimensional changes after patterning, and that the active region becomes relatively smaller as the memory cell size decreases.
第１図はLOCOS方式により製造された1MOS
型ダイナミツク装置のメモリセルを断面図で示す
ものでＱ１は転送用のＮチヤネルMOSFET、Cs
は電荷蓄積容量部であり第２図は第１図の等価回
路図である。 Figure 1 shows 1MOS manufactured using the LOCOS method.
This is a cross-sectional view of the memory cell of a type dynamic device, where Q1 is an N-channel MOSFET for transfer, and Cs
is a charge storage capacitor section, and FIG. 2 is an equivalent circuit diagram of FIG. 1.
第１図において、１はＰ型Si基板、２は
LOCOS方式によりフイールド酸化膜、３はゲー
ト絶縁膜、４はN+ソース、５はN+ドレイン、６
はポリSiゲート、７はVCCに接続するポリSi層で
メモリセルの電荷蓄積容量部Csの上部電極とな
る。 In Figure 1, 1 is a P-type Si substrate, 2 is a
Field oxide film by LOCOS method, 3 is gate insulating film, 4 is N + source, 5 is N + drain, 6
7 is a poly-Si gate, and 7 is a poly-Si layer connected to V CC , which becomes the upper electrode of the charge storage capacitor Cs of the memory cell.
このような1MOS型メモリセルでの問題点は以
下のようなものである。 Problems with such a 1MOS type memory cell are as follows.
(1) Cs（蓄積容量）が集積度の向上により減少す
る。(1) Cs (storage capacity) decreases as the degree of integration increases.
(2) Csの上部電極がVCCではVCC電位の変動の影
響を受け易い。(2) When the upper electrode of Cs is at V CC , it is easily affected by fluctuations in V CC potential.
(3) α線によるソフトエラーに影響を受け易い。(3) Easily affected by soft errors caused by alpha rays.
上記(1)については、フイールド酸化工程で酸化
膜が酸化マスクの下にまで食い込むためシユリン
ク則以上にCsの減少が大きい。上記(2)及び(3)に
ついてはC3を形成する電極下にそれぞれN+、P+
層を設けることが有効である。 Regarding (1) above, since the oxide film digs into the bottom of the oxide mask in the field oxidation process, the reduction in Cs is greater than Schullinck's law. Regarding (2) and (3) above, N + and P + are placed under the electrode forming C 3 , respectively.
It is effective to provide layers.
本発明の目的は、前述した1MOS型メモリセル
の問題点を解決する製法を提供することである。 An object of the present invention is to provide a manufacturing method that solves the problems of the 1MOS type memory cell described above.
以下本発明を1MOS型メモリセルの電荷蓄積容
量部（Cs）の製造プロセスに適用した場合の実
施例にそつて第３図ａ〜ｅを参照しながら説明す
る。 An embodiment in which the present invention is applied to a process for manufacturing a charge storage capacitor (Cs) of a 1MOS type memory cell will be described below with reference to FIGS. 3a to 3e.
(a) Ｐ型Si基板１０の表面のメモリセルとなるべ
き領域において、ゲート酸化により酸化膜１１
を膜厚500Å程度に形成し、さらにその上に
S1O2を500Å厚にデポジツトし、ホトエツチに
よつて素子分離領域となるSiO2膜１２を形成
する。このSiO2膜１２はレジストマスクでパ
ターニングするものであるため従来のLOCOS
方式の場合のような基板表面への酸化膜の食い
込みが少なく、Csを大きくとることができる。(a) In the area on the surface of the P-type Si substrate 10 that is to become a memory cell, the oxide film 11 is removed by gate oxidation.
is formed to a thickness of about 500 Å, and then
S 1 O 2 is deposited to a thickness of 500 Å and photo-etched to form a SiO 2 film 12 that will serve as an element isolation region. This SiO 2 film 12 is patterned using a resist mask, so it is difficult to use conventional LOCOS.
There is less penetration of the oxide film into the substrate surface as in the case of this method, and a large amount of Cs can be obtained.
(b) 周辺回路及びメモリセルの転送部、完成ゲー
ト部をホトレジスト膜１３で覆い、蓄積容量部
（Cs）となる部分のホトレジストを取除く。こ
のホトレジスト膜とと前記SiO2膜１２をマス
クとしてボロン(B)イオン打込み（〜150Ke〜５
×1012／cm2程度）を行なう。このボロン打ち込
みは素子分離の寄生MOS効果を防ぐために行
なうものである。打込エネルギはSiO2膜１２
の部分ではSi表面から浅く入り寄生MOS効果
を有効に防止できる。一方SiO2膜１２がない
領域では深く入る。この領域では深く入るため
α線により発生する電子の有効なバリアとな
る。(b) Cover the peripheral circuit, the transfer section of the memory cell, and the completed gate section with a photoresist film 13, and remove the photoresist from the portion that will become the storage capacitor section (Cs). Using this photoresist film and the SiO 2 film 12 as a mask, boron (B) ions were implanted (~150Ke~5
×10 12 /cm 2 ). This boron implantation is performed to prevent the parasitic MOS effect of element isolation. The implantation energy is SiO 2 film 12
In the region , it penetrates shallowly from the Si surface and can effectively prevent parasitic MOS effects. On the other hand, it penetrates deeply in areas where there is no SiO 2 film 12. In this region, since it penetrates deeply, it becomes an effective barrier for electrons generated by alpha rays.
(c) 次いで同じマスクを使用してヒ素（As）を
打込む（〜80KeV〜３×1012／cm2程度）。Asは
ポロンより浅く入るためAsが打込まれたSi表
面はＮ型となる。(c) Next, using the same mask, arsenic (As) is implanted (about 80 KeV to 3×10 12 /cm 2 ). As As enters shallower than Poron, the Si surface into which As is implanted becomes N-type.
(d) ここでレジストを除去し、アニールを行なう
ことによりＳ基板表面に深いP+層１４と浅い
N+層１５とでP+N+接合が形成される。(d) At this point, the resist is removed and annealing is performed to form a deep P + layer 14 and a shallow layer on the S substrate surface.
A P + N + junction is formed with the N + layer 15.
(e) この後、表面にゲート及び上部電極となるポ
リSi層１６を4000Å程度に形成することによ
り、メモリセルの蓄積容量部Csが完成する。(e) Thereafter, a poly-Si layer 16 that will serve as a gate and an upper electrode is formed to a thickness of about 4000 Å on the surface, thereby completing the storage capacitor portion Cs of the memory cell.
1MOS型ダイナミツクメモリセルの製造プロセ
スは下記の工程により行われる。 The manufacturing process of a 1MOS type dynamic memory cell is performed through the following steps.
No.１ 基板変化
２ ナイトライドデポジシヨン
３ ホツトエツチ（ナイトライド加工）
４ イオン打込（ボロン）
５ レジスト除去
６ フイールド酸化
７ ナイトライド除去 …(a)
８ SiO2１２デポ（4000Å）
９ SiO2ホツトエツチ
10 ゲート酸化 …(b)
11 レジスト１３パターニング
12 ボロン打込 100KeV1×1012／cm2
13 As打込 80KeV1×1013／cm2 …(c)
14 レジスト除去
15 ポリSi（N+ポリSi）
１６デポジシヨン
16 ポリSi１６ホトエツチ
17 N+層形成 …(d)
18 層間酸化膜２０デポジシヨン ……(e)
No.19 コンタクトホールホトエツチ
20 Al蒸着
21 Alホトエツチ
22 保護膜デポジシヨン ……(f)
上記No.１〜No.７はメモリセル以外（例えば周辺
回路）の素子分離形成のためのLOCOS工程であ
る。No. 1 Substrate change 2 Nitride deposition 3 Hot etch (nitride processing) 4 Ion implantation (boron) 5 Resist removal 6 Field oxidation 7 Nitride removal...(a) 8 SiO 2 12 deposit (4000Å) 9 SiO 2 hot etch 10 Gate oxidation …(b) 11 Resist 13 patterning 12 Boron implantation 100KeV1×10 12 /cm 2 13 As implantation 80KeV1×10 13 /cm 2 …(c) 14 Resist removal 15 Poly-Si (N + Poly-Si) 16 Deposition 16 Poly-Si16 photoetch 17 N + layer formation...(d) 18 Interlayer oxide film 20 deposition...(e) No.19 Contact hole photoetch 20 Al vapor deposition 21 Al photoetch 22 Protective film deposition...(f) Above No. 1 to No. 7 are LOCOS steps for forming isolation of elements other than memory cells (for example, peripheral circuits).
上記No.８〜No.12はメモリセル部素子分離形成の
ための工程であり、第３図ａ〜ｅで詳しく説明し
た。 The above steps No. 8 to No. 12 are steps for forming element isolation in the memory cell section, and were explained in detail in FIGS. 3a to 3e.
上記No.15以下はメモリセルのMOSFET形成の
ための工程である。 The steps from No. 15 above are steps for forming a MOSFET of a memory cell.
第４図は完成した1MOS型ダイナミツクメモリ
セルの要部を示すものであり、同図の１７はポリ
Siゲート電極、１８，１９はソース、ドレイン、
２０は層間絶縁膜、２１はAl配線である。 Figure 4 shows the main parts of the completed 1MOS type dynamic memory cell, and 17 in the figure is a polygon.
Si gate electrode, 18, 19 are source, drain,
20 is an interlayer insulating film, and 21 is an Al wiring.
次に前記No.１〜No.22に従つた1MOSダイナミツ
クメモリの製造工程を、第５図ａ〜ｆに周辺回路
部のMOSとメモリセル部のMOSの断面構造を用
いて説明する。まず同図の側が周辺回路部の
MOS（LOCOS構造）で側がメモリセル部であ
る。第５図ａに示されるように前記した製造プロ
セスNo.１〜No.７によつて基板１０上にフイールド
酸化膜が形成される。そして、同図ｂに示される
ように前記したプロセスNo.８〜No.10によつて
SiO2１２が形成される。次に同図ｃのように、
プロセスNo.11〜No.13によつて、メモリセル部にフ
オトレジスト１３をマスクとして基板１０表面に
ボロン及びヒ素をイオン打ち込みする。次に同図
ｄのように、プロセスNo.14〜No.17によつて周辺回
路部及びメモリセル部にポリSi層１６を選択的に
形成すると共にソース、ドレイン領域を形成す
る。そして、第５図ｅのように、プロセスNo.18に
よつて層間絶縁膜２０を形成する。次に同図ｆの
ように、プロセスNo.19〜No.22によつて、周辺回路
部のMOSへのソース、ドレイン電極となるAl電
極２１及び最終保護膜２５（フアイナルパツシベ
ーシヨン）を形成する。 Next, the manufacturing process of the 1MOS dynamic memory according to No. 1 to No. 22 will be explained using FIGS. 5a to 5f, which show cross-sectional structures of the MOS in the peripheral circuit section and the MOS in the memory cell section. First, the side shown in the figure is the peripheral circuit section.
It is a MOS (LOCOS structure) and the side is the memory cell part. As shown in FIG. 5a, a field oxide film is formed on the substrate 10 by the manufacturing processes No. 1 to No. 7 described above. Then, as shown in FIG.
SiO 2 12 is formed. Next, as shown in figure c,
By processes No. 11 to No. 13, boron and arsenic ions are implanted into the surface of the substrate 10 in the memory cell portion using the photoresist 13 as a mask. Next, as shown in FIG. 4D, by processes No. 14 to No. 17, a poly-Si layer 16 is selectively formed in the peripheral circuit section and the memory cell section, and source and drain regions are also formed. Then, as shown in FIG. 5e, an interlayer insulating film 20 is formed by process No. 18. Next, as shown in FIG. Form.
本発明によれば、素子分離領域をデポジシヨン
により形成した半導体酸化膜を利用するものであ
るから、LOCOS方式のような酸化膜の食い込み
がなく、限られたスペースで蓄積容量部を広くと
ることができ、このデポジシヨンによる酸化膜を
マスクとしてSi基板表面に不純物を選択的に導入
することによりP+N+層を形成するものであるか
ら、蓄積容量部の電極としてもVCC電位の変動を
防止できるとともにα線防止にも有効であり、前
記発明の目的が達成できる。 According to the present invention, since the element isolation region uses a semiconductor oxide film formed by deposition, there is no encroachment of the oxide film as in the LOCOS method, and the storage capacitor section can be widened in a limited space. Since a P + N + layer is formed by selectively introducing impurities onto the Si substrate surface using the oxide film formed by this deposition as a mask, it can also be used as an electrode for the storage capacitor to prevent fluctuations in the V CC potential. It is also effective in preventing alpha rays, and the object of the invention can be achieved.
本発明は高集積メモリセルの製造に特に有効で
ある。 The present invention is particularly effective in manufacturing highly integrated memory cells.
本発明は前記実施例に限定されず、例えば導電
型の変更、絶縁膜、導体膜の変更等で種々の変形
例を有するものである。 The present invention is not limited to the above-mentioned embodiments, but includes various modifications such as changing the conductivity type, changing the insulating film, and changing the conductive film.
第１図はMOSメモリの従来例を示す断面図、
第２図は第１図に等価の回路図、第３図ａ〜ｅは
本発明によるMOSメモリ要部の製造プロセスの
一実施例の工程断面図、第４図は本発明による
MOSメモリの一実施例の断面図、第５図ａ〜ｆ
は本発明による1MOSダイナミツクメモリの製造
工程を示す工程断面図である。
１……Ｐ型Si基板、２……LOCOS方式による
フイールド酸化膜、３……ゲート酸化膜、４……
ソース、５……ドレイン、６……ポリSiゲート、
７……Csの上部電極、１０……Ｐ型Si基板、１
１……ゲート酸化膜、１２……フイールド酸化
膜、１３……ホトレジスト、１４……P+層、１
５……N+層、１６……ポリSi層、１８……ソー
ス、１９……ドレイン、２０……層間絶縁膜、２
１……Al膜、２５……保護膜。
Figure 1 is a cross-sectional view showing a conventional example of MOS memory.
Fig. 2 is a circuit diagram equivalent to Fig. 1, Figs. 3 a to e are process cross-sectional views of an embodiment of the manufacturing process of the main part of a MOS memory according to the present invention, and Fig. 4 is a circuit diagram according to the present invention.
Cross-sectional view of an embodiment of a MOS memory, FIGS. 5a-f
FIG. 2 is a process cross-sectional view showing the manufacturing process of a 1MOS dynamic memory according to the present invention. 1... P-type Si substrate, 2... Field oxide film by LOCOS method, 3... Gate oxide film, 4...
Source, 5...Drain, 6...Poly-Si gate,
7...Cs upper electrode, 10...P-type Si substrate, 1
1... Gate oxide film, 12... Field oxide film, 13... Photoresist, 14... P + layer, 1
5...N + layer, 16... Poly Si layer, 18... Source, 19... Drain, 20... Interlayer insulating film, 2
1... Al film, 25... Protective film.
Claims (1)
一主面に熱酸化膜を形成し、この熱酸化膜上に容
量素子間を分離するための絶縁膜をデポジシヨン
法により選択的に形成し、前記デポジシヨン法に
より形成された絶縁膜をマスクとして前記第１半
導体領域の一主面に前記熱酸化膜を通して第２導
電型の不純物を導入して前記容量素子の一電極と
なる第２半導体領域を形成し、その後前記第２導
電型の第２半導体領域上に前記容量素子の他の電
極となる導体層を形成する工程を有することを特
徴とする半導体装置の製造法。1. A thermal oxide film is formed on one main surface of a first semiconductor region of a first conductivity type of a semiconductor substrate, and an insulating film for isolating capacitive elements is selectively formed on this thermal oxide film by a deposition method. a second semiconductor region that becomes one electrode of the capacitive element by introducing impurities of a second conductivity type into one main surface of the first semiconductor region through the thermal oxide film using the insulating film formed by the deposition method as a mask; A method for manufacturing a semiconductor device, comprising the steps of forming a conductor layer on the second semiconductor region of the second conductivity type, and then forming a conductor layer serving as another electrode of the capacitive element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56073546A JPS57188866A (en) | 1981-05-18 | 1981-05-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56073546A JPS57188866A (en) | 1981-05-18 | 1981-05-18 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57188866A JPS57188866A (en) | 1982-11-19 |
| JPH0328071B2 true JPH0328071B2 (en) | 1991-04-17 |
Family
ID=13521334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56073546A Granted JPS57188866A (en) | 1981-05-18 | 1981-05-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57188866A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6022361A (en) * | 1983-07-19 | 1985-02-04 | Nec Corp | Manufacture of mis type semiconductor memory device |
| US4570331A (en) * | 1984-01-26 | 1986-02-18 | Inmos Corporation | Thick oxide field-shield CMOS process |
| JPH06105774B2 (en) * | 1987-11-17 | 1994-12-21 | 富士通株式会社 | Semiconductor memory device and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333053A (en) * | 1976-09-09 | 1978-03-28 | Toshiba Corp | Production of semiconductor device |
| JPS55141750A (en) * | 1979-04-23 | 1980-11-05 | Nec Corp | Insulated gate type semiconductor device |
-
1981
- 1981-05-18 JP JP56073546A patent/JPS57188866A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333053A (en) * | 1976-09-09 | 1978-03-28 | Toshiba Corp | Production of semiconductor device |
| JPS55141750A (en) * | 1979-04-23 | 1980-11-05 | Nec Corp | Insulated gate type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57188866A (en) | 1982-11-19 |
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