JPS6220420A - Buffer circuit - Google Patents

Abstract

PURPOSE:To shorten the practical delay time of a BiCMOS or CMOS logic LSI by giving the logic function to a buffer circuit to cope with both of ECL and TTL signals. CONSTITUTION:The ECL signal is inputted to the first terminal A11. The ECL signal has the level shifted by bipolar transistors TRs QA1 and DA1 and is supplied to an input TR QA2. If the second input is a large signal from BiCMOS or CMOS circuit, it is supplied to a terminal A21 and is supplied to an input TR QA3 through a MOSFET. If the second inpt is the ECL signal, it has the level shifted similarly to the first input and is connected directly to a terminal A2. The same operation is performed with respect to the third input terinal A31, but a terminal A3 is connected directly to the emitter of a TR QA4 if there is not the input. In this circuit, OR and NOR are outputted to output terminals with a minimum delay time when both of ECL and TTL signals are inputted.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention applies to semiconductor integrated circuits, and particularly to high-speed logic LS.
The present invention relates to an LSI circuit suitable for a buffer circuit of I.

[Background of the invention]

Conventional buffer circuits feed back the output signal to the input side circuit, as seen in Japanese Patent Laid-Open No. 57-113483.
It was a so-called flip-flop type circuit. For this reason, the operating speed is not sufficient, and the higher the power consumption during signal switching, the lower the performance as a high-speed, low-power consumption circuit.

[Purpose of the invention]

An object of the present invention is to provide a logic LSI equipped with a high-speed human output buffer circuit.

[Summary of the invention]

There is a so-called gate array master slice LSI in which a basic gate circuit and an input/output buffer circuit are fabricated on an LSI, and a logic LSI requested by a user is fabricated by combining and connecting these circuits. This LSI
The average delay time per gate of the logic LSI manufactured by is the value obtained by adding the delay time of the internal circuit to the delay time of the output image buffer circuit, and dividing this by the number of logic stages.

The number of logic stages of internal circuits in a mask slice LSI is 2 to 3 stages at the most, and the average number of logic circuits is about 5 stages. When the number of logic stages is small in this way, even if the internal gate circuit operates quickly, the average delay time increases due to the delay of the input/output buffer circuit, making it impossible to obtain a high-speed logic LSI.

The present invention was made to reduce the influence of the delay time of this input/output circuit, and is characterized in that the input buffer and output buffer circuits also have logic functions.

In this way, a circuit in which the input/output buffer circuit also has a logic function is used in bipolar ECL master slices, but in 0MO3 and B1CMOS gate array master slice LSIs, the human output buffer circuit does not have a logic function. do not have. This is not only because it is difficult to provide a logic function to a human output buffer circuit, but also because the logic circuit has a large number of internal logic stages and is less affected by the delay time of the human output buffer circuit.

However, as mentioned above, the number of internal logic stages of a bipolar ECL master slice is small, and it is difficult to achieve high integration and high speed due to power consumption and device yield constraints, so it is difficult to apply 0MO3 or BiCMO3 circuits to this field. is strongly required.

As mentioned above, logic circuits with a very small number of logic stages are often used in circuits in such application fields, and high-speed logic L
6 In addition, bipolar ECL master slicer is essential for manufacturing SI, and ECL input/output level is commonly used because ultra-high speed operation is required in the field of SI, and human output that can handle this signal level is required. A buffer circuit is also a necessary condition.

The present invention was made in response to such a demand, and basically consists of connecting a MOSFET to the base electrode of a switching transistor of a current switch circuit used in a bipolar ECL logic LSi, and
ECL can be achieved by applying a large amplitude signal of TTL level or higher to the gate of T, and if necessary, supplying an ECL level signal directly to the base electrode of the switching transistor.

An object of the present invention is to provide a human output buffer circuit that can handle both TTL and TTL signal levels.

[Embodiments of the invention]

A detailed explanation will be given below based on this embodiment.

FIG. 1 shows an input buffer circuit according to the present invention.

This circuit basically incorporates the current switch circuit used in the bipolar ECL master slice, and PMO3 and NHO2 are added between the collector and base of the bipolar transistor, and between the base and the power supply 77, respectively. In a manual buffer circuit, at least one input is E CL I'a
Since the signal is input, it is connected to terminal All. Since the outputs OA and OA of the current switch are supplied to the BiCMO3 or CMO8 circuit, it is desirable that their amplitude be large, so the bipolar transistor QAI
After being level-shifted by a diode-connected bipolar transistor DAI, the signal is supplied to the input transistor QA2. When the second input is a large amplitude signal from the BiCMO5 or CMO3 circuit, it is supplied to A21, supplies current to the base terminal A2 of input transistor QA3, and operates QA3. The second input is ECL
Needless to say, when it is at the level, it is connected directly to the terminal A2 after performing a level shift using a device corresponding to the bipolar transistor QAI and the diode DAI in the same way as the first input. The third input signal is also similar to the second input, but if there is no third input, it is sufficient to connect A3 to the emitter terminal of QA4 without connecting the MO3FET. The other operations are the same as those of the ECL bipolar logic circuit, but since they are very similar, the explanation will be omitted.

According to this circuit, when ECL, TTI, and both (g) are input, OR and NOR are output to the output terminal, respectively, and it goes without saying that a logic circuit can be constructed by this.The delay time of this circuit is The delay time was 3.2 ns, which was a small increase in delay time compared to 3 ns for an input buffer circuit without a logic function.

FIG. 2 shows an output buffer circuit of a second embodiment. It is basically the same as the input buffer circuit shown in FIG.

However, in order to be able to handle both ECL and TTL signals for all input bipolar transistors, MOSFETs are provided, and for ECL inputs, MOSFETs are provided directly at the base of the input transistors without level shifting. Just connect it to the terminal.

The delay time in this circuit was approximately the same as the delay time in the ECL circuit, and by providing the output circuit with a logic function, it was possible to effectively reduce the delay time in the output buffer circuit.

In the embodiments shown in FIGS. 1 and 2, the source terminal of the NHO2-FET is connected to the power supply vT, but this terminal should be connected to the emitter terminal of the input bipolar transistor, the power supply ■9. It is also possible to connect to When making the former connection, the gate width of the NHO2-FET is
The latter is wider than the circuit shown in the figure.

On the contrary, it is desirable to make the connection narrower. The characteristics of these connections are that the former connection method occupies a small area for device placement and connection;
2) and the latter connection method, there was almost no difference in the occupied area. The delay time of the circuit was the smallest in the circuit using the latter connection method in which the source terminal of the NMO5FET was connected to the power supply (2) and (2).

In addition, in Figures 1 and 2, the source terminal of the PMO3FET is connected to the collector terminal A6 of the bipolar 1 helang transistor.
．． It is connected to B6, but connect a second power supply to this,
It is also possible to set this second power supply voltage to a high potential level corresponding to the ECL input signal. In this way, the amount of change in the potential of the terminals All and Bll due to the input signal is reduced, which has the effect of realizing a faster circuit.

FIG. 3 shows an output buffer circuit according to a third embodiment.

It is basically the same as the output buffer circuit shown in FIG. However, in Fig. 2, the conduction and non-conduction of the input bipolar transistor are controlled by the input of the MOSFET, but in this embodiment, the ECL input signal is directly connected to the base terminal of the bipolar transistor, and the input bipolar transistor is connected directly to the base terminal of the bipolar transistor. On the other hand, it is characterized in that it is directly input to the gate of the NMO3FET, and a logic function is provided by back-conducting non-conduction of this MOS I-'ET. In Figure 3, NMO3
FET MC11, MC21.

Although MC31 was used, it is also possible to use PMO3F[T or a mixture thereof.

〔Effect of the invention〕

As described above, according to the present invention, the delay time of the input buffer circuit and the output buffer circuit is added to the delay time of the internal logic circuit, which increases the actual delay time, but the buffer circuit also has a logic function. and ECL to the input signal level.

By making the circuit compatible with both TTL signals, BiC
By reducing the substantial delay time of MO3 and CMO8 logic LSIs, we were able to achieve high-speed operation comparable to bipolar ECL logic LSIs with lower power consumption.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 each show an ECL according to the present invention. FIG. 3 is a circuit diagram showing an input buffer circuit and an output buffer circuit capable of handling input signals having both TTL and TTL signal levels. FIG. 3 is a diagram showing another output buffer circuit according to the present invention. QAI, ..., QA6. QBI,...,QB7゜Q
CI, ..., QC7... bipolar transistor,
RAI, ..., RA3. RBI,..., RB5゜R
CI,..., RC4...Resistance.

Claims (1)

[Claims] A buffer circuit comprising a bipolar transistor having a logic function when at least one signal at a different signal level is mixedly inputted in addition to the ECL signal level in an ECL circuit.