JPS6220420A - Buffer circuit - Google Patents

Buffer circuit

Info

Publication number
JPS6220420A
JPS6220420A JP15817885A JP15817885A JPS6220420A JP S6220420 A JPS6220420 A JP S6220420A JP 15817885 A JP15817885 A JP 15817885A JP 15817885 A JP15817885 A JP 15817885A JP S6220420 A JPS6220420 A JP S6220420A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
input
ecl
terminal
supplied
tr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15817885A
Other versions
JPH0775315B2 (en )
Inventor
Hisayuki Higuchi
Makoto Suzuki
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/017509Interface arrangements
    • H03K19/017518Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H03K19/017527Interface arrangements using a combination of bipolar and field effect transistors [BIFET] with at least one differential stage

Abstract

PURPOSE:To shorten the practical delay time of a BiCMOS or CMOS logic LSI by giving the logic function to a buffer circuit to cope with both of ECL and TTL signals. CONSTITUTION:The ECL signal is inputted to the first terminal A11. The ECL signal has the level shifted by bipolar transistors TRs QA1 and DA1 and is supplied to an input TR QA2. If the second input is a large signal from BiCMOS or CMOS circuit, it is supplied to a terminal A21 and is supplied to an input TR QA3 through a MOSFET. If the second inpt is the ECL signal, it has the level shifted similarly to the first input and is connected directly to a terminal A2. The same operation is performed with respect to the third input terinal A31, but a terminal A3 is connected directly to the emitter of a TR QA4 if there is not the input. In this circuit, OR and NOR are outputted to output terminals with a minimum delay time when both of ECL and TTL signals are inputted.
JP15817885A 1985-07-19 1985-07-19 Buffer circuit Expired - Lifetime JPH0775315B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15817885A JPH0775315B2 (en) 1985-07-19 1985-07-19 Buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15817885A JPH0775315B2 (en) 1985-07-19 1985-07-19 Buffer circuit

Publications (2)

Publication Number Publication Date
JPS6220420A true true JPS6220420A (en) 1987-01-29
JPH0775315B2 JPH0775315B2 (en) 1995-08-09

Family

ID=15665973

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15817885A Expired - Lifetime JPH0775315B2 (en) 1985-07-19 1985-07-19 Buffer circuit

Country Status (1)

Country Link
JP (1) JPH0775315B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0436823A1 (en) * 1990-01-12 1991-07-17 Siemens Aktiengesellschaft Signal level converter
EP0453651A1 (en) * 1990-04-23 1991-10-30 Siemens Aktiengesellschaft Switching stage
JPH09153593A (en) * 1995-11-30 1997-06-10 Nec Corp Bimos logic circuit
JP2007536399A (en) * 2004-05-03 2007-12-13 オプティマー・フォトニクス・インコーポレイテッドOptimer Photonics, Inc. Nonlinear optically active molecules, their synthesis and use
DE102008031499A1 (en) 2007-07-05 2009-01-08 Musashi Seimitsu Industry Co., Ltd., Toyohashi Method for mounting bags involves mounting on sleeves with large and small diameters and adapted to bearing linkage

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6051327A (en) * 1983-08-31 1985-03-22 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6051327A (en) * 1983-08-31 1985-03-22 Hitachi Ltd Semiconductor integrated circuit device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0436823A1 (en) * 1990-01-12 1991-07-17 Siemens Aktiengesellschaft Signal level converter
EP0453651A1 (en) * 1990-04-23 1991-10-30 Siemens Aktiengesellschaft Switching stage
JPH09153593A (en) * 1995-11-30 1997-06-10 Nec Corp Bimos logic circuit
US5850155A (en) * 1995-11-30 1998-12-15 Nec Corporation BIMOS logic circuit directly controllable by a CMOS block formed on same IC chip
JP2007536399A (en) * 2004-05-03 2007-12-13 オプティマー・フォトニクス・インコーポレイテッドOptimer Photonics, Inc. Nonlinear optically active molecules, their synthesis and use
DE102008031499A1 (en) 2007-07-05 2009-01-08 Musashi Seimitsu Industry Co., Ltd., Toyohashi Method for mounting bags involves mounting on sleeves with large and small diameters and adapted to bearing linkage

Also Published As

Publication number Publication date Type
JPH0775315B2 (en) 1995-08-09 grant

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