JPS62203242A - Data processing circuit - Google Patents

Abstract

PURPOSE:To detect a troubled place in an early time by giving a test signal and test input data to a data processing circuit, sequentially storing data that the data processing circuit is just processing in an output register and observing it as test output data. CONSTITUTION:In the 1st clock cycle CC1 the test signal 12 and the test input data D0 are inputted, while in the 2nd clock cycle CC2 the input data D0 is stored in an input register 1. The moment a flag 53 is turned on, the clock 13 stops in subsequent cycles. Since a register 50 stands at zero in the 2nd clock cycle CC2, a selection circuit 3 outputs the final output data 14 of the data processing circuit 2. In the 3rd clock cycle CC3 the contents D'0 of the final output data 14 are stored in the output register 4 and ends up output data. Simultaneously '1' is added to the register 50, and the selection circuit 3 selects the data 15 that the data processing circuit 2 is processing.

Description

[Detailed Description of the Invention] [-Industrial Application Field] The present invention relates to a data processing circuit that performs various processes on input data, and particularly to a data processing circuit that has means for sequentially outputting data that is being processed. It is related to.

[Conventional technology]

In conventional data processing circuits of this type, given input data is temporarily held in an input register, various data processes such as logical operations and arithmetic operations are performed on the held data, and only the processing results are displayed. is stored in the output register. At the same time, the next input data is given, the contents of the input register are updated, and the next data processing is started.

In this way, the conventional data processing circuit performs data processing on input data stored in an input register, and stores the obtained final result in an output register, thereby continuously processing data.

[Problem that the invention seeks to solve]

The conventional data processing circuit described above can output only the processing result as an output result, so even if a failure occurs in a part of the circuit and unexpected data is output as an output result, no part of the data processing circuit can be output. There was a problem in that it was not easy to determine whether a failure had occurred. Also,
Run a test program to confirm circuit operation and set input data for testing, such as during a self-diagnosis routine when the power is turned on or in the initial state, or during a defect screening test during the manufacture of LSI data processing circuits. It is confirmed that the target circuit is operating normally by observing the output data, but in the case of a data processing circuit composed of more complex logic circuits, the observation point is only the final output data. Therefore, there was a problem in that a very large test program was required to detect all circuit failures during the process.

[Means for solving problems]

The data processing circuit according to the present invention performs various data processing such as logical operations and arithmetic operations on input data, and switches between the final output data of the data processing circuit that outputs the processing results and a plurality of pieces of data that are being processed. a selection circuit that can output, a clock control section that updates the input data using an external test signal, stops the clock of the input register and holds the input data, and adds the selection signal of the selection circuit using the test signal. a selection control unit that sequentially outputs the data in the middle of processing from the selection circuit, initializes the selection signal after outputting all the data, and instructs the clock control unit to start the clock of the input register;
The apparatus further includes means for sequentially outputting data during data processing while holding the input data in response to the external test signal.

[Effect]

In the present invention, by supplying a test signal and test input data to a data processing circuit, the data being processed by the data processing circuit to which the test input data has been input is sequentially stored in an output register and output as test output data. do.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is an input register that updates input data with a test signal from the outside, 2 is a data processing circuit that performs various data processing, and 3 is the final output data of this data processing circuit 2 and a plurality of pieces of data that are being processed. A selection circuit capable of switching and outputting, 4 an output register, 5 a clock control unit that stops the clock of the input register 1 and holds the input data, 6 adds the selection signal of the selection circuit 3 according to the test signal, and adds the selection signal of the selection circuit 3 to the above The data being processed is sequentially outputted from the selection circuit 3, and after all the data is output, the selection signal is initialized, and the input register 1 is sent to the clock control section 5.
This is a selection control unit that instructs activation of the clock.

The data processing circuit 2, the selection circuit 3, and the selection control section 6 constitute means for sequentially outputting data during data processing while holding the input data in response to an external test signal.

Also, 10 is input data, 11 is a clock, 12-digit test signal, 13 is a clock of input register 1, 14 is final output data of data processing circuit 2, 15゜16Φ...19
20 is output data, 21 is a selection signal for the selection circuit 3, and 22 is a start signal for the clock 13 of the input register 1.

FIG. 2 is a configuration diagram extracting and showing a portion related to the selection control section 6 in FIG. 1.

In FIG. 2, the same symbols as in FIG. 1 indicate corresponding parts, 50 is a register that outputs the selection signal 21, 51
is an adder that adds +1 to the selection signal 21; 52 is a selection circuit that switches between all zeros and the output of the adder 51 as a register 500A; 53 is a flag that switches the selection of this selection circuit 52; 54 is based on the contents of the selection signal 21; Start signal 2
This is a decoder that decodes 2.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained.

First, during normal operation, it performs the same operation as a conventional data processing circuit. That is, when input data 10 is input from the outside, the input register 1 stores the input data 10 using the clock 13. At this time, the clock control section 5 couples the clock 11 to the clock 13 as is. and,
The data processing circuit 2 executes data processing on the input data held in the input register 1, and final output data 14 is output. At the same time, the data processing circuit 2 also outputs data 15 to 19 during processing, but the selection circuit 3 outputs the final output data 14 from the data processing circuit 2 in response to the selection signal 21 from the selection control section 6. This is because inside the selection control unit 6, the flag 53 shown in FIG. Become. When the selection signal 21 is zero, the selection circuit 3 shown in FIG. 1 selects the final output data 14 of the data processing circuit 2.

The final output data 14 of the data processing circuit 2 selected by the selection circuit 3 is stored in the output register 4 at the next clock 11 and output as output data 20. At the same time, new input data 10 is stored in the input register 1, and a transition is made to the next data processing operation.

On the other hand, when the test signal 12 is input to the data processing circuit 2, it operates as follows.

Test input data 10 and test signal 12 are input simultaneously from the outside. At this time, the clock controller 5 is still coupling the clocks 11 and 13, so the input data 10 is stored in the input register 1 by the clock 13. However, at the same time, the test signal 12 causes the clock control section 5 to separate the clocks 11 and 13, so that the clock 13 is no longer output. Retains until input.

The data processing circuit 2 then performs data processing on the test input data 10 held in the input register 1 and outputs final output data 14 and intermediate data 15 to 19.

On the other hand, inside the selection control section 6, the flag 53 shown in FIG. 2 is turned on due to the input of the test signal 120, and the selection circuit 5
2 selects the output side of the adder 51. Therefore, the register 50 is zero when the test signal 12 is input, but is incremented by +1 each time the next clock 11 is input.

Therefore, the selection circuit 3 shown in FIG.
After outputting the data 4, the data 15 to 19 being processed are sequentially output each time the selection signal 21 is added. These selection circuits 3
The outputs are sequentially outputted as test output data of the data processing circuit 2 while being temporarily held in the output register 4. Further, the selection control unit 6 monitors the output of the register 50 using the decoder 54 shown in FIG. The register 50 is cleared to zero by turning off, the clock controller 5 shown in FIG. 1 is instructed to combine the clocks 11 and 13, and the normal data processing operation is resumed.

Next, the operation of this embodiment circuit will be explained based on FIG.

This FIG. 3 is a time chart used to explain the operation of FIGS. 1 and 2. (a) shows the clock 11, 6) shows the test signal 12, and (e) shows the flag 53.
, (d) is the clock 13, (,) is the register 50, (f
) is the selection signal of the selection circuit 3, -) is the input register 1, (
h) is the output register 41) indicating the activation signal 22.

Then, ccl, CC2...CC8 indicate the first clock cycle, the second clock cycle...the eighth clock cycle, and D-L r D -1+ DO+
I) +t is input data, D-2+ D-1+D
O+D+1 is the final output data obtained by processing each input data in the data processing circuit 2, no/-
1 and no/-2+D O'-3+ D O'-4r
D O'-5 is data that is being processed on a circuit in the middle of the data processing circuit 2 when the data processing circuit 2 processes the input data Do and outputs the final output data Do'.

Note that the clock in FIG. 3 sets the register at the falling edge.

First, in the first clock cycle CC1, as shown in FIG.
A test signal 12 shown in and test input data Do are input.

Then, in the second clock cycle CC2, input data D is input to the input register 1. is stored, the flag 53 is turned on, and from the second clock cycle ccf onwards, the state shown in FIG. 3 (
The clock 13 shown in d) is stopped.

Further, in this second clock cycle cc2, the register 50 is zero, so the selection circuit 3 shown in FIG. 1 outputs the final output data 14 of the data processing circuit 2.

Next, in the third clock cycle CC3, the content Do' of the final output data 14 is stored in the output register 4 and becomes output data. At the same time, the register 50 is set to “
1#, and the selection circuit 3 selects the data 15 being processed by the data processing circuit 2.

Next, in the fourth clock cycle cc4, the content DO'-1 of the data 15 in progress is stored in the output register 4 and becomes output data. At the same time, the register 50 is set to "2", and the selection circuit 3 selects the data 16 being processed by the data processing circuit 2.

Similar operations are performed in the fifth clock cycle cc5 and the sixth clock cycle CC6. Then, in the sixth clock cycle cc6, the register 50 is set to 14.
At the same time as m, this value is coded and the activation signal 22 is output.

Next, in the seventh clock cycle cc7, flag 5
If 3 is turned off, the clock 13 will be restarted. Then, in this seventh clock cycle cc7, the content DO'4 of the data 18 being processed is stored in the output register 4 and becomes output data. The register 50 is added to "5" on the same axis as the tip, and the selection circuit 3 selects the last half-processed data 19 of the data processing circuit 2.

Next, in the eighth clock cycle cc8, the next input data I)+t is stored in the input register 1, and the content oj-s of the last unprocessed data 19 for the input data Do is stored in the output register 4 and output. be done. and,
Since the register 50 is cleared to zero, the selection circuit 3 selects the final output data 14 for the input data D+1.

Then, the subsequent clock cycles are normal data processing operations.

〔Effect of the invention〕

As described above, according to the present invention, by providing a test signal and test input data to a data processing circuit, the data being processed by the data processing circuit to which the test input data has been input is sequentially stored in the output register. Since it can be observed as test output data, it is easier to create test programs that are run in self-diagnosis routines in the initial state or when a failure occurs, and in defective product selection tests during the manufacturing of LSI data processing circuits, and the number of steps is reduced. This has the effect of making it more compact and shortening test time.

In addition, since the location where the failure occurs can be directly observed, it has the advantage of allowing early detection.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a configuration diagram extracting and showing the part related to the selection control section in FIG. 1, and FIG. It is a time chart for explaining the operation. 1-...input register, 2...data processing circuit,
3. Contention/Φ selection circuit, 4. Output register, 5.@
- Clock control section, 6 φ... Selection control section, 50...
...Register, 51...Fist adder, 52...Selection circuit, 53...Flag, 54...Decoder.

Claims (1)

[Claims] In a data processing circuit that performs various data processing such as logical operations and arithmetic operations on input data and outputs the processing results, the final output data of the data processing circuit and a plurality of data in progress are switched and output. a clock control section that updates the input data using an external test signal, stops the clock of the input register to hold the input data, and adds the selection signal of the selection circuit using the test signal; a selection control unit that sequentially outputs data during processing from the selection circuit, initializes the selection signal after outputting all the data, and instructs the clock control unit to start the clock of the input register; and the external test. A data processing circuit comprising means for sequentially outputting data during data processing while holding the input data by a signal.