JPS6249451A - Information processor - Google Patents

Abstract

PURPOSE:To make it possible to execute writing or reading operation within the shortest time by selecting plural memory elements included in a shift register and connecting memory elements mutually to form a new shift register. CONSTITUTION:A shift register designating signal 100 that selects a shift register 2b from a shift register designating circuit 3 is supplied to a decoder 5, a SI selecting circuit 10 and an SO selecting circuit 11. As the result, a clock signal 103 is supplied from a clock supply circuit 4 to the shift register 2b through the decoder 5, and data 111 from an SI input control circuit 9 is inputted to the shift in terminal of the shift register 2b through the SI selecting circuit 10. Further, output data 106 from the shift out terminal of the shift register 2b outputted to an SO output control circuit 12 through the SO selecting circuit 11.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a diagnostic means for an information processing device.

In particular, the present invention relates to register diagnostic means using shift paths.

〔overview〕

In an information processing device that is equipped with a shift register and in which data is written to and read from a desired storage element in the shift register, the shift register is divided into cascade-connected shift registers with a small number of shifts, and the divided By selecting a selected shift register to write and read data to and from a desired memory element, it is possible to shorten the time required to write and read data from and to a desired memory element.

[Conventional technology]

In an information processing device that includes logic/devices equipped with registers that require initial setting and diagnosis using shift paths, storage elements within the logic device are interconnected to form a plurality of predetermined shift registers. has been done. Therefore, the number of storage elements included in one shift register, the order of connection, etc. are fixed.

[Problem that the invention seeks to solve]

In such a conventional information processing device, the number and connection order of storage elements included in one shift register are fixed, so some storage elements in one shift register are set to a predetermined value. Even when setting , it is necessary to output the entire shift register including the target storage element, set a predetermined value at the position of the target storage element in the output data, and then input it to the shift register again. Ta.

Therefore, even when data is to be written or read from a part of the memory elements, the entire shift register including the target memory elements must be output, which has the disadvantage of taking time. Furthermore, information processing equipment that includes logic devices that have registers that require initial settings and diagnostics using a shift bus has the disadvantage that the initial settings and diagnostics times take longer, and the average repair time of the equipment increases. .

[Means for Solving the Problems] The present invention provides a first shift register having a plurality of memory elements, and an input/output means for writing and reading data into and from a desired memory element among the memory elements. In the information processing device, the first shift register is configured of a plurality of cascade-connected second shift registers, and the input/output means for the second shift register including the desired storage element is provided. The present invention is characterized by comprising a control means for enabling.

[Effect]

Writing and reading to some storage elements in the shift register are performed, for example, during initialization and diagnosis using the shift bus.

At this time, input/output is not performed for the entire shift register, but only for the portion of the shift register that includes the target storage element. This part is selected by the control device and the other parts are cut off.

This reduces the time required for initial setup and diagnosis.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be explained based on the drawings.

The figure is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention.

First, the configuration of this embodiment device will be explained based on the drawings.

This embodiment device includes a plurality of memory elements 15, a logic circuit network 1 that interconnects the memory elements 15, shift registers 2a, :l'b and 2C, shift registers 2a,
a shift register designation circuit 3 that selects a desired shift register from 2b and 2c; and a shift register designation circuit 3
A shift-in selection circuit (hereinafter referred to as SI selection circuit) 10 performs input designation of shift-in data based on a shift register designation signal 100 from the shift register designation circuit 3; A shift out selection circuit (hereinafter referred to as SO selection circuit) 11 that specifies output of out data, a lock supply circuit 4 that generates a clock signal 101, and a clock supply circuit according to the result of decoding the shift register designation signal 100. a decoder 5 that supplies the clock signal 101 from 4 to one newly formed shift register;
A 1-input circuit 6 that generates a 1-manpower signal 113, a 0-input circuit 7 that generates a 0-manpower signal 112, and a clock signal 10.
The output 108 of the shift buffer 13 in response to the supply of 1;
Output 112 of 0 input circuit 7 and output 11 of 1 input circuit 6
Select one of the shift registers 2a, 2.
A shift-in input control circuit (hereinafter referred to as Sl input control circuit) 9 that inputs serial data 111 to b and 2c, and a shift register 2 in response to the supply of a clock signal 101.
A shift-out output control circuit (hereinafter referred to as SO output control circuit) 14 that outputs serial data 107 from a, 2b, and 2c, and a shift circuit that enables shift-in input and shift-out output operations of shift registers 2a, 2b, and 2c. 8 mode designation circuits, a shift buffer 13 that takes in data 107 output by the SO output control circuit 12 and supplies data 108 to the Sl input control circuit 9, and a diagnostic device that inputs and outputs data to the shift buffer 13. 14.

Next, the operation when selecting a plurality of storage elements included in the shift register 2 and writing data into one newly formed shift register 2b will be described.

First, from the shift register designation circuit 3 to the shift register 2
A shift register designation signal 100 for selecting b is supplied to the decoder 5, the SII selection circuit 10, and the SO selection circuit 11. As a result, the clock signal 103 is sent from the clock supply circuit 4 to the shift register 2b via the decoder 5.
is supplied, data 111 from the SL input control circuit 9 is input to the shift-in terminal of the shift register 2b via the S selection circuit 10, and data 111 from the shift-out terminal of the shift register 2b is input via the SO selection circuit 11. Output data 106 is output to SO output control circuit 12. The shift mode designation circuit 8 sets the shift mode to "1", and the clock supply circuit 4 supplies a clock only to the shift register 2b, and each "1" bit is sent from the shift register 2b's cystout terminal via the SO output control circuit 12. and is taken into the cyst buffer 13. At this time, S
O input signal 11 selected and output by l input control circuit 9
2 is input to the cyst-in terminal of the shift register 2b. In this way, when the contents of all the storage elements of the shift register 2b are transferred to the shift buffer 13, all "0"s should be stored in the shift register 2b, but the clock is shifted an additional - times. The bit supplied to register 2b and output from the shift out terminal is “0”.
” is checked by the SO output control circuit 12. At this time, if the storage element of the shift register 2b is in a fault state where it is stuck at "1", the bit output from the shift out terminal becomes "1", and it is possible to detect the rlJ failure. . If the check result is normal, the -rotation clock is further supplied to the shift register 2b, and rlJ is input to the shift-in terminal. As a result, in the shift register 2b, only the memory element on the shift-in input terminal side becomes "1", and only the memory element on the shift-in input terminal side becomes "1", and all other memory elements become "0". Hereinafter, this “1” will be referred to as L S D (L
AST[)IGIT), and transferring the contents of the shift register 2 to the shift buffer 13 through such a procedure is called scan out. Continuing, the data 109 written from the diagnostic device 14 is transferred to the shift buffer 1.
Transferred to 3.

Next, a procedure for transferring the write data of the shift register 2b transferred to the shift buffer 13 to the shift register 2b after being scanned out will be explained. First, shift register designation signal 1 to select the desired register 2b
00 from the shift register designation circuit 3 to the decoder 5 and S
The signal is supplied to l I selection selection circuits and SO selection circuit 11.

As a result, the shift register 2b is transferred to the shift register 2b via the decoder 5.
A clock is supplied from the clock supply circuit 4 using the clock signal 103 to the S) input control circuit 9, and the data 111 from the input control circuit 9 is input to the shift-in terminal of the shift-out 2b via the SII selection circuit 10. circuit 11
Output data 106 from the shift out terminal of shift register 2b is output to SO output control circuit 12 via. The shift mode designation circuit 8 sets the shift mode to [1].
from the clock supply circuit 4 to the shift register 2
The clock signal 103 is supplied only to the shift register 2b, and each “1” bit is transferred from the shift-in terminal of the shift register 2b to the Sl
It is transferred to the shift register 2b via the input control circuit 9.

At this time, the SO output control circuit 12 checks whether the data 106 output from the shift-out output terminal is rlJ or "0". If it is “1”, then S
The O output control circuit 12 checks whether clocks have been supplied for the total number of bits of the shift register 2b.
If the clock is supplied for the total number of bits, it is considered to be a normal end, and if not, it is considered to be an abnormal end. The reason for this is that [1] is output from the LSD that was last shifted in when the scan-out operation ended normally.
This is limited to only when the bit is shifted out, that is, when the clock is supplied for the entire number of bits. Also, the data output from the shift out output terminal is "0".
In this case, the SO output control circuit 12 further checks whether clocks have been supplied for the entire number of bits of the shift register 2b, and if the supply has not been completed, the clocks are
3 continues to be shifted into the shift register 2b,
If the shift-out output is still “0” even though the clock has already been supplied for the entire number of bits, shift register 2
Since the fault is that a certain storage element b is stuck at "0", the process ends abnormally. Hereinafter, transferring the contents of the shift buffer 13 to the shift register 2 through such a procedure will be referred to as scan-in. After the scan-out operation and scan-in operation, desired data can be written to the shift register 2b.

The write operation has been described above, but in the case of a read operation, the data 110 of the shift register 2b remaining in the shift buffer 13 is read out to the diagnostic device 14 by executing a scan-in operation after a scan-out operation. be able to.

[Effects of the Invention] As explained above, the present invention provides a method for selecting a plurality of memory elements included in one shift register and connecting the memory elements to each other so as to form a new shift register. Therefore, when writing or reading data in some memory elements, it is possible to perform shift register input/output operations on a new shift register with the minimum scale configuration that includes the target memory element. , there is an effect that a write or read operation can be executed in a minimum time.

Therefore, in an information processing device that includes a logic device that includes a register that requires initialization and diagnosis using a shift bus, the initialization time and diagnosis time can be shortened, and the average repair time of the device can be shortened. There is.

[Brief explanation of drawings]

The figure is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. 1...Logic circuit network, 2...Shift register, 3...
・Shift register specifying circuit, 4... Clock supply circuit, Decoder, 6... 1 input circuit, 7... 0 input circuit, 8... Shift mode specifying circuit, 9... SI
Human control circuit, 10...SI selection circuit, 11...S
O selection circuit, 12... SO output control circuit, 13...
Shift buffer, 14...Diagnostic device, 15...Storage element.

Claims (1)

[Claims] (1) In an information processing device comprising a first shift register having a plurality of memory elements, and an input/output means for writing and reading data into and from a desired memory element among the memory elements, the above-mentioned The first shift register is composed of a plurality of cascade-connected second shift registers, and is characterized by comprising a control means for enabling the input/output means for the second shift register including the desired storage element. Information processing equipment.