JPH01287751A - Microprocessor device - Google Patents

Abstract

PURPOSE:To easily specify the trouble of an execution part with simple circuit constitution by connecting a constant register to a scan bus through a scan-in data input terminal and a scan-out data output terminal. CONSTITUTION:A general register group 1 is equipped with >=1 general register 12 and a constant register 11 and is connected to the execution part 2 through data bus input/output terminals 115. Then the constant register 11 has a clock signal input terminal 111 for scanning, a scan-in data input terminal 112, a scan-out data output terminal 111, and a function select signal input terminal 114. Consequently, the read and write speeds of the general registers are not decreased, the regularity of layout is good, and the microprocessor device easily tests the execution part.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to facilitating the testing of microprocessor devices, and more particularly to a microprocessor device that can efficiently test the functionality of an execution section.

Conventional technology As a test method for the execution part of a conventional microprocessor device,
In particular, as a method of concatenating arithmetic numbers to an arithmetic logic circuit, one-digit shift circuit, etc., and a method of storing or reading out the result of arithmetic operations to the outside of a microprocessor device, 1) One or more general-purpose registers are configured as a shift register as shown in Figure 3. Each is connected to the scan path of the microprocessor device, serial data given from the external bin of the microprocessor device is stored by scanning into a general-purpose register, and the value of the general-purpose register is used as an arithmetic number to perform an operation. There is a method to obtain the result of an operation as serial data by executing the operation and storing the result in a general-purpose register configured as a system register, and scanning it out to the output bin of the microprocessor device. Store the immediate value stored in the storage or microprogram ROM in a general-purpose register, then perform an operation on the arithmetic unit using the stored immediate value as an arithmetic number, store the operation result in the general-purpose register, and store the stored immediate value in the general-purpose register. A method has been used in which the execution unit is tested by reading out the calculated result to the data output bin of the microprocessor device using a MOVE instruction or an I10 instruction.

Problems to be Solved by the Invention In method I) above, it is necessary to configure one or more general-purpose registers into a shift register configuration, and the general-purpose registers configured as shift registers have faster read and write speeds than other general-purpose registers. In addition to being slow, there were problems in terms of layout, such as irregularity due to the general-purpose registers having a shift register configuration.

In addition, in method (■) above, if the output result differs from the expected value, a) a process of storing the arithmetic number in the general-purpose register, a) a process of performing an arithmetic operation using the given arithmetic number and outputting the arithmetic result, ) It is difficult to identify where the failure is occurring in the process of outputting the calculation results to the outside of the microprocessor, which may lead to an increase in the test procedure and test time, or it may be difficult to detect the failure. However, there was a problem in that it was not possible to identify the location of the failure.

The present invention has been made in view of this point, and has one or more constant registers that can be manipulated by a set of instructions as a general-purpose register configured as a shift register, and is connected to the scan path of a microprocessor device to read and write general-purpose registers. The purpose of the present invention is to provide a microprocessor device that does not degrade speed (and has good layout regularity) and allows easy testing of the execution section.

Means for Solving the Problems In order to solve the above problems, the present invention provides that at least one of the constant registers in the general-purpose register group operated by the instruction set has a scan clock signal input terminal, a scan-in data input terminal, and a scan clock signal input terminal. The microprocessor device has an out data output terminal and a function selection signal input terminal, and is connected to a scan path via the scan-in data input terminal and the scan-out data output terminal.

The operation constant register can be set to normal operation mode or
Set to one of the test modes.

When a write signal is applied to the constant register in the normal operation mode, the constant register writes the data on the data bus to the shift register section of the constant register. Further, a constant unique to the constant register is always output onto the data bus by a read signal, regardless of the data stored in the shift register section.

Next, in the test operation mode, the serial data is set to the shift register section 2, and the data stored in the shift register section is serially read out by the clock applied to the scan clock signal input terminal. This is done via the scan-out data output terminal. Since the shift register is connected to the scan path of the microprocessor device, serial data can be scanned in and out of the shift register section from an external terminal of the microprocessor device. When a read signal is input, the data in the system register section written in the normal mode or scanned in in the test mode is output onto the data bus.

Embodiment FIG. 1 is a block diagram showing an embodiment of the microprocessor device of the present invention. In FIG. 1, a general-purpose register group 1 includes one or more general-purpose registers 12 and a constant register 11, and is connected to the execution unit 2 via a data bus input/output terminal 115. The constant register 11 has a scanning clock signal input terminal 111. Scan-in data input terminal 112. Scanout data output terminal 11
It has a 3° function selection signal input terminal 114. FIG. 2 shows an example of the configuration of a constant register of a microprocessor in an embodiment of the microprocessor device of the present invention. In FIG. 2, 11 is a constant register, and is a scan clock signal input terminal 111° scan-in data input terminal 1
12. Scan-out data output terminal 113, function selection signal input terminal 114. data bus input/output terminal 115a,
115b.

To test the execution section using this constant register 11, a test mode is set by a function selection signal. First, serial data is scanned in to the scan path using the external terminal of the microprocessor device, data is set in all scan paths, and then the data set in the scan path is scanned out to the external terminal, and this scanned out data is It is necessary to perform a functional test of the scan path by comparing the scan path with the scanned data. By performing this scan path functional test, the function confirmation of the shift register section of the constant register 11 and the storage of data into the shift register are completed at the same time. Subsequently, in the test mode, the data stored in the shift register group of constant register 11 is transferred to other general-purpose registers 12 using instructions from the microprocessor. Before this, it is necessary to check the functionality of the transfer command. A NOT instruction is used as this transfer instruction, and the constant register 11 is used as the source register, and the constant register 11 is also designated as the destination register. After the NOT instruction is executed, the inverted version of the set data is stored again in the shift register group of the constant register 11. This re-stored data is scanned out to check whether the set data has been inverted, and to confirm the function of the NOT command.

After confirming the function of the transfer command, the data stored in the shift register portion of the constant register 11 is transferred to the general-purpose register using the transfer command. However, since the NOT instruction is used, the data set in the general-purpose register 12 is the inverted version of the data in the shift register section. If necessary, serial data is scanned into the shift register section of the constant register 11, and the plurality of general-purpose registers 12 are scanned.
Transfer different data to.

The execution unit is tested using data set in the general-purpose register 12. The constant register 11 is specified as the destination register of a 2-operand or 3-operand operation instruction, data is transferred from the constant register 11 as the source register, and the set general-purpose register 1
2 or the constant register 11 is used. After the calculation in the execution section is completed, the calculation result is stored in the shift register section of the constant register 11. The function of the execution section can be tested by scanning out the calculation result to the external terminal of the microprocessor device in the test mode and comparing it with the expected value.

According to this method, data can be directly set in the register without going through a data fetch unit or the like, so if the calculation result does not satisfy the expected value, it can be determined that a failure has occurred in the execution unit. In addition, by using the constant register 11 as the destination register for load instructions, the source register as the constant register 11 for store instructions, and the constant register 11 as the destination register for immediate instructions, it is possible to easily test the data fetch section and instruction fetch section. can be realized in a similar way.

Effects of the Invention As described above, according to the present invention, failures in the execution unit can be easily identified with an extremely simple circuit configuration, and thus the microprocessor device according to the present invention is extremely useful industrially.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a microprocessor device according to an embodiment of the present invention, FIG. 2 is a constant register configuration diagram of a microprocessor according to an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional microprocessor device. It is a diagram. 1...General purpose register group, 2...Execution unit, 11...Constant register, 12...General purpose register. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 3

Claims (1)

[Claims] At least one of the constant registers in the general-purpose register group operated by the instruction set has a scan clock signal input terminal, a scan-in data input terminal, a scan-out data output terminal, and a function selection signal input terminal; A microprocessor device, characterized in that it is connected to a scan path via an in-data input terminal and the scan-out data output terminal.