JPS62198544A - Wiring logical notation for aggregated wiring system - Google Patents

Abstract

PURPOSE:To make a wiring logical expression have generality and expressible with a minimal expression method, simplify an alteration of high-speed processing, a logic addition, elimination, etc., as well as to render it inexpensive, besides high in reliability, by expressing wiring logic with an inverse Polish notation. CONSTITUTION:In an inverse Polish notation, a right side of the conventional logical operation expression Y=X+Y comes to XY+, while the right side of y=(W+X)*(Y+Z) comes to WX+YZ+*. Therefore, logical development finding a logical expression to show wiring logic on the basis of a combination of the input data prestored in a memory is performable in succession in order of being high in precedence. As for the procedure, data retrieval of a distribution table is performed out of the first data, and when the data is an operator, the logical operation is made so as to be carried out. And, the retrieval is performed in order from a (n) address, and only when the operator is the case, operation to two adjacent on-bite data takes place. Therefore, processing efficiency is improved, and control software also can be made into a concise one.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transmission method using a microcomputer, and particularly relates to a wiring logic description suitable for describing the wiring state between an input and various applicable devices. Regarding the law.

[Conventional technology]

For example, automobiles have various electrical components such as lamps and motors,
A large number of electrical devices such as six-sided sensors and actuators for vehicle control (hereinafter referred to as these electrical components and electrical device total load) are arranged. The number of such devices continues to increase with the advent of car electronics, reaching several hundred points in total. In order to efficiently manage and control these loads, we are proposing an integrated wiring system using optical fibers.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, little consideration has been given to the control software of the centralized wiring system. Specifically, in the wiring relationship between inputs such as switches and output loads (hereinafter, this relationship will be referred to as wiring logic), how is information about which lamps are lit when a switch is turned on? The question is how to express it.

The objectives of the present invention are: 1. Generality in expression 2. Expression using a minimal representation method 3. High-speed processing 4. Easy changes such as addition or deletion of logic 5. High reliability We will do this by providing control software for a centralized wiring system that satisfies (6) no maintenance required (7) and low cost.

[Means for solving problems]

The above object is achieved by fully describing the wiring logic using reverse Polish notation. Reverse Polish notation is a notation in which the right-hand side of a logical operation expression, which was conventionally expressed in the form ``Country = ward vassal'', ``operator ward'', is expressed in the form ``ku ku side 1 operator''. For example, the right side of y=x10y becomes XY+, and the right side of y=(W+X) tree (Y+Z) becomes wx+yz10 trees.

[Effect]

The advantage of introducing reverse Polish notation is that all logic expansions can be executed sequentially in order of highest priority.

"Logical expansion" here is based on a combination of input data and logical operators stored in memory in advance.
This is the task of finding a logical formula that represents wiring logic. - An example is shown in FIG. In this example, one (X2+X3) logic is stored. The input is (00) Hl or (01) u. For example, let NOT, OR, AND operations be (80)H, (CO)H, (EO)H, and at the end of the logic, (FF)H? for discrimination? Store. An example using normal notation is shown in (2), and an example using reverse Polish notation 'k(
1) Show K.

As a logical development method, data search in the wiring table is performed from the first data of the diple. Then, when the data is an operator, a logical operation is performed. However, this procedure is very inconvenient when handling the normal notation t-. This is because the notation is not necessarily arranged in the order of the logic that actually performs the calculation. For example, Figure 2 (
In 2), the search is performed sequentially starting from the data at address n.

After recognizing that the operation inside the parentheses has the highest priority,
Perform the OR operation for the first time, then return by some procedure,
Next, after recognizing that the AND operation has a high priority, the operation it-
I will do it. Finally, r at address (n+7)
The search ends with an ENDJ search, but during that time the values of the index register and program counter increase and decrease rapidly, significantly deteriorating processing efficiency.

The same wiring logic is expressed in reverse Polish notation and the next side is shown in Figure 2 (1). Reverse Polish notation is a notation that arranges items in descending order of total logical priority. Therefore, logical development is also very easy. The procedure is to search sequentially starting from address n, and only in the case of an operator, perform an operation on the previous two 1-byte data. In other words, it is only necessary to "reverse" the search by 2 bytes at most. This improves processing efficiency and simplifies control software.

〔Example〕

An embodiment of the present invention will be described below.

An example of an in-vehicle integrated wiring system employing the present invention is shown in FIG. Central control unit CCU
ontrol Unit) 10, and multiple terminal processing units ItL CTJ (Local (::ontr)
OL Unit) 11 to 14 are commonly connected using an optical fiber cable OF. An optical branch connector oC is provided at the OF branch point. The CCU is installed near the dash board of an automobile and controls the entire system. The LCUs are installed in a distributed manner in the vicinity of a large number of loads installed in the automobile, such as each of the power switches 8W, the meter M1, and the lamp L.

At the part where the CCU and LCU are connected to the OF, there is a photoelectric conversion module O/E that bidirectionally converts optical signals and electrical signals.
66 to 68 are provided.

The CCU is equipped with a microcomputer 18 and has a communication function using serial data.The CCU and LCUK are communication processing circuits CI
Abbreviation for Interfac Mod 15-17
is provided. and CCUii, monitor, control,
A total of three types of wiring are used for the memory.

The monitor table 97 stores data that the CCU sends to the LCU and data that the LCU sends back to the CCU. The reason for storing both data before and after transmission is to check both data before and after transmission, and only for loads where they do not match, C
This is because all methods for the CU to send control data have been adopted. The control table 98 stores data such as on and off applied to each load. The wiring table 99 shows wiring logic between inputs such as switches and loads.

FIG. 3 is a rough block diagram of the CIM, which is a signal transmission-only LSI used in FIG. 1.

XTAL is an input terminal of a crystal oscillator installed in each CIM, and EXTAL is an output terminal. Now, block circuit 3
08 is given a clock from the oscillation circuit 310.

308, the clock and the synchronization circuit 309 send two-phase locks φM and φsk whose phases are shifted by half a cycle. Based on the signal, the stage counter recognizes the status of the CIM, such as reception, transmission, etc., using a count value. Then, the stage decoder 307 decodes the stage counter value and sends a control signal as appropriate.

On the other hand, various loads such as lamps, meters, and sensors are I10
It is connected to the input/output terminal section from the buffer 301. This terminal can select input/output as appropriate, and address designation is given by address decoder 304 decoding the values of address value input terminals ADDRO-ADDR5.

Now, the data RXD received as serial data
is transmitted to a 25-bit shift register 302. The I10 buffer 301 mentioned earlier,! By performing parallel data transmission, appropriate bidirectional transmission is possible. In addition, the fail-safe data stored in advance from the shift register is
From fail safe register 305 ■10 buffer 301
Parallel data is transferred to ensure fail-safety.

The control signal is MPU (Micro process).
an MPU interface unit 311 that controls the state of sing [Jnit), and a mode decoder 312 that defines CIM (7) modes such as transmission mode and reception mode.
, a comparator 303 that detects address errors. The received data that has been transmitted to the shift register is output in parallel to various loads. After the load information is input in parallel to the shift register, the transmission data TX
D, and is transmitted to the CCU.

FIG. 4 is an example of a data transmission situation using the monitor, wiring, and control table.

The monitor table and control table have 16 pieces of data for one LCU. This is the I10 boat, that is, the number of switches and loads that can be externally attached. The number of tables is secured for the number of connected LCUs. The monitor table is
Stores the data of each LCU immediately before transmission. Note that in this example, CCU and LCUI, LCU・−=LCU
It is assumed that n is connected.

Here, it is assumed that when certain switches SWI to Swn of a certain LCU are turned on, a lamp L having all of them and a predetermined wiring logic is lit. The procedure is shown in FIG.

1. The LCU sends load and switch data to the CCU.

After the Z CCU receives the data, it stores it in the monitor table. Then, check the data in the monitor table before and after transmission, and recognize all changes. At this point CC
U knows which switches of the LCU are turned on and off.

3. Input the data in 2 and refer to the wiring table.

Then, based on the wiring logic, it determines load data, that is, information such as which lamps should all be turned on or turned off.

4. The CCU transmits monitor table data based on the control table to the LCU via the transmission path. After receiving it, the LCU turns on and off predetermined lamps (updates load data).

becomes.

Figure 6 shows specific wiring table specifications. The table is 3 bytes long. The first byte is the offset of the manual CIM (transmission order), and the second byte is the offset of the output CIM. The most significant bit is the general wiring logic table GETB
It is determined whether to refer to L''k, that is, whether there is a one-to-one relationship between input and output.

The upper 4 bits of the third byte are the DIO number of the input CIM (
0-F), the lower 4 bits are the DIO number of the output CIM. For example, (1) DIO "F" of the 5th CIM is input, Cth CI
DIO ``0'' of M is output. One-on-one relationship.

(2) The output is DION6'' of the 9th CIM.See GETBL for input relations.

becomes.

FIG. 7 is a general wiring logic table GETBL.

Columns in the table are of variable length. The first byte is the output CIM
The last DIO number (FF) u is end determination data. NOT, OR, AND operators all (80) u, (CO
)i, (EO)u, etc. are set in advance to be negative. Positive data is 2 bytes and indicates one input terminal. Then, the wiring logic is stored using reverse Polish notation. For example, GE
The first row of TBL indicates that the DIO "4' of the second CIM and the DIO "o" of the A-th CIM are ORed, and the output is set to DIO "F" of the third CIM. Each row of the table The third byte of data indicates the number of bits up to the next row of data.This is aimed at high-speed table searching.

Now, FIG. 8 shows a method for searching the wiring table and the film wiring logic table. The procedure is 1. Compare all new and old data in the monitor table, and check all input data only when there is a rare change.

If there is no change, no control is performed. This is because high-speed processing is aimed at, and because the actual switch on/off switching interval is significantly longer than one transmission time period.

2. Pay attention to the output offset and output DIOIC of CC'rBL, and search for terms with the same output in GETBL. 3.
Pay attention to the relevant data in GETBL. In the case of input data, the input eTABLE as a result of referring to the monitor table is stored in the sofa. The operator is left as is. - An example is shown in Figure 9.
DIO “6” of CIM is 1.9th DIO “C” of CIM is 0
．． When DIO “3” of the 7th CIM is 0, TABLE
The buffer will look like the figure below.

4. Perform a NOT operation on TABLE and store another buffer called MEM. This is because NOT has a higher priority than other operations. This process is
The MAKE MEMJ routine is shown in FIG. 10.

5. Stack operation is performed in MEM and stored in a buffer called CUICU. This process is rsTAcK 0
This is called the PERATIONJ routine, and its contents are shown in Figure @11.

6-: Determine the transmission data of the monitor table based on the results of C and ULCU.

According to this embodiment, the wiring logic expression has generality, can be expressed using a minimum expression method, and has the effect of enabling efficient control.

〔Effect of the invention〕

According to the present invention, since the wiring logic expression can be generalized and expressed using a minimum expression method, there is an effect that the entire integrated wiring system can be controlled efficiently and at high speed. Furthermore, since it becomes easy to make changes such as adding or deleting logic, it is possible to easily deal with changes in the input/output relationship due to changes in the manufacturer, model, etc. of the load.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing wiring logic in normal notation and reverse Polish notation, and stored in tables respectively, Fig. 3 is a rough block configuration diagram of CIM, and Fig. 4 is a diagram showing an embodiment of the present invention. The figure shows an example of a data transmission situation using a monitor, wiring, and control table. Figure 5 is an explanatory diagram of the operation procedure for each table. Figure 6 is a diagram showing an example of a wiring table. Figure 7 is a diagram showing an example of a wiring table. FIG. 8 is an explanatory diagram of the procedure of the control method, and FIGS. 9, 10, and 11 are explanatory diagrams of the specific procedure of FIG. 8. 10...CCU, 11-14...LCU, 15-1
7...CIM, 18...Microcomputer, 6
6 to 68... Photoelectric conversion module, 97... Wiring table, 98... Monitor table, 99... Control table, 301... I10 buffer, 302... Shift register, 303... Comparator , 304...
・Address decoder, 305... Fail safe register, 306... Stage decoder, 307... Stage decoder, 308... Clock circuit, 309...
...Synchronization circuit, 310...Oscillation circuit, 311...M
PU interface, 312...Mo)"f:r-ta.

Claims (1)

[Scope of Claims] 1. In a control method for an integrated wiring system in which data transmission between multiple terminals is performed by a common data transmission system under the control of a central station equipped with a computer,
A wiring logic description method for an aggregated wiring system, characterized in that connection conditions between the plurality of terminals are described in reverse Polish notation. 2. A wiring logic description method for an integrated wiring system as set forth in claim 1, characterized in that it is used for an integrated wiring system in an automobile. 3. In claim 1, a memory is provided which is used in an in-vehicle integrated wiring system and which stores a table of connection conditions between the plurality of terminals in advance, and which enables the central station to create data for transmission. A wiring logic description method for an aggregated wiring system, characterized in that it is configured to be performed by table search.