JPH01255347A - Integrated circuit for parallel/serial-serial/parallel conversion - Google Patents

Integrated circuit for parallel/serial-serial/parallel conversion

Info

Publication number
JPH01255347A
JPH01255347A JP8365388A JP8365388A JPH01255347A JP H01255347 A JPH01255347 A JP H01255347A JP 8365388 A JP8365388 A JP 8365388A JP 8365388 A JP8365388 A JP 8365388A JP H01255347 A JPH01255347 A JP H01255347A
Authority
JP
Japan
Prior art keywords
serial
data
parallel
input
data length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8365388A
Inventor
Teruo Mizumoto
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8365388A priority Critical patent/JPH01255347A/en
Publication of JPH01255347A publication Critical patent/JPH01255347A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To enable being variable a data length without extending LSIs for a parallel/serial(P/S) or serial/parallel(S/P) conversion even when an input/output data length is increased by dealing it with the extension of gate circuits and latch circuits.
CONSTITUTION: The gates of gate circuits (1-1)∼(1-N) and (2-1)∼(2-N), in which the latch circuit data concerned are housed, are opened by first decoders 1-23 and 2-23, and the data are converted to serial data by P/S converters 3-1 and 4-1. The serial data are received by controllers 2 and 1 of the other side, they are converted to parallel data by S/P converter 4-2 and 3-2, the data are stored into latch circuits (2-31)∼(2-3N) and (1-31)∼(1-3N), and necessary data are outputted by second decoders 2-11 and 1-11. Consequently, when the input/output data length is increased, it is sufficient that the gate circuits and latch circuits are extended according to the input/output data length. Thus, without extending LSIs 3 and 4, the data length of the input/output can be made variable.
COPYRIGHT: (C)1989,JPO&Japio
JP8365388A 1988-04-04 1988-04-04 Integrated circuit for parallel/serial-serial/parallel conversion Pending JPH01255347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8365388A JPH01255347A (en) 1988-04-04 1988-04-04 Integrated circuit for parallel/serial-serial/parallel conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8365388A JPH01255347A (en) 1988-04-04 1988-04-04 Integrated circuit for parallel/serial-serial/parallel conversion

Publications (1)

Publication Number Publication Date
JPH01255347A true JPH01255347A (en) 1989-10-12

Family

ID=13808410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8365388A Pending JPH01255347A (en) 1988-04-04 1988-04-04 Integrated circuit for parallel/serial-serial/parallel conversion

Country Status (1)

Country Link
JP (1) JPH01255347A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2374242B (en) * 2001-04-07 2005-03-16 Univ Dundee Integrated circuit and related improvements

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2374242B (en) * 2001-04-07 2005-03-16 Univ Dundee Integrated circuit and related improvements

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