JP2001296340A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To possibly reduce the number of pins of a tester to lower the inspection cost for testing output signals of semiconductor devices. SOLUTION: There are gates G00, G01 for inputting signals on outer output terminals P0-P3, and buffer circuits P4B, P5B contain AND-OR gates P45, P55 for switching over outputs from the gate circuits G00, G01 and data output signals D4, D5 according to a TEST signal and output signals thereof to outer output terminals P4, P5 connected to a tester. This constitution reduces the number of concerning pins of the tester with output signals down to 1/3, suppresses the cost increase of the tester and reduces the inspection cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a function of reducing the number of tester pins required in a test mode.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, an output signal from an internal circuit is normally output to an external output terminal via an output circuit (buffer circuit) provided in a peripheral portion of a chip. FIG. 7 is a block diagram showing a configuration of a part of an output unit of a conventional semiconductor integrated circuit. As shown in the figure, data output signals D0 to D5 from the internal circuit are transmitted to external output terminals P0 to P5 via buffer circuits P0B to P5B, and output to the outside by P0 to P5. The buffer circuit P0B includes an inverter P04 to which the data output signal D0 is input, a latch circuit P03 for latching the output signal of the inverter P04 in synchronization with the clock CK, and an inverter P0 to which the latch data of the latch circuit P03 is input.
2 and a buffer amplifier P01 to which the output of the inverter P02 is input. Although not shown, the buffer circuits P1B to P5B are also buffer circuits P0B
It is configured similarly to. The test for the semiconductor integrated circuit is performed using an IC tester by mounting the semiconductor integrated circuit in a socket and bringing the external output terminals P0 to P5 into contact with the pins of the socket.

[0003]

In recent years, application-specific integrated circuits (ASICs) have been developed.
In a logic integrated circuit such as an ated circuit, the number of pins is remarkably increased, and an ultra-high pin device exceeding 1000 pins has already been realized. However, as described above, in order to test a semiconductor integrated circuit by a conventional method,
Since the external output terminals of the semiconductor integrated circuit need to be brought into contact with the pins of the tester in one-to-one correspondence, the tester needs to have as many pins as the number of output terminals. As the number of pins of the semiconductor device increases, the price of the tester becomes extremely high, and as a result, the test cost rises. Alternatively, the number of pins of the tester cannot keep up with the increase in the number of external output terminals of the semiconductor integrated circuit, and the number of external terminals is limited by the number of pins of the former. An object of the present invention is to solve the above-mentioned problems of the related art. It is an object of the present invention to collect several signals output from external output terminals of a semiconductor integrated circuit in a test mode and to collect other signals at other output terminals. Output from
An object of the present invention is to eliminate the need for an expensive multi-pin tester even when a semiconductor integrated circuit has a large number of pins.

[0004]

According to the present invention, an output circuit is provided corresponding to each of a plurality of external output terminals, and an output signal from the inside is passed through the output circuit. In a semiconductor integrated circuit transmitting to an external output terminal, in some output circuits, a test signal indicating whether a test mode or a normal mode, and an output signal passing through the output circuit in the normal mode, An output signal output through another output circuit in the normal mode is input, and an output signal output through the output circuit in the normal mode according to the instruction of the test signal and an output signal output through the other output circuit in the normal mode. A semiconductor integrated circuit is provided with an output switching circuit that switches and outputs a signal.

According to the present invention, an output circuit is provided for each of a plurality of external output terminals, and an output signal from the inside is supplied to the external output terminal through the output circuit. In a semiconductor integrated circuit for transmitting, some of the output circuits include a test signal indicating whether a test mode or a normal mode, an output signal passing through the output circuit in the normal mode, and another in the normal mode. An operation result of a logic gate receiving a plurality of output signals output through an output circuit of the logic gate is input, and an output signal and an operation result of the logic gate output through the output circuit in a normal mode according to an instruction of the test signal. A semiconductor integrated circuit characterized by being provided with an output switching circuit for switching and outputting the same. Preferably, in the normal mode, a plurality of output signals output through another output circuit are input to a plurality of types of logic gates having different functions, and the operation results of each logic gate are output from separate output circuits. Input to the switching circuit.

[0006]

Next, embodiments of the present invention will be described with reference to examples. FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a time chart of the semiconductor integrated circuit shown in the circuit diagram of FIG. In FIG. 1, the same reference numerals are given to the same parts as those in the conventional example shown in FIG. The present embodiment is different from the conventional circuit shown in FIG. 7 in that the present embodiment includes a 4-input AND gate G00 and a 4-input NOR gate G01 to which output signals of external output terminals P0 to P3 are input. In addition, a gate that switches output signals of these gates with a test enable signal TEST
This is the point formed in the buffer circuits P4B and P5B.

The output signals of the external output terminals P0 to P3 are supplied to a 4-input AND gate G00 and a 4-input NOR gate G01.
Are connected respectively to the input terminals. AND gate G
00 is output from the AND gate in the buffer circuit P5B.
The input signal to one input terminal of the AND gate P55 ₁ of the OR gate P55, and the output signal of the NOR gate G01 is supplied to the A / OR gate P45 in the buffer circuit P4B.
It is input to one input terminal of the ND gate P45 _1. The test enable signal TEST is input to the other input terminal of the AND gates P45 ₁ and P55 _1. The test enable signal TEST is further inverted by the inverters P46 and P56, and the AND of the AND / OR gates P45 and P55.
It is input to one input terminal of the gate P45 ₂ and P55 _2. The other input terminal of AND gate P45 ₂ and P55 _2, the output signal of the inverter P42 and P52 due to the data output signal D4, D5 is input. AN
The output of the D / OR gate P45 is a buffer amplifier P41
And the output signal of the amplifier P41 is transmitted to the external output terminal P4. Similarly, an AND-OR gate P
The output of 55 is also transmitted to the external output terminal P5 via the buffer amplifier P51.

Next, the operation of the circuit of FIG. 1 will be described with reference to FIGS. Here, it is assumed that the clock CK is at a high level for a certain period from timings T0 to T3.
At timing T0, TEST is low level, D0
Since D5 is at a high level, the external output terminals P0 to P3 are held at a high level. As a result, the AND gate G0
The output of 0 becomes high level. Further, the output of the NOR gate G01 to which the same signal is input becomes low level. The signals are AND / OR gates P55 and P4, respectively.
5, and cannot be passed through the AND gates P45 ₁ and P55 ₁ because TEST is low level. On the other hand, the TEST corresponds to the inverters P46 and P56.
Since the high level is inverted is input as the control input signal to the AND gate P45 ₂ and P55 ₂ of AND · OR gate P55 and P45 by, D4, D5 intact can pass. As a result, high levels of D4 and D5 are output to the external output terminals P4 and P5.

Next, between timings T0 and T1, D0 to D
When 5 changes to low level, the external output terminals P0 to P3 change to low level in synchronization with the rise of the timing T1. As a result, the output of the AND gate G00 goes low, and the output of the NOR gate G01 goes high. However, since TEST is still at the low level at this point, the external output terminals P4 and P5 output the low level of D4 and D5 as they are. Next, TEST is T1 and T2
During the period (T4), and changes to a high level.
Are also turned to the high level, the external output terminals P0 to P3 go to the high level at the rising timing of T2. As a result, the output of the AND gate G00 goes high and the output of the NOR gate G01 goes low. At this time, since TEST is at the high level, these signals are AN
AND gate P45 between D-OR gate P55 and P45
₁ and P55 ₁ , but at the same time TEST is inverted by inverters P46 and P56 and input to the control input terminals of AND gates P45 ₂ and P55 ₂ and DEST
4. Block the passage of D5. As a result, the external output terminal P
4, low and high levels of G01 and G00 are output to P5. Thereafter, the same operation is repeated at timing T3.

As described above with reference to the timing chart of FIG. 2, while TEST is at a low level, the signal passes through D4 and D5 regardless of the output state of the AND gate G00 and the NOR gate G01. Therefore, the test of D4 and D5 may be performed during this period. Next, D0 to D
When the test 3 is performed, TEST is set to the high level and D
4, block D5. Assuming that D0 to D3 all output expected output signals, AND gates G00 and NORG are output for all combinations of those signals.
01 outputs a signal as expected, and the signal is P
4. Output from P5. Now, assuming that a stuck-at fault in which D0 is always at a low level occurs, the AND gate G
The output signal of 00 is fixed at a low level. Where D
When the signals output from P4 are monitored by operating so that D1 to D3 are at a low level and D0 is at a high level, a stuck-at fault occurs in which D0 is at a low level because P4 is at a high level. Can be detected.

Assuming that a stuck-at fault occurs in which D0 is always at the high level, the output signal of the NOR gate G01 is fixed at the low level. Here, P1 is operated so that D1 to D3 are at a high level and D0 is at a low level.
When the signal output from P5 is monitored, since a high level is output from P5, it is possible to detect that a stuck-at fault in which D0 is at a high level has occurred. D
The same can be detected when stuck-at faults occur in 1 to D3.

In the first embodiment described above, since data for six pins of the external output terminals P0 to P5 can be output to two pins P4 and P5, the number of pins of the tester related to the output signal is one. / 3. Gate G0
By increasing the number of output terminals grouped by 0 and G01, the required number of pins of the tester can be further reduced.

FIG. 3 is a block diagram showing a second embodiment of the present invention. This embodiment differs from the first embodiment shown in FIG. 1 in that the gates for receiving the signals of the external output terminals P0 to P3 are different from the AND gate and the NOR gate of the first embodiment in that the four-input NAND gate is used. The point is that a gate G02 and a 4-input OR gate G03 are used. The operation is almost the same as in the first embodiment (in the timing chart of FIG. 2, the levels of P4 and P5 when TEST is at a high level are inverted). In this way, by receiving the signal of the external output terminal to two gates having different functions and enabling each to be output from a separate output terminal, even if the number of pins of the tester is reduced, the malfunction of the semiconductor integrated circuit can be reduced. Can be detected. Note that the combination of two gates that receive signals from a plurality of external output terminals is an AND gate and an OR gate,
Alternatively, a NAND gate and a NOR gate may be used.

FIG. 4 is a block diagram showing a third embodiment of the present invention. This embodiment is different from the first embodiment shown in FIG. 1 in that an AND / OR gate for switching an output signal provided in the buffer circuits P4B and P5B is NO.
R / NOR gates P47 and P57. The operation is almost the same as in the first embodiment.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention. This embodiment is different from the first embodiment shown in FIG. 1 in that an AND gate for receiving signals from a plurality of external output terminals is provided.
The gate and the NOR gate are omitted, and the buffer circuit P
1B, a buffer amplifier P11, an inverter P12,
The point is that an AND / OR gate P15 is provided in addition to P14 and the latch circuit P13. In this embodiment, T
In the normal mode in which EST is at the low level, D0 and D1 are output from P0 and P1, respectively, and in the test mode in which TEST is at the high level, D0 is output from P1.
According to this embodiment, the required number of pins of the tester related to the output signal can be reduced to half.

FIG. 6 is a block diagram showing a fifth embodiment of the present invention. This embodiment is different from the first embodiment shown in FIG. 1 in that the gates receiving the output signals of P0 to P3 are A
Only the ND gate G00 is provided, and the NOR gate G01 is omitted. Accordingly, in the test mode, the output terminal P5
(Not shown) does not reflect the contents of the output signals of P0 to P3. According to the present embodiment, although the test function is reduced as compared with the first embodiment, the number of tester pins related to output signals can be reduced to 1/5.

[0017]

As described above, the semiconductor integrated circuit according to the present invention is such that the output signal output from the original external output terminal in the normal mode is output from another external output terminal in the test mode. Therefore, the required number of pins of the tester can be reduced, and an expensive tester can be avoided. Alternatively, the number of pins of the semiconductor integrated circuit to be manufactured does not have to be limited by the number of pins of the tester. Also, by combining a plurality of external output signals into an AND gate or a NOR gate and outputting the signals to two external output terminals separately,
The required number of pins of the tester can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a third embodiment of the present invention.

FIG. 5 is a block diagram of a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a fifth embodiment of the present invention.

FIG. 7 is a block diagram of a conventional example.

[Explanation of symbols]

CK clock D0, D1, D2, D3, D4, D5 Data output signal TEST Test enable signal P01, P11, P41, P51 Buffer amplifier P02, P04, P12, P14, P42, P44, P
46, P52, P54, P56 Inverters P03, P13, P43, P53 Latch circuits P0B, P1B, P2B, P3B, P4B, P5B Buffer circuits P0, P1, P2, P3, P4, P5 External output terminals G00 4-input AND gate G01 4-input NOR gates G02 4-input NAND gate G03 4-input OR gate _{P45 1, P45 2, P55 1} , P55 2 AND gates P15, P45, P55 AND · OR gate P47, P57 NOR · NOR gate

Claims (6)

[Claims] An output circuit is provided corresponding to each of a plurality of external output terminals. In a semiconductor integrated circuit for transmitting an output signal from the inside to an external output terminal through the output circuit, some of the output circuits Is a test signal that indicates whether the mode is the test mode or the normal mode, an output signal that passes through the output circuit in the normal mode, and an output signal that is output through another output circuit in the normal mode. An output switching circuit that switches and outputs an output signal output through the output circuit in the normal mode and an output signal output through another output circuit in the normal mode in accordance with the instruction of the test signal. Semiconductor integrated circuit. 2. An output circuit is provided corresponding to each of a plurality of external output terminals, and in a semiconductor integrated circuit for transmitting an output signal from the inside to the external output terminal through the output circuit, a part of the output circuits is provided. Is a logic that receives a test signal indicating whether the mode is the test mode or the normal mode, an output signal passing through the output circuit in the normal mode, and a plurality of output signals output through other output circuits in the normal mode. An output switching circuit that receives an operation result of the gate and that outputs an output signal output through the output circuit and an operation result of the logic gate in a normal mode in accordance with an instruction of the test signal and outputs the operation result. A semiconductor integrated circuit characterized by the above-mentioned. 3. In the normal mode, a plurality of output signals output through another output circuit are input to a plurality of types of logic gates having different functions, and the operation results of each logic gate are output from separate output circuits. 3. The semiconductor integrated circuit according to claim 2, which is input to a switching circuit. 4. The plurality of types of logic gates having different functions are a NAND gate and a NOR gate or a NAND gate.
4. The semiconductor integrated circuit according to claim 3, wherein the combination is any one of a gate and an OR gate, an AND gate and a NOR gate, or an AND gate and an OR gate. 5. An output switching circuit comprising: two first-stage gates controlled by the test signal or an inverted signal thereof; and a second-stage gate to which output signals of the two first-stage gates are input. Each of the first-stage gates has an output signal that passes through the output circuit in the normal mode, an output signal that is output through another output circuit in the normal mode, and an output signal that is output through another output circuit in the normal mode. 2. The operation result of the logic gate to which a plurality of output signals are inputted is inputted.
5. The semiconductor integrated circuit according to any one of items 1 to 4, 6. The semiconductor integrated circuit according to claim 5, wherein said first-stage and second-stage gates are each an AND gate and an OR gate, or each is a NOR gate.