JPS62232292A - Data transmission system - Google Patents

Abstract

PURPOSE:To collate information at a high speed by detecting a nonconformity by a circuit function through a collating means for comparing previously transmitted data and data to be transmitted at the present time in parallel every bit. CONSTITUTION:The receiving data 411 from a terminal processor received by a central control unit is transmitted to an LCU as transmission data 412 via a shift register 413 consisting of 1 bit shift registers 401-403. At this time, the contents of the shift register 413 are stored in a fail safe register 414. After the completion of one transmission, the information from the same LCU is brought again as the receiving data and stored in the shift register 414. At this time, the contents of the shift register 413 and the fail safe register 414 are collated. In this manner, when performing a multiple data transmission, the information before the transmission of the respective slave stations in a master station can be collated to the information after the transmission in hardware, so that the trasnmission data can be collated at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multiplexed data transmission method, and more particularly to a data transmission system suitable for high-speed data transmission in an automobile.

[Conventional technology]

For example, a large number of electrical devices such as automobile Vch channels and various electrical devices using motors as actuators, and various sensors and actuators for automatic storm control are installed, and the number of these devices is increasing as automobiles become more electronic. , increase 7
He is on his way to 70.

For this reason, if the wiring was done independently for each of these many electrical devices as in the past, the wiring would be extremely complex and large-scale, resulting in increased cost, weight, and
This causes major problems such as an increase in space.

Therefore, as one means to solve these problems, it has been proposed to simplify the wiring by using a multi-single transmission system that allows transmission of a large number of signals with a small number of wiring lines.

The fifth page shows an example of an in-vehicle integrated wiring system using such a multiplex transmission method. An optical fiber cable OF is used as a signal transmission path, and central control mrltc CU (
Central Control Unit).

Hereinafter simply referred to as CCU. ] and multiple trend processing devices L
CUs (Local Control [Jnit], hereinafter simply referred to as LCU) are commonly connected by optical signal channels, and an optical branch connector OC is provided at the OF branch point. The CCU is installed near the dash board of an automobile and controls the entire system. The LCUs are distributed and installed near various electrical equipment such as various switches SW, indicators such as meters M, lamps L, and sensors S, which are installed in large numbers in the automatic layer. C.C.
The part VC where U and CU are connected to (JF') is a photoelectric conversion module U that converts optical signals and electrical signals in both directions.
/E is provided.

Equipped with a CCUfl microcontroller/computer and has a communication function using serial data, LCUK is a communication circuit CI M
(Communication Interface
Abbreviation for Module. Hereinafter, it will simply be referred to as CIM. ) is provided, the CCU selects one of the LCDs, exchanges data between them, and repeats this process.
Multiplex transmission via one channel (JP) is possible, and complicated and extensive wiring inside the car can be simplified.

In addition, regarding this type of conventional technology, 1%
An example thereof is disclosed in Japanese Patent No. 05490.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, when the CCU exchanges information with I and C[J, it must perform information verification in one time series. Specifically, the information before transmission of Vcilt%L CU is compared with the information after transmission for the number of LCUs, and if there is a change in information, CCLI issues a control command to I and CUK. It means. The information in this case includes, for example, a change in the on/off value of the switch SW, a change in the reading on the scale of the meter M, and the like. Conventionally, such information collation riLcU information was stored in an accumulator or RAM (Random Access Memory).
), etc., and this was done using software as a binary information comparison of 0.1. In other words, information verification is a bit shift.
1. This was done every 1, 3, and 3 times, and the time required for information verification increased almost in proportion to the amount of information required for one transmission.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission system that enables high-speed information collation and reduces the burden of conventional software.

In addition, in the conventional technology, information verification must be performed after temporarily storing the information before transmission and the information after transmission in an accumulator or RAM, which lengthens the information verification time.
Furthermore, it was necessary to secure an information collation memory area in advance. Another object of the present invention is to eliminate the need for an information collation memory area and to shorten the information collation time by efficiently using a part of the transmission circuit.

[Means to solve the problem]

The above purpose is to change the conventional software-based information verification to hardware-based verification, and to
The shift register in M is used directly without storing it in the external 81SRAM, etc., and the contents in the register are compared with the contents in the fail-safe register, so that data is read continuously.

[For Kui]

For information verification by hardware, the information before transmission of each LCU should be saved in advance in a register that is part of the transmission circuit, and the updated information after transmission should be saved in another V3 register, etc. , each bit of both registers is checked by hardware. As a result, information collation time is shortened compared to the case where register bit foot operations are performed many times to collate information. In addition, since a part of the transmission circuit is directly used as a data matching area, there is no need to store LCU information in another memory and load the results back into the LCU, saving memory and speeding up information matching. become part of the process.

〔Example] Hereinafter, one aspect of the present invention will be explained in detail.

FIG. 3 is an overall block diagram showing an example of a system to which an embodiment of the present invention is applied. #
(corresponding to CCU in Figure 5), 102 is CIM, 103~
105 is a terminal processing unit (corresponding to the LCU in FIG. 1), 10
6 to 111 are external loads.

112 is a signal transmission path (corresponding to OF in FIG. 1). In this embodiment, 112 is shown for only the electrical signal transmission path. Therefore, 101. and 103~]05Vc is O/E
>(Unnecessary, 103 to 105 are essentially only CIM.

Computer C microcomputer) includes tr central processing! 11101 is a transmission path 112 and each terminal processing gci11
03 to 105, and transmits data to and receives data from external loads 106 to 111 using a multiplex transmission method.

FIG. 4 shows a rough block configuration of one embodiment of each terminal processing device 103 to 105. The received signal R input from the transmission path 112, XDtI'i is supplied to the synchronization circuit 309, and is sent from the 1 excavation circuit 310. Synchronize the glue a-tsuku.

XTAL d is an input terminal of a crystal oscillator installed in each terminal processing device, and gXTAL is an output terminal. After synchronization, the clock circuit 308 is provided with a clock that is asynchronous with the clock component of the signal XD. Based on the clock signal, this clock circuit 308 provides two-phase clocks φ and φme in which the five phases are separated by half a period, and these signals are sent to the stage counter 306 .

φ8 is sent, and the stage counter 306 recognizes T by counting up the status of the terminal processing device, such as reception and transmission, based on the signal. Then, stage decoder 307#: decodes the 11th section of the t stage counter and sends a control signal to the processing at as appropriate.

On the other hand, external loads such as 106 to 111 in Figure @3 are input/output terminals from the I10 buffer 301! Il/C connection is made. This terminal can select input/output as appropriate, and its address is specified by the address decoder 304.
The values of address value input terminals ADDR, 0-ADDR5 are decoded and given.

Now, the data RXD received as serial data is sent to the 25-bit shift register 302Kffl. By performing parallel data transmission with the eI10 buffer 301 mentioned above, transmission in the appropriate direction is possible. Furthermore, if a transmission abnormality occurs, the data in this shift register 302 is transmitted in parallel to the fail safe register 305, where the information is held. These 10 buffers 301 and 7 fail safe registers 305
Bidirectional transmission is also possible.

The control signal is sent to the MPU innotaface section ax1. which controls the state of the MPU. C such as transmit mode, receive mode, etc.
A mode decoder 312 that defines the iM mode. This is provided by a comparator 303 or the like that detects address errors. Finally, the received data that has been transmitted to the shift register 302 is transferred to the buffer 3 of the process 10 as the transmitted data
01 to external loads 106-111. Also,
Condition code register 313d shift register 302. Creates control commands for the I10 buffer 301 and transmits data via the bus rhino.

Next, FIG. 1 shows an embodiment of the present invention.
It is assumed that the data is transmitted to the LCU as transmission data 412 via a shift register 413 (corresponding to shift register 302 in FIG. 43) consisting of 1-bit shift registers 401 to 403. that time.

The contents of this shift register 413 are stored in 7 fail safe receipts 414 Vl. Therefore, the fail-safe register 414 has a 1-bit fail-safe register.
Assuming that 5g is made from 04 to 406, 401
The data is transmitted after the value of each bit is copied in advance to each bit of the fail-safe register 414, such as the data of 404 is transferred to 404 and the data of 402 is transferred to 405. In this case, when there is only one LCU for the CCU, the fail-safe register 414 is used in this way, and when there are multiple r, I, C[J, R, AM, etc. are used to Ailsey 7 register and T
Ru.

Then, after the first transmission is completed, information from the same LCU is again provided as received data and is stored in the shift register 414. The S, EC)R gates 407 to 409 perform an EOR (Exclusive
OR, ), and use the result as the input terminal of the 0-ordinary gate 41O, and similarly, the BUR of 402 and 405, ,
Take E (JR, of 403 and 406 and use it as the input terminal of 410. Therefore, OR, goo) The output of 410 is input 1
If any one of M is "H", it becomes "H". In other words, the shift register 413 and the 7 fail safe register 41
If the contents of 4 completely match, an "L" flag is given to the condition code register 415, and if any one bit does not match, an "H" flag is given. Condition code register 4
15H Based on the flag, shift register 302. I1
It becomes possible to generate control signal 2 for the 0 buffer 301.

FIG. 2 shows another embodiment of the present invention.

@1 The number of inputs of the OR gate 41O in '44 in the figure matches the number of bits of the shift register 413.

This is an alternative solution to prevent the 16-bit shift register from requiring 16 people. That is, according to this embodiment, when performing bit comparison between the shift register 513 and the 7 fail safe register 523, 4
Multi-input NA using bit comparators 524-525
The number of inputs to the ND gate 526 is reduced to one-fourth, so its basic configuration is almost the same as that in FIG. 514 to 517 is performed by a 4-bit comparator 524, and similarly, the output terminals of the core comparators 524 to 525 are connected to the multi-input NAND gate 52.
6 input.

According to this embodiment, it is possible to perform information matching between old data and new data in hardware using the circuit configuration, which eliminates the need for processing that must be performed in software using 77 bits. It enables high-speed data transmission and reduces the burden on software.

〔Effect of the invention〕

According to the present invention, when multiplexed data transmission is performed, it is possible to perform hardware-based verification of information before transmission of each slave station at the master station and information after transmission, so high-speed verification of transmitted data is possible. Make it possible.

As a result, this has the effect of enabling high-speed signal transmission within a vehicle. Furthermore, since a part of the transmission circuit is directly used as a data collation area, there is no need to read or write information on the LCU circle to another memory, which has the effect of saving memory and speeding up information collation.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the data transmission system according to the present invention, Fig. 2 is a block diagram showing another embodiment, and Fig. 3 is an example of an automobile internal wiring system. FIG. 4 is a block diagram showing an example of seven data transmission systems to which the embodiment of the present invention is applied, and FIG.
! J is a more detailed explanatory diagram of the in-vehicle integrated wiring system.

Claims (1)

[Scope of Claims] 1. A master station and at least one slave station are provided, and data consisting of a plurality of bits is sequentially exchanged between the two by a data sending operation from the master station to the slave station, and In a data transmission system in which this data transmission operation from the master station to the slave station is performed only when there is a mismatch between the data sent last time and the data to be sent this time, the previously sent data and the data to be sent this time are 1. A data transmission system characterized by comprising a collating means for comparing each bit in parallel, and the collating means detects the mismatch by means of a circuit function. 2. In claim 1, the collation means:
A data transmission system comprising two 1-bit buffer registers and configured to detect the mismatch by comparing corresponding bits of these buffer registers. 3. The data transmission system according to claim 2, wherein one of the buffer registers is a shift register for data transmission.