JP2764858B2 - Data transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] [0001] The present invention relates to a data multiplex transmission system.
The communication mode used for the system, especially the operation mode
Can be selected arbitrarily and can be configured with one type of terminal device.
Data transmission system. [0002] 2. Description of the Related Art For example, various lamps are used for automobiles and the like.
Electrical components such as motors and motors, as well as various
Many electrical devices such as sensors and actuators are arranged,
The number will increase with the increasing use of electronics in automobiles.
It's going on. For this reason, as in the prior art, these many
Since the wiring was performed independently for each air device,
Is extremely complicated and large-scale wiring.
Cost, weight, space, or mutual
A major problem such as the occurrence of interference occurs. [0004] Therefore, a method for solving such a problem.
As one of them, transmission of many signals is possible with less wiring
The simplification of wiring by the multiplex transmission method has been proposed.
For example, Japanese Patent Application No. 57-175 filed by the present applicant.
No. 35 (see JP-A-58-70657).
I can do it. [0005] FIG. 1 is a block diagram of the multiplex transmission system.
1 shows an example of an integrated wiring system in a vehicle. The system shown in FIG.
System uses optical fiber cable OF as signal transmission path
The central control unit CCU (hereinafter simply referred to as CCU).
This is an abbreviation of Central Control Unit) and multiple ends
End processing unit LCU (hereinafter simply referred to as LCU.
This is an abbreviation of Local Control Unit).
Fiber optic cable OF
Is provided with an optical branching connector OC. [0006] The CCU is located near the dashboard of the car.
Any suitable place to control the entire system
It has become. LCU has various operation switches SW,
Display such as meter M, lamp L, sensor S, automobile
A predetermined number near the electrical devices installed in the
They are distributed. The CCU and each LCU are
Optical signal and electrical signal are connected to the cable
Photoelectric conversion module O / E that converts
Have been. The CCU has a microcomputer and a serial
It has a data communication function using ALDATA,
Each LCU has a communication processing circuit CIM (hereinafter simply referred to as CIM).
Say. In addition, this is the Cimmunication Interface Adapter
) Is provided, and the CCU sequentially selects one of the LCUs
And exchange data with the LCU.
1 channel fiber optic cable by repeating
Multiplex transmission is possible via OF, and complicated and large-scale
The wiring in the vehicle can be simplified. For use in such an integrated wiring system in an automobile.
FIG. 2 shows an example of a data transmission system to be used. FIG. 2 shows the entire system of the data transmission system.
In the figure, reference numeral 10 denotes a central processing unit.
(Corresponding to the CCU in FIG. 1), 20 is a signal transmission path (optical
(Corresponds to fiber cable OF), 30-32 are end-treated
Device (corresponding to the LCU in FIG. 1), 40 is an analog digital
Converters (hereinafter referred to as A / D), 51 to 58 are external negative
It is a load. In this example, the signal transmission path 20 is
The case where the air signal transmission line is used is shown.
The central processing unit 10 and the terminal processing units 30 to 32
No photoelectric conversion module is required, so the terminal processing device
The contents of 30 to 32 are substantially only CIM. Computer (microcomputer)
The central processing unit 10 includes the
Combined with 30-32, various sensors, lamps, activators
External load 51 composed of an electric device such as a heater or a motor
-58 and the data from these
The acquisition is performed by the multiplex transmission method. At this time,
External loads 57, 58 such as sensors that output log data
Is connected to the terminal processor 32 via the A / D 40,
Transmission operation using digital data is now possible
I have. What is the signal transmission path 20 if it is bidirectional?
Not only electrical signal transmission systems, but also optical
Signal transmission system, etc.
The formula is the so-called Half Duplex method, with central processing
One of the plurality of terminal processing devices 30 to 32 from the device 10
One of the terminal processing devices and the middle
Transfer of data with the central processing unit 10 is performed through the transmission path 20.
Are performed alternately. [0011] Multiplex transmission using such a half-duplex system is not possible.
Therefore, the data sent from the central processing unit 10 includes
An address indicating the destination is attached and received from the transmission path 20.
Address attached to the data
Only one of the terminal processors that recognizes
To answer. As described above, the address from the central processing unit 10 is
Address according to the data sent with
Terminal processing that understands and determines that it is its own
Only one of the devices responds and centrally processes its data.
The above half-duplex system is transmitted to the
Thus, a data transmission operation can be obtained. Also, in this example, each of the terminal processing devices 30 to
Thirty-two functions are consolidated into specific ones, and these terminal processing devices
30-32 LSI (Large Scale Integrated Circuit)
ing. And the specific function at this time is
Data transmission function, that is, multiplex transmission by half-duplex system
Functions required for A / D and A / D attached to each terminal processing device
It has two types of functions to control external devices such as
You. As a result, the exclusive use of the data transmission function
For example, integrated wiring systems in automobiles
When applying to a system, use the half-duplex
Transmission speed, address bit number, etc.
You can decide. Further, in this multiplex transmission system,
Utilizes the functions of the terminal processing device that has been made into an LSI as it is
And the central processing unit 10ApplicableAnd
As a result, the central processing unit 10 also has a data transmission function.
General-purpose computers (such as microcomputers)
) And the above-mentioned LSI terminal processing device 33
The central processing unit 10 can be configured only by combining
Software required for the computer of the central processing unit 10
In addition to reducing the load on the wear side,
The versatility of the finishing device can be increased. As a result, as described above, the above-mentioned LSI and specialized
Can be used more advantageously.
You. For such a common use, these terminal processes
Processing devices 30 to 32 (hereinafter, also referred to as CIMs)
U) and CIM 33 are all made in the same configuration,
Depending on the mode settingDIO mode, AD mode, MPU mode
Any of the three modes can be selected and operated
I am getting it. The DIO mode refers to the CIM
Required when used as 30-31 in FIG.
The AD mode is hereinafter referred to as the AD mode.
This is an operation mode required for M32, and the MPU mode
This is an operation mode required for the CIM 33. An example of such an LSI-based CIM is
As shown in FIG. In FIG. 3, reference numerals 61 to 84 denote LSI circuits.
A terminal pin of the package, 60 indicates a package. end
Terminal pins 61 and 62 are for power supply, and terminal pin 63 is for resetting.
It is for inputting a cut signal. The terminal pin 64 is connected to the transmission line 20 (FIG.
2), and the received signal RXD is input. Terminal pin
The clock 65 is for clock input, and is, for example, a 4 MHz clock.
Lock is supplied. Terminal pin 66 is coupled to transmission line 20
And serves to output a transmission signal TXD.
You. Terminal pins 67 to 70 receive address data ADDR.
4 bits for power. The address data ADDR is
Data indicating the destination of data during data transmission
However, in this CIM, the address data AD
Make the above mode setting by DR.
You. Terminal pins 71 to 84 are for connection with an external device,
Used for input / output of data according to the operation mode described above.
Or for transmission of control signals. Reference numeral 101 denotes a control circuit.
01 is a sequence counter 303 and a sequence decoder
304, and various control signals required within this CIM.
Signal is generated as the sequence counter 303 advances.
And work to advance the operation of this CIM sequentially.
I do. Reference numeral 102 denotes a synchronization circuit, which is a synchronous circuit of the received signal RXD.
Clock φ synchronized with start bit_MAnd φ_SWork to make
To Reference numeral 104 denotes a 24-bit shift register.
Transmission and reception of real data, or serial data and
Used for mutual conversion between parallel data. 105
Is a 14-bit input / output buffer.
Exchanges parallel data with the
It works. An A / D control circuit 106 includes an external A / D control circuit.
It functions to control the D converter 40 (FIG. 2). 30
Reference numeral 6 denotes address data, which is externally provided through terminal pins 67 to 70.
According to the address data ADDR set and input from the section
A predetermined signal is generated, and each bit of the I / O buffer 105 is
Determine the input / output direction of the
It functions to output a signal for conversion. Reference numeral 307 denotes an address comparison circuit, which is a terminal pin 6
Address and shift register 10 set in 7 to 70
4 and the data stored in the predetermined bits
To determine the address of the received data.
U. 308 is an error detection circuit, which transmits the received data
Check for errors and determine when
If the dresses do not match, the operation of this CIM
Works to reset. Next, the address by the terminal pins 67 to 70
The setting will be described. As already explained, FIG.
In the system, the CIM on the LCU side has different
Address is assigned, and based on this address,
Multiplex transmission of data by the duplex method is now performed.
ing. This address is stored in each CIM
Connected to comparator 307
Four terminal pins 67-70,
Data ADDR to be given to input₀~ ADDR_ThreeBy this
The address of the CIM is specified. For example, the CIM
To specify the address of “10”, the address
Data ADDR₀= 0, ADDR₁= 1, ADDR_Two= 0,
ADDR_Three= 1, and (101
0) may be input. In this CIM, data "0" is not connected.
Ground potential, data “1” is power supply voltage V_ccRepresented by
Therefore, for the address “10”, the terminal pin 67
And 69 are grounded, and terminal pins 68 and 70 are connected to the power supply.
Will be. In this CIM, address data is
ADDR is also input to the address decoder 306, and
Controls the directionality of the I / O buffer 105.
It has become so. As a result, specify the address
And 14 terminal pins 71 to 8 of the I / O buffer 105
Determine which of 4 becomes data output port
Is done. In this CIM, the address is
It corresponds to the number of output ports as it is. Follow
Now, if the address is defined as "10", the I / O
10 out of the 14 terminals of the
Control is performed so that the remaining four ports become input ports. Although omitted in FIG. 3, this ad
The output of the address decoder 306 is the sequence of the control circuit 101.
Also provided to the decoder 304 and other circuits.
As a result, as shown in FIG.
It can be switched. That is, in this example
Indicates that the CIM with the address set to “0” is in MPU mode
With C, the address is set between "1" and "D".
IM is in DIO mode, and the address is "E",
CIM set to any of “F” is in AD mode
Each is operated. Next, in each of these operation modes,
Will be described. First, is the address "1"?
To "D" and set to DIO mode
Then, the CIM enters the functional block state of FIG. Therefore, the reception signal input from the transmission path 20 is
The signal RXD is supplied to the synchronization circuit 102 and the control circuit 101
Clock synchronized with the clock component of the received signal RXD
Hook φ_M, Φ_SIs provided, whereby the control circuit 101
Generates a control signal and sends the received signal to the shift register 104.
Is read serially. On the other hand, the address comparison circuit 307
Terminal processing from "1" to "D"
If one of the addresses assigned to the device is given
Address and a predetermined bit of the shift register 104.
The data read at the address position is the address comparison circuit 307
And the shift register only when they match.
The data in the master 104 is transferred to the I / O buffer 105.
And given to external equipment. The control circuit 101 advances by a clock.
Generates sequential control signals
Then, the data based on the reception signal RXD is transferred to the I / O buffer 10.
After giving it to 5, followed by an I / O buffer
Parallel data from shifter 105 to shift register 104
And transmit it from an external device to the central processing unit 10.
Serial data into the shift register 104
Prepare as. Then, this data is transferred to the shift register 10.
Read out serially from 4 and transmit as transmission signal TXD
It is sent to the road 20. At this time, the reception signal RXD
The transmitted address is directly added to the transmission signal TXD.
Transmitted from the other end connected to the transmission line 20.
Is not received by the central processing unit, while
Device 10 matches the address sent by itself.
Then, the transmission signal TXD is taken in.
Data transfer for one cycle is completed by the half duplex method
I do. In this way, the central processing unit 10 executes the next terminal processing.
Send data to the management device and repeat this
In this way, a plurality of terminal processing devices 30 to 32 can communicate with each other.
Data exchange is performed periodically, enabling multiplex transmission.
You. The data contents of the shift register 104 at this time are shown in FIG.
As shown in the DIO mode of No. 6, No. 0 to No. 5
No 6 bits are used, and 1 from No. 6 to No. 19
4 bits are allocated to data DIO of I / O buffer 105
I can Then, the four bits from No. 20 to No. 23
No. 24 is assigned to the address data ADDR of
Assigned to start bit. In addition, DIO Day
The number of bits allocated to the data is 14
Means that the I / O buffer 105 has 14 bits
Because there is. For this reason, in this CIM, I
The maximum number of external loads that can be connected to the / O buffer 105 is
There are fourteen child pins 71 to 84 (FIG. 3). The data transmission method by this system is as follows.
Asynchronous, bi-directional, two-way reverse transmission,
Digital data in NRZ (nonreturn to zero) method
The transmission waveform is shown in FIG.
As shown. That is, CIM side CIM
Received a frame that transmits data to the CIM on the LCU side
If the frame is a transmission frame, the reception frame and the transmission
Both frames are 74 bits, so one frame is 14 bits.
It has 8 bits. Then, the reception frame and the transmission frame
Have the same frame configuration.
There is a bit “0” followed by one bit for start-stop synchronization.
A start bit consisting of a bit "1" is provided.
Then, the 24-bit reception data RXD is the transmission data T
XD is transmitted in NRZ signal format, and these data
Data RXD (bar superscript) orTXD(On the bar
Attached) is transmitted. Note that this inversion
Data RXD (with bar) orTXD(Bar superscript)
The transmission is performed for transmission error checking. As already explained, in this system,
Since multiplex transmission is performed by the half-duplex method, the reception
The CCU is assigned to the first 4 bits of the
Address of the LCU to be called
ADDR is attached as shown in FIG.
TX data of the transmission frame transmitted from the LCU
The same address data ADDR is attached to the first 4 bits of D.
Transmitted. The transmission frame is transmitted from the LCU side.
Is only the LCU called by the CCU?
The address is not added to the transmission data TXD
Also, on the CCU side, the data is from any LCU
Can be immediately determined. Therefore, the transmission frame
It is not necessary to add an address to the data TXD.
And the first 4 bits of data TXD are set to L, such as (0000).
Data that does not match any address of the CU
Good. Next, the address is set to either "E" or "F".
If set to either, the CIM will be in AD mode.
The function block is switched to the state shown in FIG.
You. The A / D control circuit 106 is a terminal processing device in FIG.
A / D40 control function required when used as 32
Sensor that generates an analog signal.
Which data from external loads 57 and 58
Digitized into the shift register 104
To provide the necessary control functions. In addition,
Others are the same as the case of FIG. This CIM operates in the AD mode.
Stored in shift register 104 when set to
The contents of the data to be read are as shown in the AD mode of FIG.
8 bits from No. 0 to No. 7 are transmitted via A / D 40
Data stored from external loads 57, 58, etc.
No. 8 and No. 9 are AD channel data
No. for DIO data.
It is 10 bits from No. 10 to No. 19. In addition,
Others are the same as in the DIO mode. The AD channel data at this time is
Is the channel when using multi-channel A / D.
This is data for specifying the channel, and in this embodiment, A / D40
2 bits
Is assigned. The A / D control circuit 106 is dedicated to the situation.
With a sequence counter and sequence decoder
It operates independently of the control operation by the control circuit 101, and
Step by step and advance control sequentially. So
This controls the external A / D 40,
Analog data from up to four types of external devices
Digitally converted periodically and imported as serial data
Only four channels provided in the A / D control circuit 106.
An operation is performed so as to sequentially write data in the register of the channel. On the other hand, when the input of the received frame is completed
(Time t in FIG. 7)₀) Is written to the shift register 104
The data format is the AD mode shown in FIG.
The Q of the shift register 104₈And Q₉The bits of
Two bits of AD data are stored. There
In this case, the A / D control circuit 106
Write to the above 4 channel registers based on the
A certain AD data is read and it is shifted by the shift register 10.
Q of 4₀To Q₇Write to bits. And after this
By transmitting a transmission frame, this AD data is transmitted
Signal TXD and transmitted to the CCU.
Mode operation can be obtained. By the way, in this CIM, as described above,
Receive signal RXD and the subsequent transmit signal TX
Regardless of the D transmission process, the A / D control circuit 106
The AD data is prepared in the register inside. Follow
In this CIM, at what timing
Even if the reception signal RXD appears, it immediately follows the AD data.
The transmission of the transmission signal TXD can be performed, and the transmission of the A / D 40 can be performed.
The transmission processing is not affected by the operation, and the A / D
Transmission speed decreases due to time required for conversion operation
There is no danger. In this system, the CIM is connected to the LSI
A / D40 is externally attached for the CIM
The cost is reduced when implementing the technology. One
That is, as described with reference to FIG.
Set one type of CIM as LCU 30-31
Or as LCU 32 or CIM3 of CCU10
3 can be used. However, at this time, the A / D
When it is used as CIM30,31,33
And the general wiring of automobiles
When applied to the system, it is used as CIM32.
The number of used is used as other CIM30,31,33
A / D is included in all CIMs
There is not much merit by storing. for that reason,
The A / D is external. However, because of the external connection of the A / D,
As is evident from FIG. 8, 4 for the external A / D 40
Connection terminals are required, and when the LSI
This may lead to an increase in the number. So, in this example,
With the connection configuration as shown in Fig. 3, CIM is in AD mode
When set, 14 ports of the I / O buffer 105
Four of the ports are connection terminals for A / D 40
It is intended to be used. That is, in this CIM, the I / O buffer
The port 105 has 14 ports.
As you can see, when CIM is set to DIO mode
May all be used as input / output ports
However, only 10 ports are used at the maximum in AD mode
No, 4 ports are used for input / output of DIO data.
There is no surplus. Therefore, the remaining four ports are set in the AD mode.
To switch and use it as a terminal pin for A / D40.
For example, even if the A / D is externally connected, the number of terminal pins does not increase.
Increased versatility when implementing LSI, enabling cost reduction
Become. Next, the address of this CIM is set to “0”.
The case where the MPU mode is set and the MPU mode is set will be described.
This MPU mode is used as the CIM 33 in FIG.
Mode to provide the necessary functions when
Mode and the AD mode,
U10 microcomputer (hereinafter simply referred to as microcomputer)
), The serial data
Data to the transmission path 20 and returned in response to it.
When the incoming data is received, it is converted to parallel data.
Transfer interface operation to transfer to microcomputer
This is the mode in which you work. By the way, in the above description, FIG.
As explained above, the explanation from the viewpoint of CIM on the LCU side
Because it was mainly, CIM of CCU side to CCU of LCU side
Frames that transmit data to the IM are received frames, and vice versa
Frame transmitted from the LCU to the CCU
After that, as shown in FIG.
Frame to send data as seen from the CIM
Receives a frame when it accepts data
The description will be made as a frame. Therefore, hereinafter, a certain CIM, for example, CI
The transmission frame in M33 is another CIM, for example, CIM3.
0 indicates a received frame, while transmission on the CIM 30
The frame is a received frame in the CIM 33. FIG. 10 shows the address of this CIM.
Set to “0” and control to operate in CPU mode
This is a rough functional block diagram when
As is clear,CPU modeThen I / O buffer 1
05 (Fig. 3), A / D 40 is stopped functioning,
Are connected by a 14-bit data bus. Note that this
Terminal pins are input / output ports of the I / O buffer 105
It is used commonly with
Needless to say, And this 14
8 bits out of input / output (14) are for data
The remaining 6 bits are for control signals. Now, in this CPU mode, the shift
The data content of the register 104 is changed to the MPU mode in FIG.
Q as shown₀To Q_{twenty three}All 24 bits up to MPU
It is data, and the microcomputer is an 8-bit data bus
To access this shift register 104
It has become. Therefore, the microcomputer and the shift register 10
The transfer of data to / from 4 requires 3
Access times. On the other hand, the control circuit 101 controls the microcomputer.
Receiving the control signal,₀~ Q_{twenty three}All of
When the data from the microcomputer is stored in all the bits,
At the time t when this data is stored.
_xStarts transmission of a transmission frame as shown in FIG.
You. Thus, the transmission frame is transmitted from the CIM 33.
When sent, the CIMs 30-32 on the LCU side
One responds and then the CIM sends
Time t_xWhen transmitting 1 frame (148 bits) from
Time t when the time has elapsed_y, The shift register 104
Some of the CIMs (CIs)
Data transmitted from one of M30-32)
The portability function will end. Therefore, the control circuit 101 of the CIM 33
At this time t_yGenerates an interrupt request IRQ at
The microcomputer reads the data of the shift register 104 in response
Thus, data transmission for one cycle is completed. Note that this
Of data exchange between CIMs at the time is related to FIG.
Is the same as in the DIO mode described above.
Needless to say. The CIM described above is disclosed in Japanese Patent Application No.
8-40581, Japanese Patent Application No. 58-104880, Japanese Patent Application
No. 58-106666 and Japanese Patent Application No. 58-1066
According to the invention filed by the present applicant as No. 67,
These are described in more detail in the specifications of these applications.
Is well described. [0062] SUMMARY OF THE INVENTION
The problem illustrated is that in the data transmission system described above,
Maintain accurate fail-safe state when data transmission is abnormal
It is in. Therefore, the object of the present invention is to
Providing a data transmission system suitable for application to communication equipment
To provide. [0063] [0064] [0065] [Means for Solving the Problems]According to the first invention,
The purpose is that the data storage means is used when a transmission error occurs.
A driving signal of the electric device based on the data read from the
And writing new data to the data storage means.
Stop the write clock to prevent
Is achieved. Next, according to a second aspect of the present invention,
The purpose is to determine when a transmission error occurs
A table to store the processing data required for
Achieved by: According to the third aspect of the present invention,
For example, the purpose is to drive the electric device when a transmission error occurs.
Indicates that one of the terminals that output the motion signal has a transmission error.
This is achieved by outputting a signal. [0066] DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a CIM (terminal) according to the present invention will be described.
The processing device will be described with reference to the illustrated embodiment.
FIG. 11 shows an embodiment of the present invention.
Is a terminal pin, 305 is an abnormality detection circuit, 330 is automatic transmission
The circuit 331 is a mode decoder, and the others are FIG.
Is the same as the conventional example. The terminal pins 85 and 86 are connected to the mode select signal
This is an extension for inputting the number MS. Abnormality detection circuit 3
05 is a received signal RXD input through the terminal pin 64
And the input of the received signal RXD is predetermined.
Over a certain periodInterruptedIf this is abnormal
Generates a fail-safe control signal by determining that a failure has occurred.
do. Then, the fail-safe control signal is transmitted to the I / O
Supplied to the buffer 105 and checks the state of its output port.
It works to fix to a fixed state. The automatic transmission circuit 330 is a sequence counter
Check the count number of 303 and when it reaches the specified value
A predetermined number is loaded to the count output of the counter 303.
The control state of the sequence decoder 304 is shown in FIG.
Time t_xIn the required control state
Work. FIG. 12 is a diagram showing a configuration for inputting address data ADDR.
Four terminal pins (67 to 70 in FIG. 11) and a mode selector
Two terminal pins (85, 85,
86) only, and in this embodiment,
Depending on the matrix with the dress input mode select input,
The setting for the fixed operation mode has been started
I have. FIG. 13 shows address data and mode select.
An example of an operation mode setting in combination with a signal is shown.
In the matrix diagram, the 4-bit address data
Addresses “0” to “F” to be set and 2-bit mode
Deselect signal MS₀, MS₁What settings and what
It is shown whether the operation mode is set. Here, each function will be described.
You. The connection mode refers to the operation mode of the entire CIM.
The operation modes of MPU, DIO, and AD are already
As described above. The address is set to “0” and the mode select
Connection obtained when the default input is set to other than (0,0)
The forms (TEST0) and (TEST1) are LS
Easy product testing of I-CIM
When (TEST0) is set in the operation mode
Sequence counter 303 counts at 4 times the normal speed
The DIO mode and AD
Function required for data reception and transmission in mode is normal
The test of whether or not the test can be completed in a short time. If (TEST1) is set, abnormal detection is performed.
The output circuit 305 can be operated with a short waiting time,
Can efficiently test whether the function is normal or not.
You. The input / output direction refers to the direction of each terminal of the I / O buffer 105.
Setting of the input / output direction sets the address from "1" to "D".
Already explained in the DIO mode set to one of
As described above, the address is determined by this address.
MPU mode with mode select (0, 0)
Mode, the I / O buffer 105 is made through and its direction
Is lost and becomes bidirectional, and data input and output
To be controlled by the connected microcomputer
become. On the other hand, when the address is "0", the mode is selected.
Is other than (0,0), that is, in test mode
In the AD mode of addresses “E” and “F”,
Deselect signal MS₀, MS₁I / O buffer 1
05 input / output directions are determined. The fail-safe function means that the abnormality detection circuit 3
05 and the resulting I / O buffer 1
This is a detailed explanation of the output status fixing function of 05.
As will be described later, in this embodiment, the I / O buffer
Of 105 input / output terminals, set in the output direction
If an error occurs, check the status of the terminal output data immediately.
A method of fixing the previous state (this is called maintaining the current state)
) And a method to turn it off uniformly (this is OFF
) Can be selected. The automatic transmission function means that this CIM is
Data transmission system, one-to-one transmission using only CIM
Functions required when configuring the system.
As will be described later, the automatic transmission circuit 330 is activated.
Whether or not to grant is selected depending on whether or not to make it
It has become. The selection by the mode select input is as follows.
Each function works in the same way. So, for example,
Set mode select to (1, 1) at address "0"
If it is, the CIM operates in AD (TEST0) mode
However, the I / O buffer 105 has five inputs and five outputs.
Fail safe function is OFF method and automatic transmission
The communication function is not provided. Therefore, according to this embodiment, only two
Many functions can be selected simply by adding terminal pins 85 and 86
And easily implement a multi-function CIM into an LSI.
Can be. Next, details of the abnormality detection circuit 305 and the details thereof will be described.
The failsafe function obtained by the above will be described.
In a transmission system using this CIM,
Depending on the signal transmission path such as one optical fiber cable,
Signals are being transmitted, the
Transmission failures can affect the control status of many electrical devices.
May affect the safety of automobiles.
You. Therefore, in such a system,
If an error such as a failure occurs in the transmission system, make sure
To control the operation of loads such as electrical equipment.
Also causes safety issues for cars, etc.
It is desirable to hold in a direction where there is less danger.
No. Therefore, an abnormality detection circuit is provided for this purpose.
The path 305 and the fail-safe function by this. FIG. 14 shows an embodiment of the abnormality detection circuit 305.
In the figure, reference numeral 501 denotes a counter for a timer;
2 is a flip-flop acting as a 1-bit register,
503 to 506 are AND gates, 507 is an inverter
is there. 331 is address data ADDR and mode.
Mode of operating by matrix with select signal MS
A decoder is shown, and the rest is the same as the embodiment of FIG.
The same. The counter 501 counts an appropriate clock.
And carry-out output every time the specified number is counted
Generates CO. The reset input R is
Address comparison circuit 307 (FIG. 11).
A match signal MYADDR is input. The mode decoder 331 has the configuration shown in FIG.
A switching signal is generated and supplied to a predetermined part
However, at this time, FIG.
As shown, the state of the output port of the I / O buffer 105
Is turned off irrespective of the previous state.
OFF mode and the output status up to that point are saved as is
OFF mode signal
AND gate 503 and the status quo mode signal
Output to each of the gates 504. The I / O buffer 105 includes therein
When writing data, input the clock for writing.
To be supplied. That is, the shift register
Data D is given to predetermined bits from 104 (FIG. 11)
Does not write anything to the I / O buffer 105,
Clock was supplied to input CK after applying data D
Only when the data in it can be rewritten
It is. Then, a clock is input to the input CLR.
Then, the data D written at that time is all
And the output port data becomes all 0s.
Output ports such as electric machines connected to these output ports
All loads such as electrical equipment connected to the port are OFF
Will be done. Next, the operation of this embodiment will be described.
You. Counter 501 always counts by clock
And reset only when the signal MYADDR is input.
It is. Therefore, if the signal MYADDR is not input, the
Determined by lock frequency and number of bits of counter 501
Generate carry-out output CO every predetermined period
You. On the other hand, the signal MYADDR is used for address comparison.
This is the output of path 307 and therefore this CIM is
Mode, AD mode, and automatic transmission mode described later.
Occurs each time you receive data addressed to you
You. And the data transmission system using this CIM
It is in a normal stateLimit, Predetermined period
The data must be transmitted to itself within
Has already been described. Therefore, the bit number of the counter 501 is now
And the frequency of the clock input to it
Carry-out output CO of the counter 501 is generated.
The period (this is PCO) is the data addressed to the above
Is larger than the maximum transmission cycle (this is PD) by a predetermined value.
It is assumed that it is determined that That is, PCO> PD
Suppose that it is determined to be. Then, this CIM is used for LCUs 30 to 3
2 in the data transmission system (Fig. 2) built in
While the functions of the CCU 10 and the transmission path 20 are normally maintained
Is always within a period within the above-described predetermined cycle PD.
Data transmission to the IM is performed and the address comparison
Signal MYADDR will be generated from path 307.
As a result, the counter 501 indicates that PCO> PD described above.
Count value reaches the count out due to the condition of
Before being reset and carry-out output
CO is not output and therefore the flip-flop
The loop 502 remains reset. Next, some abnormality, for example, this CIM
An error such as disconnection of the transmission line 20 for
I do. Then, after the point of occurrence of this abnormality,
I can no longer receive data for CIM,
The signal MYADDR disappears no matter how long
I will. As a result, the counter 501 indicates that this abnormality has occurred.
Immediately before the time of occurrence, data for this CIM is received.
After being reset when received,
Only the counting operation can proceed without being
You. Therefore, the counter 501 determines whether an abnormality has occurred.
The period corresponding to the above-mentioned cycle PCO has passed
At which point a carry-out output CO is generated,
Flip-flop 502 is set. Therefore, this counter 501 is used for the transmission system.
System is normal and data is being received normally.
Output CO is not generated while the flip-flop 502
Keep the reset state, but there is something wrong with the transmission system
Occurs and data cannot be received by this CIM
And output CO and set flip-flop 502
Will behave like a flip-flop.
It is possible to know the occurrence of an abnormality by the state of the rop 502
In this case, an abnormality detection function can be obtained. Next, Q of this flip-flop 502
The output is one of each of AND gates 503 and 504.
Is tied to the input. Therefore, as described above,
Is detected, and the flip-flop 502 is set.
And these AND gates 503 and 504 are activated
You. On the other hand, these AND gates 503, 50
4 has a mode decoder 331 at its other input.
The status quo mode signal and the OFF mode signal are respectively
And supplied. Note that these two types of models
Mode signals are supplied at the same time, as is clear from FIG.
It will not be done. That is, between these signals Current status mode signal (+)OFF mode signal= 1 The relationship is given. Therefore, now, the mode decoder 331
The fail-safe function selection is changed to the status quo mode.
If so, the flip-flop 50 in which the abnormality is detected
When the Q output of the second gate becomes "1", the AND gate 50
Only the output of AND gate 504 out of 3,504
It becomes “1”. Therefore, as a result, the AND gate 505
Is fixed to “0” and the clock WCLOCK (bar
-Superscript) to the CK input of the I / O buffer 105
Supply of the write clock to be performed is prohibited. Therefore, at this time, when an abnormality is detected,
After that point, data transfer to the I / O buffer 105
Writing (rewriting) is prohibited, and I /
The state of the output data of the O-buffer 105 is
The status is maintained as it was immediately before
Therefore, a fail-safe function can be obtained. On the other hand, the mode decoder 331
The safe mode is set to OFF mode.
If an abnormality is detected at this time,
Only the output of AND gate 503 among 503 and 504
Becomes “1”, and as a result, via the inverter 507
AND gate 506 is activated and clock WCLOC
Clear input of I / O buffer 105 by K (bar superscript)
The force is supplied to the CLR. Therefore, at this time, an abnormality is detected.
Immediately after that, all data in the I / O buffer 105 is cleared.
And the output data is all "0", that is, turned off.
The fail mode in the OFF mode.
Function will be provided. Next, another embodiment of the abnormality detection circuit 305 will be described.
Is shown in FIG. In this embodiment, the counter 501
Bit output Q_nIs used to display the point at which an error has occurred.
This is different from the embodiment of FIG.
Added AND gate 508 and OR gate 509
And the fail-safe function in OFF mode is activated
Output Q of the last bit of the counter 501_nThe terminal pin
It is only the point that it is taken out to one of 71 to 84,
Others are the same as those in FIG. The clock is always input to the counter 501.
The MYADDR signal is no longer supplied
A carry-out output CO is generated and flip-flop 5
This counter 501 continues counting even after 02 is set.
And the output Q of the last bit_n
Is the duty ratio of the above cycle PCO as one cycle
Are continuously obtained as pulses (rectangular waves) of 50%. Therefore, an external negative electrode to be connected to the terminal pin 71
Loads as electrical equipment, for example, room lamps for cars
If an abnormality is detected, the room lamp
The room lamp may start flashing regardless of whether it is on or off.
And the display of the occurrence of the abnormality can be performed. The OR gate 5 in the embodiment of FIG.
09 is used because the terminal pin 71 is shared.
As a result, in this embodiment, the connection to the terminal pin 71 should be made.
External load is limited to equipment like the room lamp above
Otherwise, display equipment cannot be used. Therefore, the terminal pin for output of the abnormality detection display is
It is provided exclusively for output of the AND gate 508 from its terminal pin.
If you try to extract the force directly, you can save on terminal pins
Although it cannot be obtained, the degree of freedom in use should be high
Can be. The counter 501 counts up.
Time to generate carry-out output CO
Is smaller than the data transmission period PD for one CIM.
Must be large enough for this purpose.
It is necessary to select a period PCO of, for example, 100 mS or more.
You. Therefore, for example, if the frequency of the clock is 4 MHz
If z, the bit of the counter 501 is 20 bits or more
Costly.
It gets worse. On the other hand, in the embodiment shown in FIG.
The path 102 contains a 4-bit counter, which
The frequency of the 4 MHz clock is_M, Φ_STona
And this signal φ_M, Φ_SIs an 8-bit sequence
Counter 303. In this embodiment, the sequence cow
Counter 303 carry-out output to counter 501
To be supplied as a lock so that the counter 5
The number of bits required for 01 is reduced to 8 bits
doing. Next, details of the automatic transmission function will be described.
You. So far, this CIM is shown in FIG.
It applies to data transmission systems.
Was. Then, in the system of FIG.
A CCU is provided for controlling data transmission between each other,
The system is controlled by the microcomputer etc. included in this CCU.
The whole control is appropriately performed. For this reason, it is used for CCU and each LCU.
CIM is set when MPU mode is set on the CCU side.
In this case, the data for each frame is controlled by the microcomputer.
Data TXD transmission, while the LCU side
When set to the mode, the data transmitted from the CCU side
TXD is input as received data RXD,
The transmission data TXD of its own is actually received.
Transmission is started. Therefore, a transmission system using this CIM
In order to obtain the necessary data transmission function
Therefore, a CCU equipped with a microcomputer etc. is indispensable.
A transmission system cannot be constituted by M alone. Immediately
That is, as shown in FIG. 16, two CIs are used without using a microcomputer.
M and only one OF etc. are combined, and CIM becomes M
Assuming PU mode and CIM DIO mode
However, as it is, data transmission from any CIM
Since it does not start, the data transmission function is not exhibited. this
This means that both CIMs must be in MPU mode or DIO mode.
The same goes for However, in the case of the configuration shown in FIG.
In any case, use any means to download data from any CIM.
Data transmission, then data transmission
Operation starts and data transmission continues alternately.
can do. However, transmission is started in this way.
Even so, such data transmission systems are noisy.
It is unavoidable that data transmission errors occur due to
As a result, once a transmission error occurs,
Data transmission operation will be stopped, and
The specified data transmission operation cannot be expected. On the other hand, as a wiring system in an automobile,
Relatively large data transmission system including many LCUs
Multiplex transmission between two LCUs
Is a relatively small data transmission system.
A stem may also be required. For example, a steering wheel column
Switch panel on the side of the
Wiring systems between controlled devices such as
is there. Therefore, for such a system,
If possible, use the small-scale data transmission system shown in FIG.
Use is preferred. However, such small-scale data transmission
For the transmission system, using the CIM described above
When configured, a microcomputer or the like
A control device is provided, and this CIM is provided with the function as a CCU.
Or an additional CCU for two LCUs
Must be provided separately.
There was a disadvantage that the system would be expensive. The automatic transmission function handles such a case.
Two CIMs are interconnected via a transmission path.
And the LCU's one-to-one transmission system can be used immediately
Multiple data transmission can be performed stably and small scale
Low cost data transmission system is possible,
To make an improved CIM useful for integrated wiring
Specifically, as shown in FIG.
330 to activate this circuit as needed.
It is something that has been done. The automatic transmission circuit 330 uses the CIM
The start condition of the data transmission operation is transmitted from another CIM.
Not only due to the end of receiving data
In addition to the above,
And at a predetermined time after the end of the data transmission operation by itself
Data transmitted from another CIM within
A function that adds the function of adding something
Therefore, a one-to-one transmission system as shown in FIG.
M, one CIM, eg, C
IM in automatic transmission mode (hereinafter referred to as active mode)
) And the other CIM (in this case CIM
) Without automatic transmission mode (hereinafter referred to as passive mode)
). Note that, as shown in FIG.
Is required to set the CIM to active mode.
Address from “1” to “D”
(At this time, as apparent from FIG. 13, the DIO mode
Mode) and the mode select input MS₁= 1, M
S₀= 0, respectively.
To set the address mode, set the address to "1"
To “D” and select the mode
Input MS₁= 0. Incidentally, the active mode and the passive mode
In the data transmission operation even in
There is no change in the function of the reply. On the other hand, as shown in FIG.
In a point-to-point transmission system, between CIMs
Exchange data with each other. Therefore, at this time
To enable data transmission, CIM and CIM
To the same address (limited to addresses 1 to D)
You have to set up and configure your system. Note that, in the active mode, the same
The input and output ports of the I / O buffer
Need to be inverted and configured as such
However, this point will be described later. The automatic transmission circuit 330 according to this embodiment is
It consists of a smart circuit, an inverter, and a flip-flop.
The CIM is set to active mode
Sometimes, the count output of the sequence counter 303 is
When S254 is reached, the signal LOA
D49 is generated, and S49 is set in the sequence counter 303.
It acts as a load, which allows you to
Even if no data is received, data will be
Data transmission operation is started automatically.
You. Thus, in the DIO mode, the
CIM that can be set to active mode and passive mode
And a one-to-one LCU transmission system as shown in FIG.
FIG. 17 shows the configuration of the system. Here, CIM3
4 is C in the DIO mode and the active mode is set.
IM and CIM 35 in DIO mode and passive
CIM set to the active mode. Therefore, the CIM 34 is automatically operated as shown in FIG.
Already described except that the transmission circuit 330 is activated
Operates as CIM in DIO mode, while CI
M35, because the automatic transmission circuit 330 is not activated,
Exactly the same operation as CIM in DIO mode described in
It is supposed to. Next, the configuration using the CIM shown in FIG.
Operation of the one-to-one transmission system as shown in FIG.
Will be described. As described above, C in FIG.
The basic operation of each of the IMs 34 and 35 is DIO
Mode (in particular, CIM35 is D
IO mode), so in the following description D
Focus only on the differences from the IO mode.
U. First, the engine key of the automobile is operated.
When the transmission system is turned on for
And the output of the sequence counter 303 is
It is set to S0 (this S is an abbreviation of stage).
Then, following the clock φ_MBy counting
This counter 303 advances. Thus, the counter 303 starts to advance.
When the count output reaches S25, CIM3
Both 4 and 35 become idle and receive afterwards
Just waiting for a signal to come in
turn into. By the way, in this system, FIG.
As is evident, what is coupled to the signal transmission line 20 is
There are only two CIMs 34, 35, so these are
If both enter the idle state, it will be described with reference to FIG.
As described above, the data transmission operation starts
Not. However, in FIG. 17, CIM3
4 and 35 are according to the embodiment of the present invention shown in FIG.
This sets the CIM 35 to active mode.
ing. On the other hand, as already described,
The basic operation of M is the same as that of CIM in FIG.
Therefore, even in the idle state, the CIM 34 and 35
Sequence counter 303 is clock φ_MCount
It continues as it is. Therefore, in the system shown in FIG.
CIM34,35 enters idle state after Charize
And thereafter, the CIM 35 in the passive mode
CIM 34 remains idle
Since the active mode is set, the automatic transmission circuit 33
0 has been activated, and as a result
After the count output of the counter 303 reaches S254.
Signal LODO49 is generated at the timing of
S49 is loaded to the output of the counter 303. As described above, this CIM 34,3
5 as well, as described with reference to FIGS.
Transmitted by the count data of the sequential counter 303
The sending operation is controlled. Therefore, the sequence of CIM34
When the output data of the sense counter 303 is set to S49,
The operation of the CIM 34 changes from the idle state up to D
Jump to the UMMY state, and then
25-bit "0" transmission by the increment of the counter 303
Transmission and subsequent transmission operation of data TXD from S74
Will enter. In this way, once the data is
This data is idle once transmission of
Received by CIM 35, which results in CIM 34
Data transmission to and from the D.35 is alternately performed in DIO mode.
Frame, and the two CIMs 34 and 35
Data transmission by the one-to-one transmission system starts
become. Therefore, at this time, CIM34 and CIM35
FIG. 18 shows a state transition diagram. On the other hand, the CIMs 34 and 35
Data transmission operation between the two, and a steady half-duplex system
Transmission error occurs when
If so, both CIMs 34 and 35 are idle
And the data transmission operation is stopped again. However, also at this time, the CIM 34
Is in the active mode, the sequence counter 30
When the count output of No. 3 reaches S254, the
S49 is loaded into the sense counter 303 and automatically
Data transmission starts. Therefore, according to the CIM of this embodiment,
Operating mode, select active mode or passive mode.
After the selection, the one-to-one transmission system is configured as shown in FIG.
Data transmission can always be performed stably.
Small data transmission systems at low cost
Can be Here, the mode in one embodiment of the present invention
For selection and switching of I / O buffer 105 input / output ports
explain about. As already explained, FIG.
In one embodiment of the present invention, when in DIO mode,
Mode and passive mode can be selected and set.
In automatic mode, the automatic transmission circuit 330 is activated.
But data transmission in DIO mode
The operation and other configurations are the same as those of the CIM of FIG.
For,DIOIn the mode, the port of the I / O buffer 105
Direction is determined by the address, and the address is
The number of output ports remains unchanged. For example, in the DIO mode, a 4-bit address
Address “1” to “D” correspond,
If “1”, the 14-bit I / O buffer 105
Of the ports, one bit is an output port and 13 bits are input.
Output port, 13 bits output at address "D"
One bit becomes an input port at the port. On the other hand, as already described, FIG.
In a one-to-one transmission system such as
If you do not match the 35 addresses,
Sending is not possible. In the system shown in FIG.
The data transmitted from the other CIM, for example, CIM 34
Always received only by CIM35, while CIM3
The data sent by 5 is received only by CIM34
I / O buffer 1 in both CIMs 34 and 35
Since the number of input ports and the number of output ports of 05 were the same
Is a waste of data transmission, and the number of bits that can be transmitted is limited.
It cannot be used effectively. That is, from the nature of data transmission,
In one CIM in a simple one-to-one transmission system
Output port data to the output port of the other CIM
If not received, data transmission was performed
The number of input ports on one CIM
Is equal to the number of output ports on the other CIM,
The number of output ports of one CIM is the input of the other CIM.
Most desirably equal to the number of ports. Thus, in this embodiment, the
Switching the input / output port of the I / O buffer 105
In the active mode, the operation is the same as that of the CIM in FIG.
When set to passive mode,
Conversely, the number of addresses is determined by the number of input ports.
It is so. For example, the CIMs 34 and 35 in FIG.
Is set to the address “1”, CIM3
5, among the 14 ports of the I / O buffer 105,
While one is an output port and 13 is an input port
Therefore, the output port of the CIM 34 in the active mode is
Thirteen, one input port for one-to-one transmission
The data transfer function can be fully utilized. As described above, the CI of the present invention
Power on when M is set to active mode
Later, or after data transmission is interrupted,
After the counter 303 advances to S254, the automatic transmission operation starts.
enter. Therefore, the clock φ_MData by
Transmission speed of 250Kbit/ Sec, about 1m
Automatic transmission starts in the Sec waiting time.
Is the maximum number of bits of the sequence counter 303 and the clock.
It goes without saying that the lock frequency can be set arbitrarily.
No. In the embodiment shown in FIG.
Set the time before starting automatic transmission using the
Configuration required for operation in active mode
And low cost. The active mode and the passive mode
For the CIM that can be set and operated,
Further details are described in the specification of Japanese Patent Application No. 58-104880.
It has been specified. [0145] 【The invention's effect】According to the present invention, the data transmission system
Always maintain a fail-safe state even when transmission is abnormal
Can be applied to data communication devices such as automobiles.
And maintain sufficient safetycan do.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram showing an example of an integrated wiring system in a vehicle. FIG. 2 is an explanatory diagram illustrating an example of a data transmission system using a CIM. FIG. 3 is a block diagram showing a conventional example of a CIM. FIG. 4 is an explanatory diagram showing mode switching by an address. FIG. 5 is a functional block diagram in a DIO mode. FIG. 6 is an explanatory diagram showing an example of data content. FIG. 7 is an explanatory diagram of a transmission waveform. FIG. 8 is a functional block diagram in an AD mode. FIG. 9 is an explanatory diagram of a transmission waveform. FIG. 10 is a functional block diagram in an MPU mode. FIG. 11 is a block diagram showing one embodiment of a terminal processing device according to the present invention. FIG. 12 is an explanatory diagram of a mode select input in one embodiment of the present invention. FIG. 13 is an explanatory diagram showing one embodiment of matrix selection by address input and mode select input in the present invention. FIG. 14 is a block diagram showing one embodiment of an abnormality detection circuit according to the present invention. FIG. 15 is a block diagram showing another embodiment of the abnormality detection circuit according to the present invention. FIG. 16 is a conceptual diagram of a small-scale data transmission system. FIG. 17 is a conceptual diagram showing one embodiment of a one-to-one transmission system using a terminal processing device according to the present invention. FIG. 18 is an explanatory diagram of an operation of a one-to-one transmission system using the terminal processing device according to the present invention. [Description of Signs] 60 CIM package 61 to 84 Terminal pin 101 Control circuit 102 Synchronization circuit 104 Shift register 105 I / O buffer 106 A / D control circuit 303 Sequence counter 304 Sequence decoder 305 Abnormality detection circuit 306 Address decoder 307 Address comparison circuit 308 Error detection circuit 330 Automatic transmission circuit 331 Mode decoder

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁶ Identification symbol FI H04L 29/12 H04L 11/00 340 H04Q 9/00 311 13/00 317 (72) Inventor Akira Hasegawa Daiji Koba, Katsuta City, Ibaraki Prefecture No. 2520 Co., Ltd. Hitachi, Ltd. Sawa Plant (56) References JP-A-57-25034 (JP, A) JP-A-57-92948 (JP, A) JP-A-58-70567 (JP, A) JP-A-58-86698 (JP, A) JP-A-58-136149 (JP, A) JP-A-58-149834 (JP, A) U.S. Pat. No. 4,471,456 (US, A) IEEE PROCEEDINGS Part. E COMPUTERS & DIGITAL TECHNIQUES VOL. 129, no. 6, November 1982, STEVENAGE GB, N.M. Preston et al, "Multiprocessor implementation of the logical function of a multiplexed wiring system for automobiles" pp. 223-228 33rd IEEE VEHICULAR R TECHNOLOGY CONFERENCE, 25-27 May 1983, IEEE New York, USA, Hirayama T .; et al, Fiber Optic Multiplexed Wiring System Usig a Custom Designed LSI "pp. 35-40 (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/44 G04Q 9/00 311 INSPEC (DIALOG) JICST file (JOIS) WPI (DIALOG)

Claims (1)

(57) [Claims] In a data transmission system for exchanging data between a data transmission processing device and a terminal processing device, and outputting a signal for controlling the electric device based on the received data, the terminal processing device may include: Data storage means for storing data, data updating means for updating data in the data storage means when data transmission is normally performed, and output means for outputting a drive signal of the electric device based on the received data. Further, when a transmission error occurs, a drive signal of the electric device is output based on the data read from the data storage means.
And writing new data to the data storage means.
A data transmission system in which a write clock is stopped so as to prohibit it . 2. In a data transmission system for exchanging data between a data transmission processing device and a terminal processing device, and outputting a signal for controlling the electric device based on the received data, the terminal processing device may include: Data storage means for storing data, data updating means for updating data in the data storage means when data transmission is normally performed, and output means for outputting a drive signal of the electric device based on the received data. Further, when a transmission error occurs, depending on the abnormal state, i) outputting a drive signal of the electric device based on data read from the data storage means, or ii) based on predetermined data predetermined have a selection means for selecting whether to output the drive signal of the electrical device,
The selection means, the fail-safe mode determination hand stage (Meaux
Corresponding to the selection mode of the decoder 331).
Is a table that stores the processing data required for the output of ii).
A data transmission system characterized by being constituted . 3. In a data transmission system for exchanging data between a data transmission processing device and a terminal processing device, and outputting a signal for controlling the electric device based on the received data, the terminal processing device may include: Storage means for storing data; means for updating data in the data storage means when data transmission is normally performed; and output means for outputting a drive signal for an electric device based on the received data. Further, the output means outputs a signal indicating a transmission abnormality to one of the terminals for outputting a drive signal of the electric device when a transmission abnormality occurs.