JP2612433B2 - Automotive data transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] TECHNICAL FIELD The present invention relates to a multiplex data transmission system.
Related to the communication processing circuit used for the system, especially
About automotive data transmission system suitable for wiring system
Related. [0002] 2. Description of the Related Art For example, various lamps and motors are used in automobiles.
Transmission products, as well as various sensors and antennas for vehicle control.
Many electric devices such as actuators are arranged, and the number is
Increasingly increasing as automobiles become more electronic
I'm going. For this reason, as in the prior art, these many
Because the wiring was done independently for each air device
Has become extremely complex and large-scale
Increase, cost, weight, space, or
A major problem such as mutual interference occurs. [0004] Therefore, a method for solving such a problem.
One of them is that many signals can be transmitted with few wires
The simplification of wiring by the multiplex transmission method has been proposed.
For example, Japanese Patent Application No. 57-17535 filed by the present applicant
(See JP-A-58-70657). FIG. 1 shows a multiplex transmission system of this type.
1 shows an example of an integrated wiring system in a vehicle. The system shown in FIG.
System uses optical fiber cable OF as signal transmission path
The central control unit CCU (hereinafter simply referred to as CCU).
This is an abbreviation of Central Control Unit) and multiple terminal
Processing unit LCU (hereinafter simply referred to as LCU.
ocal Control Unit) on the optical signal channel.
At the branch point of the optical fiber cable OF
Is provided with an optical branching connector OC. [0006] The CCU is located near the dashboard of the car.
Any suitable place to control the entire system
It has become. LCU has various operation switches SW,
Display such as meter M, lamp L, sensor S, automobile
A predetermined number near the electrical devices installed in the
They are distributed. The CCU and each LCU are
Optical signal and electrical signal are connected to the cable
Photoelectric conversion module O / E that converts
Have been. [0007] The CCU has a microcomputer,
Has a data communication function with real data and supports it
Each LCU has a communication processing circuit CIM (hereinafter simply referred to as CI).
It is called M. This is Communication Interface Adap
(abbreviation of tor) is provided, and the CCU sequentially selects one of the LCUs
And exchange data with the LCU.
By repeating the above, one channel optical fiber cable
Multiplex transmission via BLE OF is possible,
Simple vehicle wiring can be simplified. FIG. 2 shows an example of such a transmission system.
FIG.
0 is a central processing unit (corresponding to the CCU in FIG. 1), 20 is a signal
Transmission line (corresponding to the optical fiber cable OF in FIG. 1), 30 to
32 is a terminal processor (corresponding to the LCU in FIG. 1), 40 is A /
D and 51 to 58 are external loads. In this example,
When the electric signal transmission line is used as the signal transmission line 20,
Therefore, the central processing unit 10 and the terminal
A photoelectric conversion module is not required for
Therefore, the contents of the terminal processing devices 30 to 32 are substantially CI
M only. Including computer (microcomputer)
The central processing unit 10 transmits each terminal processing
30 to 32, and various sensors, lamps,
External load 5 composed of electric devices such as tutors and motors
Transmission of data to 1 to 58 and data from them
Is performed by the multiplex transmission method. At this time,
External loads 57, 5 such as sensors that output analog data
8 is coupled to the terminal processor 32 via the A / D 40,
Digital data transmission can now be performed.
ing. What is the signal transmission path 20 if it is bidirectional?
Not only electrical signal transmission systems, but also optical
Signal transmission system, etc.
The system is a so-called half-duplex system (central processing unit).
Device 10 to one of a plurality of terminal processing devices 30 to 32
One of the terminal processing devices and the central
The transfer of data with the processing device 10 is performed via the transmission line 20.
Are performed alternately. [0011] Multiplex transmission using such a half-duplex system is not possible.
Therefore, the data sent from the central processing unit 10 includes
An address indicating the destination is attached and received from the transmission path 20.
Address attached to the data
Only one of the terminal processing units that recognizes that there is a response
It is supposed to. As described above, the address from the central processing unit 10 is
Address according to the data sent with
Terminal processing that understands and determines that it is its own
Only one of the devices responds and centrally processes its data.
The above half-duplex system is transmitted to the
Thus, a data transmission operation can be obtained. In this system, the central processing unit 1
0 to the microcomputer and data by serial data.
And a CIM 33 having a data communication function.
Data transmission operation by the above half-duplex method via M33
Work, which allows the microcomputer
General-purpose devices without data transmission function can be used
It has become so. [0014] [Problems to be solved by the invention]In the above prior art,
A central processing unit in a data transmission system for a vehicle; and
Specifics of the communication processing circuit located at the input / output unit of the terminal processing device
Does not take into account disclosure of the general structure,
There is a problem in making the communication processing circuit an LSI module
Was. The purpose of the present invention is to make LSI modules into chips.
Disclose the specific configuration of the necessary communication processing circuit,
Sufficient miniaturization for the systemCar
Data transmission system. [0015] [0016] [0017] SUMMARY OF THE INVENTION In order to achieve this object,
Therefore, the present inventionTerminal processing equipment according to the communication control program
Communication control computer that controls data transmission to and from the
Connected to the communication control computer and the communication control computer.
The data received from the terminal processing device and the
First communication having a register for temporarily storing transmission data
A central processing unit having a processing circuit;
Data received from the processing circuit and connected to the terminal processing device.
To temporarily store data indicating the status of the external load
And an I / O connected between the register and the external load.
A second communication processing circuit having an O buffer;
Data transmission between the first communication processing circuit and the second communication processing circuit
Data transmission system for automobiles with communication lines
ComposedIt is characterized by points. [0018] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described in detail with reference to examples. FIG. 3 shows one embodiment of the present invention.
Is a schematic functional block diagram showing the basic configuration of
Control circuit 1 for performing overall operation control
01, according to the received signal RXD input from the transmission path 20
Synchronous circuit 10 for synchronizing clocks by start-stop synchronization
2. Provided in advance as 4-bit data from outside
Address data ADDR₀~_ThreeSelection of operation mode by
And address comparison of input data
The circuit 103 serially captures and transmits input data.
Shift register 104 to control data input / output.
I / O buffer 105 for performing on the parallel
Controls A / D 40 and enables analog data transmission
A / D control circuit 106 for
A clock generator 107 for generating necessary clocks
And a state where it is configured as an LSI. Address for address comparison circuit 103
The data input is 4 bits as described above, and these 4 bits
By selecting the data ADDR to be given,
Mode, AD mode, and MPU mode
To operate in one of the operation modes,
Switching of the internal function is performed. First, in the DIO mode, the CIM
Used as terminal processing devices 30 to 31 described in 2
This is an operation mode that provides the functions needed when
To do this, the address data ADDR is changed from "1" to
What is necessary is just to set to any address of "D". Next, the AD mode refers to the terminal shown in FIG.
Needed when used as CIM for processor 32
Operating mode that can provide
Indicates whether the address data ADDR is "E" or "F".
You can set a crab. And the MPU mode is
Needed when used as CIM 33 in FIG.
Operating mode to provide the function
Set the dress data ADDA to “0”.
You. The relationship between the above address setting and the operation mode is shown in the figure.
The result is as shown in FIG. Therefore, according to this embodiment, FIG.
Such a transmission system is composed of only one kind of CIM.
And the generalization of CIM becomes possible,
It is possible to fully obtain the advantages of the dedicated product and LSI.
You can do it. Next, in each of these operation modes,
The operation of one embodiment of the present invention will be described sequentially. FIG.
The CIM according to the embodiment of the present invention shown in FIG.
Or if set to any of "D", the function
The block is in the state shown in FIG.
The received signal RXD is supplied to the synchronization circuit 102 and
Synchronize clocks from lock generator 107 and control
Asynchronous with circuit 101 for clock component of received signal RXD
Is supplied to the control circuit 101.
Generates a control signal and sends the received signal to the shift register 104.
Is read serially. On the other hand, the address comparison circuit 103
Terminal processing from "1" to "D"
The address assigned to the device is given.
Address and a predetermined bit position of the shift register 104
The read data and the address comparison circuit 103
Are compared and the shift register 10
4 is transferred to the I / O buffer 105 and
Given to equipment. The control circuit 101 advances by a clock.
Generates sequential control signals
Then, the data based on the reception signal RXD is transferred to the I / O buffer 10.
After giving it to 5, followed by an I / O buffer
Parallel data from shifter 105 to shift register 104
And transmit it from an external device to the central processing unit 10.
Serial data into the shift register 104
Prepare as. Then, this data is transferred to the shift register 10.
Read out serially from 4 and transmit as transmission signal TXD
It is sent to the road 20. At this time, the received signal RXD
The transmitted address is added to the transmission signal TXD as it is and transmitted.
Therefore, the central processing unit 10 transmits the address transmitted by itself.
The transmission signal TXD
1 cycle by half duplex method
Transfer of the minute data is completed. In this way, the central processing unit 10 executes the next terminal processing.
Send data to the management device and repeat this
In this way, a plurality of terminal processing devices 30 to 32 can communicate with each other.
Data exchange is performed periodically, enabling multiplex transmission.
You. FIG. 6 shows the DIO mode shown in FIG.
A block diagram illustrating one embodiment of a CIM in further detail.
5, the same or equivalent parts as those in FIG.
In FIG. 6, reference numeral 301 denotes a reception signal RXD
A synchronous circuit for generating a start-stop synchronized clock,
302 is a two-phase clock φ_SAnd φ_MA counter that generates
303 is a counter for sequential control, and 304 is a counter for sequential control.
Counter that generates various control signals from the output of
Cans decoder, 305 is an abnormality detector, 306 is an I / O
Address decoding for input / output switching selection of buffer 105
307 is a 4-bit comparator for address comparison.
308, an error detection circuit, and 310, two AND gates.
Gate and one NOR gate, 311
Exclusive OR gate for error detection, 312
AND gate for data transmission, 313, 314 try
It is a state buffer. Note that the shift register 104
Is 25 bits (24 bits + 1 bit) and I / O buffer
The key 105 has 14 ports (14 bits). First, when the DIO mode is selected,
The A / D control circuit 106 does not operate, and the shift
The data content of the register 104 is as shown in FIG.
o 6 bits from 0 to No. 5 are not used.
The 14 bits up to No. 19 are the data of the I / O buffer 105.
Data DIO. And No.20 to No.23
Up to 4 bits are allocated to address data ADDR
No. 24 is assigned to the start bit. What
Note that the number of bits allocated to DIO data is 14
Is that the I / O buffer 105 has 14 bits.
It is because it has become something. Also, because of this,
In the CIM according to the embodiment, connection to the I / O buffer 105 is possible.
The maximum number of active external loads is 14. The data transmission method according to this embodiment is
This is called a step-synchronous, bi-directional, inverted duplex transmission method.
Digital data by NRZ (nonreturn to zero) method
The transmission waveform is shown in FIG.
It has become. That is, from the CIM on the CCU side to the LCU side
A frame for transmitting data to the CIM of the received frame,
Conversely, a frame transmitted from the LCU to the CCU is transmitted.
If it is a frame, both the received frame and the transmitted frame
74 bits, so one frame is 148 bits
ing. Then, the reception frame and the transmission frame
Have the same frame configuration.
There is a bit “0” followed by one bit for start-stop synchronization.
A start bit consisting of a bit "1" is provided.
Followed by 24-bit reception data RXD or transmission data
TXD is transmitted in NRZ signal format, and
Data RXD (bar superscript) or TXD (bar
(Superscript) is transmitted. In addition, this anti
Transfer data RXD (with bar) or TXD (with bar)
The transmission is performed for transmission error checking. As described above, in this embodiment, a half
Since multiplex transmission is performed by the duplex method, the reception frame
The first four bits of the data RXD of the
Address data of the LCU to be called
ADDR is added as shown in FIG.
TXD data TXD transmitted from the LCU
The same address data ADDR is appended to the first 4 bits of
Transmitted. The transmission frame is transmitted from the LCU side.
Is only the LCU called by the CCU?
The address is not added to the transmission data TXD
Also, on the CCU side, the data is from any LCU
Can be immediately determined. Therefore, the transmission frame
It is not necessary to add an address to the data TXD,
The first 4 bits of data TXD are
Data that does not match any address may be used. Here, returning to FIG. 6, the address of the CIM is
explain about. As described above, in this embodiment,
Is a different 4-bit CIM for the LCU.
Address is assigned, and based on this address,
Multiplex transmission of data by the duplex method is now performed.
ing. This address is stored in each CIM
Connected to comparator 307
4 inputs 2⁰~ 2^ThreeAnd these inputs
Data to be given ADDR₀~ ADDR₁By the CI
The address of M is specified. For example, if the address of the CIM is "10"
Address data ADDR.₀= 0,
ADDR₁= 1, ADDR_Two= 0, ADDR_Three= 1, and
And input 2⁰~ 2^ThreeSo that (1010) is entered in
I just need. In this embodiment, data "0" is not
And data "1" is the power supply voltage V_ccRepresented by
Input for address "10".⁰, 2^TwoConnect
Ground, input 2¹, 2^ThreeTo the power supply. By the way, in this embodiment, the address input
2⁰~ 2^ThreeIs also input to the address decoder 306, and the
The direction of the I / O buffer 105 is controlled by the output.
It has become. As a result, if you specify an address,
Which of the 14 terminals of the I / O buffer 105
It is determined whether it will be a data output port. In this embodiment, the address is
It corresponds to the number of output ports as it is. Follow
Now, if the address is defined as "10", the I / O
10 out of the 14 terminals of the
Control is performed so that the remaining four ports become input ports. Although not shown in FIG. 6, this ad
The output of the address decoder 306 is the sequence of the control circuit 101.
Also provided to the decoder 304, which in FIG.
As described, the operation mode of this CIM is switched.
It has become so. That is, in this embodiment,
CIM with address set to “0” is in MPU mode,
CIM with the address set between “1” and “D” is DIM
In IO mode and address is either "E" or "F"
The CIMs set in the mode operate in AD mode
To be. Next, the control circuit 101 and the synchronous circuit 102
The function will be described. In this embodiment, FIG.
As already explained, the start-stop synchronization method is adopted.
As a result, both received and transmitted frames
Before transmission, 25-bit "0" must be
Inserted, and then as one start bit
“1” data is inserted (FIG. 8). Therefore, the synchronization circuit 301 determines the maximum value of the received frame.
Start bit following the first existing 25-bit "0"
Of the internal clock is synchronized.
Therefore, until the next received frame appears,
Operated by internal clock bit-synchronized with the timing of
Will be carried out. The counter 302 is synchronized
Two-phase clock from the internal clock synchronized on
Hook φ_SAnd φ_MTo produce This makes the clock φ_SAnd φ_M
Is phase-synchronized with the received data RXD
It will be. The sequence counter 303 is a synchronous circuit 30
2 indicates the start bit rising detection timing
Receiving the signal, the specific count value, for example, the state of count 0
State, and then the clock φ_SOr φ_MBy
Be counted. Therefore, the output of the count
The control procedure for the entire M can be determined, and the count
Operation of the CIM at an arbitrary timing
Can be found in which step is. Therefore, the counter 303
To the sequence decoder 304, and the CIM
Control signals required for operation, for example, RXMODO, TXM
ODE, READ, SHIFT, etc.
All control signals are generated by the sequence decoder 304
Like that. In other words, this embodiment uses the clock
φ_S, Φ_MIs a sequence control method by
Yes, therefore, decoding the output of counter 303
Then, all necessary controls can be performed. Next, the transmitted data RXD is
Whether it is data for CIM, that is, from CCU
The challenge by transmitting the received frame is to itself
The operation for determining whether or not is the case will be described. Already explained
As described above, one input of the comparator 307 has an input
2⁰~ 2^ThreeAddress data from the
Of the shift register 104₂₀Bit to Q
_{twenty three}Up to bits of data are provided. The comparator 307 has both
MYADD only when the input data of
Output R. Therefore, the received data is stored in the shift register 104.
RXD is input and its Q₂₀Bit to Q_{twenty three}bit
Up to the address prefixed to the data RXD
At the time the data (see Fig. 7) is stored.
The output signal MYADDR of the data 307 is checked.
If this signal MYADDR is "1", the data
The RXD is for you and the call from the CCU is
It turns out that it is for minutes. For this reason, the error detection circuit 308
No. COMPMODE is supplied and the specified timing
Captures the signal MYADDR and turns it to “0”.
INITIAL is generated when the
Sets the sequence counter 303 to count 0
Then, the operation of the entire CIM is restored and the next data transmission is entered.
Prepare to be empowered. On the other hand, when the signal MYADDR becomes "1"
The INITI is detected by the error detection circuit 308.
Since there is no occurrence of AL, the operation of CIM
According to the count value of the current counter 303 at that time.
And continue as it is. Next, the transmission error detecting operation will be described.
You. In this embodiment, as described with reference to FIG.
Data transmission by the continuous transmission method is adopted.
Transmission errors can be detected. For this reason, the shift register 104
First Q of₀Bit and last Q_{twenty four}Excle from a bit
The data is supplied to the ship OR gate 311 and this gate
311 is output as signal ERROR (bar superscript).
To the error detection circuit 308. The sequence decoder 304 has a start
RXD and RXD (bar superscript) following the packet (Fig. 8)
During the transmission period, the control signal RXMODE is output to output the composite signal.
The lower gate of the gate 310 is opened, whereby the transmission line 2 is opened.
Shift register using data from 0 as serial signal SI
Input to the data 104. At this time, the composite gate 310
Is supplied from the transmission line 20 because the
Incoming data is inverted and input to the shift register 104
Is done. Therefore, the start frame of the received frame (FIG. 8) is
The 24-bit data following the bit is stored in the shift register 10.
4 is input to the shift register 104
Q₀Bit to Q_{twenty three}Received signal RX
D inverted data RXD (bar superscript) is written
Become. Next, as is apparent from FIG.
After the received signal RXD is transmitted,
The 24-bit inverted signal RXD (with bar superimposed) is transmitted
When it comes, it is inverted by the composite gate 310 and the data
RXD, shift register as serial signal SI
Input to 104 is started. As a result, Q of shift register 104₀To
The first bit of the inverted signal RXD (with superscript bar) is inverted
At the input timing, the reception
The inverted data of the first bit of the transmission signal RXD is the shift register.
Q of data 104_{twenty four}Bit 2 of the inverted signal RXD
The data of the first bit is Q₀At the timing written to
The data of the second bit of the reception signal RXD is Q_{twenty four}Bit
In the end, the inverted signal RXD is shifted.
Serially written to the register 104 one bit at a time.
At each bit timing, the shift register 1
04 Q_{twenty four}Bit and Q₀The bits are opposite to the received signal RXD.
Data of the same bit of the inverted signal RXD (superscript bar) is always
It will be written correspondingly. By the way, as described above, the exclusive
The shift register is connected to the two inputs of the Shiv OR gate 311.
Q of data 104₀Bit and Q_{twenty four}Bit data is input
ing. Therefore, the reception signal RXD and the inverted signal RXD (bar
-If no error occurred during transmission of (Superscript)
During transmission of the inverted signal RXD
The output of the exclusive OR gate 311 is always "1"
It should be. Because the received signal RXD and its inverted signal
The corresponding bit of RXD (bar superscript) must be "1"
And “0” should be inverted, and as a result, the gate 3
Input of 11 always indicates mismatch, otherwise it is transmission
This is because only when there is an error in. Therefore, the error detection circuit 308 outputs the inverted signal
24-bit period during which RXD (bar superscript) is transmitted
During, monitor the signal ERROR (bar superscript),
Generates a signal INITIAL when it reaches “0” level
Then, an error detection operation can be obtained. Note that such a data transmission system is
Transmission error detection method detects transmission errors
And then repair it to get the right data
In this embodiment, transmission errors are detected.
When it is issued, the data reception operation of that frame is
Method to cancel and prepare for receiving data of the next frame
Thus, the configuration is simplified. Next, in the DIO mode of the embodiment of FIG.
The overall operation of data transmission in FIG.
This will be explained by the chart. φ_M, Φ_SIs the counter 302
The two-phase clock output to the synchronization circuit 301
Based on the internal clock generated by the
Have been generated. On the other hand, RESET (with bar)
Signals supplied to the CIM
2 is the same as the reset signal of the
Is supplied for every CIM in the system.
External reset circuit when necessary, such as when power is turned on.
To initialize the entire transmission system.
U. When initialization is completed, a sequence count
The counter 303 sets the count value to 0, and
Φ_MBy step by step. And the count value becomes 25
The IDLE signal and RXENA signal
And the CIM enters the idle state and
The sequential control based on the count value of the
Is stopped, and the tri-state buffer 313 opens to receive a signal.
It will be in a reliable state. At this time, after initialization, the
Until the count value of the cans counter 303 reaches 25
The reason that the signal is not receivable is the synchronization
This is for start-stop synchronization by the circuit 301, and the reception signal RX
Since D is 24 bits, a minimum 25-bit “0” period
Because it is necessary to give. When entering the idle state, the sequence
The counter 302 has a clock φ_S, Φ_MStep by count
While the sequence decoder 304 outputs the control signal I
DLE and INITIAL remain generated and received
It is in a state of simply waiting for a signal to be input. What
For this purpose, as shown in FIG.
25-bit “0” is added at the beginning of the frame
It is. In this way, the system enters the idle state,
Well, time t₀It is assumed that the received signal RXD is input at. So
Then, a one-bit star is placed at the head of this signal RXD.
Tobit is attached. So this start bit
Is detected by the synchronization circuit 301, and bit synchronization of the internal clock is performed.
I take the. Therefore, after that, the transmission operation for one frame is performed.
Data RXD, RXD (bar superscript) and
Lock φ_MAnd φ_SSynchronization with the internal clock depends on the stability of the internal clock.
The start-stop synchronization function is obtained. Sequence when a start bit is detected
The counter 303 has a count output of 0 (hereinafter, this counter
The output data of 303 is denoted by S, for example, in this case,
(Represented by S0).
The decoder 304 stops the control signal IDLE and outputs the control signal RXM
ODE is generated. Also, in parallel with this,
The shift pulse SHIFT is supplied to the_MTo
Supplied synchronously. As a result, the 48 bits following the start bit
Signal RXD and inverted signal RXD (bar superscript)
8) Syria from transmission line 20 through composite gate 310
1 bit in the shift register 104 sequentially
It is written while shifting. At this time, the first 24-bit reception signal R
XD is the data R inverted by the composite gate 310.
XD (bar superscript) is sequentially stored in the shift register 104.
Since it is written in real, 24 bits following the start bit
Period, that is, whether the sequence counter 303 is S1 or not.
At the point when the shift register 105 reaches S24,
₀Bit to Q_{twenty three}RXD is inverted for bits up to
Data RXD (with bar superimposed) will be written.
You. Here, the clock φ of the next S25_MRising
Outputs the control signal COMPMODE (with bar above),
The error detection circuit 308 functions. And continue in this state
Input of the inverted signal RXD (with superscript bar)
As a result, this time, the inversion signal RXD (bar superscript) was inverted.
The data RXD is equal to the Q of the shift register 105.₀From a bit
It is written in serial. As a result, the shift register is shifted from S1 to S24.
Data RXD (bar superscript) written to the data 104
From the first bit to Q of shift register 104_{twenty four}Bit position
And the sequence counter 303 determines from S25 to S4
Overflows one bit at a time until it reaches 8.
It is being done. On the other hand, in parallel with this, the shift register 10
Q of 4_{twenty four}Invert signal RXD through bit position (bar superscript
RXD) in sequence from the first bit.
It is written in real time, during this time exclusive
Transmission error by the gate 311 and the error detection circuit 308
Detection is performed as described above. Accordingly, the sequence counter 303 determines that S4
At the time when the value of the shift register 104 becomes₀Bit
To Q_{twenty three}Up to the bit, the same data as the received signal RXD
Data RXD is written as it is. Therefore, at the timing of S48, the
By examining the output signal MYADDR of the
The above-mentioned address is confirmed, and the data
Data RXD is for itself,
Whether or not the call from the CCU is addressed to you
Is determined. It is to be noted that the sequence counter 303 determines in S25
A transmission error is detected during a period between
Or, if an address mismatch is detected, an error detection circuit
308 is a control signal INITIAL when S48 is reached.
At this point, the sequence counter 303
Is returned to the state of 25 bits before idle,
All receiving operations for received frames are canceled,
Prepare for the next signal input. By the way, the sequence counter 303 determines in S25
No transmission error is detected during the period from
When no mismatch of the dress is detected, that is, S48
When the error detection circuit 308 becomes INITIAL,
When no signal is generated, when S48 is reached
At this point, the sequence decoder 304 outputs the control signal WRITES.
Generate TB. As a result, at the time of S48, INI
Either the TIAL signal or the WRITESTB signal
Occurs, and both transmission errors and address mismatches occur.
If not, the former, and transmission errors and
If one of the two
Each will be output. Now, at the time of S48, the control signal WRITE
When STB is output, the shift register 10 at that time is output.
4 data is written to the I / O buffer 105 in parallel.
As a result, depending on the received data RXD,
The received data is output to the output port of the I / O buffer 105.
From the external load 51 to any one of the external loads 51 to 56. In this case, the operation is performed in the DIO mode.
Therefore, as described with reference to FIG.₆Bit
To Q₁₉Up to 14 bits are the data RXD
And how many of the bits are I
Whether the output port of the / O buffer 105 is
As already explained,
It is. When the processing reaches S48, the reception frame
All the processing is completed, and the next S49 starts to process the transmission frame.
(Fig. 8). First, what processing is performed from S49 to S72
Also do not. This is the start-stop synchronization of the CIM on the CCU side
IDL in the processing of the received frame described above.
For the same purpose as the operation during the period set before E
It is. In S73, the sequence decoder 304
Outputs a control signal PS.
The data 104 is a parallel data reading operation, and the I / O
External loads 51-56 are connected to the input port of the buffer 105.
Input the data given in parallel. The number of bits of the data read at this time is
Out of the ports of the 14-bit I / O buffer 105,
The bits used as output ports in the processing of
This is the number of remaining bits subtracted. For example, as mentioned above,
When this CIM address is set to 10, output
Since the number of ports is 10, the input ports
The number of bits is 4 bits. The parallel data for the shift register 104
The data is written in the shift clock SH together with the signal PS.
Since one bit of IFT is required, the clock of S73 is used.
φ_SAfter the signal SP is started by the clock of S74,
φ_SThe shift pulse SHIFT synchronized with the control signal TX
Supplied before the rise of MODE. At this time, as is apparent from FIG.
, A start bit is added before the transmission data TXD,
Further, an address is added to the first 4 bits of data TXD
Must. Therefore, it is omitted in FIG.
Is a shift register only while the signal PS is being generated.
104 Q_{twenty four}A signal representing data "1" is in the bit,
And Q₂₀Bit to Q_{twenty three}Input 2 in the bit part⁰~
2^ThreeAddress data is supplied from
I have. Thus, the DUMM from S49 to S73
25-bit data required for start-stop synchronization depending on the Y state
After the “0” transmission period is set, the control is performed when entering S74.
The signal TXMODE rises, which causes a TX (transmit) state.
Be in a state. The generation of this signal TXMODE causes the composite
The upper AND gate of the gate 310 is activated, and
The AND gate 312 is activated. Shift by this
Q of register 104_{twenty four}Bit data, start
Bit data “1” passes through the AND gate 312.
And sent out to the transmission line 20. Then, the subsequent clocks after S75
φ_MShift clock SHIFT generated in synchronization with
The contents of the shift register 104 are shifted one bit at a time.
Q_{twenty four}From bit through AND gate 312
It is sent out to the transmission line 20, and the transmission frame (FIG.
8) Transmission of the transmission signal TXD including the start bit is performed.
Be done. On the other hand, the shift register 104
In parallel with the data reading,_{twenty three}Is it a cell of bits
The data read out is inverted through composite gate 310.
Supplied to the serial input of the shift register 104
I have. As a result, after S75, the shift register 104
Q₀Bit to Q_{twenty three}The transmission data written up to the bit
TXD is one bit by the shift clock SHIFT.
Are sent out to the transmission line 20 one by one,
Q of shift register 104 as serial data SI₀
The data is sequentially written from the bit. Therefore, the period during which the control signal PS is generated
Inside of the shift register 104 Q₀Bit to Q_{twenty three}bit
All the transmission data TXD written in the cells of
At the time of this₀Bit to Q_{twenty three}Bit of cells
Is the inverted data T instead of the previous transmission data TXD.
XD (bar superscript) is stored. Therefore, the reading of the transmission data TXD is
After the completion, the shift
Read inverted data TXD (with bar superimposed) from register 104
Starts, and the inverted data TXD (bar superscript)
Is transmitted to the transmission line 20 following the transmission data TXD.
Will be. When the process reaches S122, the shift register
Q of data 104_{twenty three}Bit to Q₀Inverted data up to bit
Is completed, the control signal TXMODE falls.
Transmission of the shift clock SHIFT is also stopped.
End the state. Then, the clock φ that follows S122
_MGenerates the control signal INITIDL, and the sequence
Counter 303 is set to S0 and CIM is idle
(IDLE) Return to the previous signal reception preparation state. Therefore, according to this embodiment, start-stop synchronization,
Half-duplex multiplex communication using bidirectional, inverted double transmission
To ensure the connection between CCU and CLU, the LCU side
CIM with DIO mode operation function required by
Can be obtained. Next, the AD mode of the CIM according to this embodiment will be described.
The operation in the mode will be described. As mentioned above, C
Electrical equipment to exchange data with CCU via IM
The device is not capable of outputting analog signals such as various sensors.
Part loads 57 and 58 (FIG. 2).
The embodiment includes an A / D control circuit 106,
Also has the function of controlling the A / D 40
I have. Then, the operation mode of the CIM at this time is the AD mode.
Mode. And, as already explained,
In the embodiment, input 2⁰~ 2^ThreeAddress data to be given to
Therefore, the operation mode has been set.
The address data corresponding to the AD mode is shown in FIG.
Thus, "E" and "F" are shown. Therefore, the CIM according to this embodiment is
When set to “E” or “F”, the function block
The locked state is as shown in FIG. And like this
The data stored in the shift register 104 when set
The contents of the data are as shown in Fig. 7 and are from No. 0 to No. 7.
8 bits via the A / D 40 are connected to external loads 57 and 58
No. 8 and No. 9 for storing AD data imported from
Two bits are for storing AD channel data.
No. 10 to No. 19 for DIO data
Bit. Others are in DIO mode.
Same as when. The AD channel data at this time is
Is the channel when using multi-channel AD.
This is the data for designating the A / D 40 in this embodiment.
2 bits
Is assigned. FIG. 11 shows the embodiment of FIG. 10 in more detail.
FIG. 11 is a block diagram showing the details.
Is a shift register, 312 is a register, 322 is a game register.
, 323 is an A / D control counter, and 324 is an A / D control counter.
Control signal generation circuit, 325 is for A / D channel selection
It is a counter of. Others are described in the case of FIG.
It is the same as the place. The shift register 320 has 8 bits.
Then, take in serially from external A / D40 and
Data (external load 57, 58, etc.)
A / D conversion of analog data)
Readout and A / D40 channel
2 bits provided from the counter 325 for designating
Receive the channel selection data of
It functions to read out serially and supply it to the A / D 40. The register 321 is a 32-bit register.
/ D40 is 8 bits and 4 channels.
Use as 8-bit 4-channel register
Data taken from A / D40 in 8 bits
Is stored for each channel. The gate 322 also corresponds to the register 321.
32 bits (8 bits, 4 channels)
Q of shift register 104 for data transmission₈Bit and Q₉
AD channel data read from bit cell
7) is controlled by the channel of the register 321.
Select one, and shift the 8-bit data to the shift register
Q₀Bit to Q₇AD data (Fig. 7)
It works as writing. The counter 323 has a clock φ_MCount
And the entire operation of the A / D control circuit 106 is
It acts as a control that is both official and cyclic.
You. The A / D control signal generation circuit 324 includes a counter 323
Including a decoder and a logic circuit for decoding the output of
Various control signals necessary for the operation of the entire D control circuit 106
It works to happen. Next, the operation of the entire A / D control circuit 106 will be described.
The work will be described. In this embodiment, the counter 323
Sequentially corresponding to each of the count outputs
The control proceeds, the number of steps is 27, and the count output is 0.
(This is called S0) and the count output 26 (this is S0)
6), one cycle of control is completed, and A / D4
Data of one channel of 0 is taken into register 321
It is. First, when the control of one cycle starts, the signal
Signal INC causes a channel selection counter 325 to
This causes the output data of the counter 325 to be decremented.
The data is (0,0) → (0,0,
1) → (1,0) → (1,1) → (0,0)
You. The output data of this counter 325 is shifted
Register 320 is written in parallel to the first two bit positions
And then read out as serial data ADSI
/ D40. In parallel with this,
The output data of the data 325 passes through a decoder (not shown).
Is also supplied to the register 32,
8 bits of the channel to be selected. Subsequently, A / D 40 is the serial data AD
It depends on the channel selection data input as SI
Select the analog input channel corresponding to the
8 bits after converting log data to digital data
Shift register 320 as serial data ADSO of
Of the shift register 320.
Store. Thereafter, the data is stored in shift register 320.
The converted 8-bit digitally converted data AD is
The data is read out in parallel at a predetermined timing,
Register 3 previously selected by the output data of
Transferred to 8 bits of 21 predetermined channels,
The control operation of the controller ends. Thus, for example, the output data of the counter 325
If the data is (0,0), the A / D40
Channel 0 analog data is digitized and
The data stored in the 8 bits of channel 0 of the
, The counter 323 is reset to S0 and the next cycle
The counter 325 is incremented.
The output data is (0,1), this time the channel
The analog data of register 1 is digitized and
21 bits of channel 1 are accommodated in 8 bits. Therefore, according to this embodiment, the A / D control
The operation of fetching data from the A / D 40 by the circuit 106 is as follows.
Sequence counter 303 and sequence decoder 304
Performed independently of data transmission process by timing
The data of each channel of the register 321 is 4 cycles.
Is refreshed once per AD control operation of the
Input to four channels of A / D40 in the register 321
Analog data is stored for each channel.
And always prepared as 8-bit digital data
Will be. Therefore, the reception signal RXD is now transmitted from the transmission path.
Is input, and the address data attached to
Assume that it was for CIM. In this case,
As described above, the address data is “E” or
"F". Then, the input of the received frame is completed.
At the time (S48 in FIG. 9), the data is written into the shift register 104.
The data format used is the AD mode shown in FIG.
Therefore, the Q of the shift register 104₈Bit and Q₉
The AD channel data consisting of 2 bits is stored in the bit.
Has been delivered. Therefore, this AD channel data is
Read when signal WRITESTB occurs at 48
Which allows the gate 322
Is selected. As a result, the signals PS and S are output in S73 (FIG. 9).
At the time when HIFT occurs, the four
Of the channels, Q of shift register 104₈, Q₉2
Only the AD data of the channel selected by
And it is the Q of shift register 104₀From a bit
Q₇Written to the 8-bit part up to the bit. And
This is included in the transmission signal TXD in the transmission state after S74.
And transmitted to the CCU. In this embodiment, as described above,
The reception processing of the reception signal RXD and the transmission signal T
Regardless of the XD transmission processing, it is always stored in the register 321.
Is provided with AD data. Therefore, this embodiment
Then, at what timing,
Even if D appears, the transmission signal TX by AD data immediately
D can be transmitted, and the operation of A / D 40
A / D conversion operation without affecting transmission processing
There is no danger that the transmission speed will decrease due to the necessary time.
No. In this embodiment, the CIM is implemented as an LSI.
A / D40 is external and CIM is used for general purpose
In this case, the cost is reduced. Toes
Therefore, as described with reference to FIG.
One type of CIM is set by the CIM of LCU30-31
As the CIM of the LCU 32 or the CCU
It can be used as 10 CIMs 33. However, at this time, the A / D
When used as CIM 30, 31, 33
It is wasteful and, in general, the centralized wiring
When applied to the stem, it is used as CIM32.
Use as the other CIM30,31,33
A / D is included in all CIMs
There is not much merit by storing. for that reason,
The A / D is external. However, since this A / D is external,
As is clear from 11, for the external A / D40
Four connection terminals are required, and the terminal
This may increase the number of components. Then, one of the present invention
In the embodiment, when the CIM is set to the AD mode,
Is four of the 14 ports of the I / O buffer 105
Is switched as a connection terminal for the A / D 40.
It is. That is, in the embodiment of the present invention, the I / O bus
The buffer 105 has 14 ports, which are shown in FIG.
As can be seen, the CIM is set to DIO mode
May be used as input / output ports
However, there are at most 10 ports in AD mode.
No. 4 ports No. 11 to No. 14 shown in FIG.
Is not used for input / output of DIO data
You. Therefore, the remaining four ports are set in the AD mode.
To switch and use it as a terminal pin for A / D40.
For example, even if the A / D is externally connected, the number of terminal pins does not increase.
Increased versatility when implementing LSI, enabling cost reduction
Become. Next, the MPU module of the CIM according to this embodiment will be described.
The operation in the mode will be described. Clear from FIG.
Thus, the CIM according to this embodiment is switched to the MPU mode.
To change the address, the address ADDR₀~ ADDR_ThreeTo
Address set to “0”, that is, input 2⁰~ 2^ThreeAll
It may be maintained at the ground potential and set to (0000). This MPU mode is the CIM shown in FIG.
33 to provide the necessary functions when used as
Mode, used in DIO mode and AD mode
Unlike the case, data is given to the microcomputer of CCU10.
When it is received, it is transferred to the CIM 30-31 of the predetermined LCU.
Sent for any of them and returned accordingly
After receiving the data, transfer the data to the microcomputer.
To perform the transmission interface operation.
You. Incidentally, in the description so far, FIG.
As explained above, the explanation from the viewpoint of CIM on the LCU side
Was mainly used, so CIM on the CCU side
A frame that transmits data to the CIM is a received frame,
On the other hand, a frame transmitted from the LCU to the CCU
I've made it a frame, but from the point of view of each CIM
The frame that sends data is the transmission frame, and the data
The frame when the data is accepted by the
I will tell. Therefore, after that, a certain CIM, for example, CI
The transmission frame in M33 is another CIM, for example, CIM3.
0 indicates a received frame, while transmission on the CIM 30
The frame is a received frame in the CIM 33. FIG. 12 shows the CI according to the embodiment of the present invention.
Address “0” is set in M, and the CPU operates in the CPU mode.
Is a rough functional block diagram when it is controlled to
3 shows a state of the CIM 33 in FIG. As described above, in this embodiment,
Indicates that three CIMs with the same configuration
Mode, that is, CPU mode, DIO mode, AD mode
It can fulfill the function in any state of
Therefore, the state shown in FIG. 12 corresponds to the state in the CPU mode.
The CIM according to this embodiment represents a functional block.
It shows that the configuration is different from that of FIG.
Not. As is apparent from FIG.
The I / O buffer 105 (FIG. 3) and the A / D 40
Function stopped, 14-bit data between microcomputer
It is tied by bus. Note that the terminal pins at this time are
Shared with the input / output port of the
Needless to say, there is no increase or decrease in
Nor. And the input / output of these 14 bits (14)
8 bits are for data and the remaining 6 bits are for control signals.
No. Now, in this CPU mode, the shift
As shown in FIG.
₀To Q_{twenty three}All 24 bits up to become MPU data
The microcomputer uses an 8-bit data bus to
The shift register 104 is accessed.
You. On the other hand, the control circuit 101 controls the microcomputer.
Receiving the control signal,₀~ Q_{twenty three}All of
When the data from the microcomputer is stored in all the bits,
At the time t when this data is stored.
_xStarts transmission of a transmission frame as shown in FIG.
I do. Thus, the transmission frame is transmitted from the CIM 33.
When sent, the CIMs 30-32 on the LCU side
One responds and then the CIM sends
Time t_xFrom one frame (148 bits) transmission time
Time t has elapsed_x, The shift register 104
Some CIM (CI
M30-32) is the case.
Will be delivered. The control circuit 101 of the CIM 33
At this time t_yIssues an interrupt request IRQ (with bar above)
And the microcomputer responds accordingly to the shift register 104
Read data and end data transfer for one cycle
You. In this case, data transfer between CIMs
The operation is performed in the DII mode described with reference to FIG.
It goes without saying that it is the same as the case. FIG. 14 shows the CIM 33, that is, the MPU.
Function showing one embodiment of CIM when set to mode
Functions required in MPU mode in the block diagram
Only corresponding blocks are shown.
400 and 402 are 8-bit switches, and 404 is an 8-bit switch.
The other is the same as the embodiment of FIG.
The same. In this MPU mode, shift register 1
04 Q₀Bit to Q_{twenty three}8-bit input / output up to bit
Connected to the microcomputer's data bus via
Data is sent to and received from
Q of shift register 104₀~ Q_{twenty three}Bits of three groups
Loop, Q₀~ Q₇(Reg3), Q₈~ Q_Fifteen(Reg
2), Q₁₆~ Q_{twenty three}(Reg1)
No, they are accessed sequentially in a time-division manner. Therefore, for this reason, the 8-bit switch 4
Register given from microcomputer using 00 and 402
Switch 4 according to the combination of select signals RS0 and RS1
00 and the control signal of the switch 402.
Control signals STB1-3, and input / output terminal pins 7-14
Connect to Reg1, Reg2, and Reg3 sequentially
And the microcomputer is accessed three times by 8 bits
Transfer of data between the shift register 104 and the
It has become. Then, in this case, the shift
When writing data to the register 104, the microcomputer
Data read time from the shift register 104
To compensate for the difference between the
Switch 404 is provided to temporarily store data from the microcomputer.
After writing, write. In the MPU mode, data reception
Address at the beginning of 24-bit data
Is not performed in the CIM 33. Follow
And input 2⁰~ 2^ThreeThe address (0000) given to
The address decoder 306 sets this CPU mode to MPU mode.
Used only to configure IM and
The parator 307 is not operated. Next, in the MPU mode, the CIM 33
Input / output terminal pins 1 to 6
It is a transmission path, which allows the microcomputer to send CIM
Clock E and chip select
Signal CS (with bar), read / write signal RW, and
Given the above register select signals RS0 and RS1,
On the other hand, an interrupt request signal IRQ (bar
(Superscript) is output to the microcomputer. FIGS. 15 and 16 show processing circuits for these signals.
In one embodiment, which is omitted in FIG.
01, first, the clock E is
And processed together with the internal clock CLOCK
As a result, two-phase clocks EH and EL are generated. Soshi
And these clocks EH and EL and signals from the microcomputer
RW, CS (with bar above), RS0, RS1 are the times of FIG.
Signal STB0-3 and RESD0-1
Be born. In addition, the signal MPU sets the CIM to the MPU mode.
This signal becomes "1" when set. Further, the signal processing by the circuit of FIG.
FIGS. 17 and 18 show the timing.
FIG. 17 shows the generation timings of the signals READ0 to READ3.
FIG. 18 shows the generation timing of the signals STB0 to STB3.
Are respectively shown. In these figures, signal RED0
To 3 occur and the signals STB0 to STB0
3 is determined by whether signals RS0 and RS1
The combination is determined by the
Group Reg1, Reg2 of shift register 104
Reg3 is selected. By the way, these signals READ0 to READ3,
The signals READ0 and STB0 of STB0 to STB3 are
Used for group selection of shift register 104
However, an interrupt request signal IRQ (bar superscript) described later is issued.
Used raw. Therefore, selection by signals RS0 and RS1 is performed.
FIG. 19 shows the selected state. Next, FIG. 20 shows an interrupt request signal IRQ (bar
FIG. 14 shows an embodiment of the generation circuit of FIG.
The CIM 33 is included in the circuit 101 and receives data.
When completed, store received data in shift register 104
WRITE STB (FIG. 9)
And the time when the signal IRQ is generated by the signal READ0.
And the input / output terminal pins 7-14.
One of the data lines D0 to D7 connected to the tabus
One, for example, the signal DATA from the data line D0 and the signal S
And a circuit for generating a signal MASK1 from TB0.
The operation is shown in the timing charts of FIGS.
It is shown. FIG. 18 shows a signal among these figures.
DATA becomes "0" at the generation timing of STB0.
FIG. 19 shows the operation when the signal DATA is "1".
It shows the operation when the state is changed to.
In the circuit of FIG. 20, the signals DATA and STB0 are supplied.
The flip-flop set is called Reg0. Follow
Therefore, in the circuit of FIG. 20, "1" is written in Reg0.
The interrupt request signal IRQ (bar superscript)
Will be hung. Next, the embodiment shown in FIG.
CIM is set to MPU mode
The overall operation of data transmission in the timing of FIG.
This will be described with reference to a chart. In the embodiment of the present invention, the CIM 30
The operation of each of the sequence counters 303 is
Controlled by the count output of
When the count output of the counter 303 is set to a predetermined value,
If it can be transposed to any operating state
Is as described in connection with FIGS.
This means that whatever mode the CIM is set to
There is no change. By the way, as shown in FIG.
CIM33 set to the password is combined to transmit data.
As shown in FIG.
Or CIM30-32 set to AD mode.
ing. And this CIM is in DIO mode and A
When it was set to D mode, it was explained in FIG.
When data from another CIM is received,
Continue to transmit its own data for one frame
Data transfer operation, so to speak, a passive operation.
Only work is done. On the other hand, MPU like CIM33
If the mode is set to
When the data is written to the shift register 104,
It requires an active action to start communication, so to speak. So
In this embodiment, the active data transmission starts
For the group selection of the shift register 104
Use the signal STB3 among the signals STB1 to 3
I have to. This corresponds to the mask for the shift register 104.
Writing of transmission data by icons is Reg1, Reg
2 and Reg3 in this order, so that the signal STB3
When the error occurs, the microcomputer
Writing of the data to the shift register 1 is completed.
04 stores all data to be transmitted this time.
is there. Then, returning to FIG. 23, at a certain point in time,
The microcomputer of CCU10 (Fig. 2)
It is assumed that data to be transmitted is prepared. Do so
And this microcomputer sends signals via input / output terminal pins 1 to 6.
CS (with bar above), RW, RS0, RS1 are CIM33
To the control circuit 101 in FIG.
Signals STB0 to STB3 are generated as described (FIG. 23, left).
8 bits of data sequentially from the data bus
To Reg1, Reg2, Reg of the shift register 104
Write in 3. On the other hand, the control circuit 101 outputs the signal STB
3, the sequence counter 303 stores “4”.
9 "is loaded. Sequence by this signal STB3
Time for setting the output data of the counter 303 to “49”
FIG. 24 shows an embodiment of the circuit, and FIG.
FIG. 25 shows the operating chart. Thus, the sequence counter 303 sets S4
9, the time t_x(Figure 13)
Processing is started. Transmission from S49 to S122
Frame processing is in the case of DIO mode described in FIG.
This is almost the same as the shift register in this MPU mode.
The data to be transmitted is already written in the star 104
From S49 to S73, do nothing, just shift
Q of register 104_{twenty four}"1" for the start bit
It is different from DIO mode only in writing.
It is. When the processing reaches S122, the signal INIT is output.
IAL occurs, and then the minimum time from S0 to S24
Enter idle state including pause. In other words, in MPU mode
Is different from the DIO mode,
Instead of waiting for the data to be received,
When writing of data to the
Data 49 is forcibly loaded into the
This will automatically start sending frames
-ing Thus, transmission from CIM 33 of CCU 10
When the transmission of the frame starts, as described with reference to FIG.
The transmission data TXD is transmitted to the CIMs 30 to 3 on the LCU side.
2 is received as reception data RXD,
Return data by CIM whose address matches
Data is transmitted, this time it is the received data RX
D is received by the CIM 33. The processing of the received frame at this time is also shown in FIG.
MPU mode is almost the same as DIO mode in
The only difference is that the address
It is. Then, from S0 to S48, the shift register
Data has been stored in the
If not detected, the clock φS of S48
When the signal WRITE STB rises, this causes
0 to the interrupt request signal IRQ (bar) as described in FIG.
-Superscript) occurs, and the signal is generated by the subsequent clock φM.
INITIAL occurs and this CIM 33 is idle
State and idle until the next signal STB3 is generated.
Keep state. In this manner, the interrupt request signal IRQ (with a bar above)
Is generated, the microcomputer in the CCU 10 receives this signal I
Jump to interrupt processing routine by RQ (bar superscript)
And fetches the received data from the shift register 104.
Now. At this time, the data from the shift register 104
For the capture, a switch 400 is used, as shown in FIGS.
The signals READ1 to 3 are sequentially supplied from the circuit described in step 16.
Shift shift via 8-bit data buses D0-D7.
Row of Reg1, Reg2, Reg3 of the register 104
What is done is as already explained.
You. By the way, in this embodiment, FIG.
As described, this signal IRQ (bar superscript)
The CCU10 microcomputer is configured to
By writing “1” to g0 (FIG. 20),
The signal IRQ (bar superscript) can be masked. Therefore, as shown in FIG.
Time of occurrence t_xAt the point of time when the signal STB0 occurs (see FIG.
Set the data bus D0 to “1” according to (lower left)
For example, the signal MASK becomes “1”, and then the signal WRI
Even when TESTB is generated, the interrupt request signal IRQ
(Bar superscript) is not supplied to the microcomputer,
The computer gives priority to other processing during the prescribed period as necessary.
Can do it. The release of the mask is performed as shown in FIG.
As is apparent from 0, data is generated at the time of occurrence of signal STB0.
If the bus D0 is set to “0” and “0” is written to Reg0,
Good. On the other hand, the microcomputer of the CCU 10
When performing IRQ (bar superscript) mask,
The signal IRQ shown in FIG. 20 was checked, and it was "1".
Data reception has been completed.
The data is taken in from the master 104, and it is set to "0".
If so, wait for the data reception to be completed. The signal I
RQ (bar superscript) occurs when data is taken in
From the signal READ0 that is released from FIG.
it is obvious. Therefore, according to this embodiment, the CCU
After transferring the data to CIM33,
Useless waiting time because other processing operations can be started
System that makes full use of its processing capacity by eliminating the need for
And at this time, the data of CIM 33
Data reception is completed, but other processes with higher priority
The mask can be activated for movement,
There is no danger that processing operations with higher priority will be interrupted
I can do it. [0155] Here, as shown in FIG.
CIM33 and DIO mode (or AD mode)
Data transmission by combination with specified CIMs 30-32
FIG. 26 shows the transmission operation in a state transition diagram. [0156] 【The invention's effect】According to the present invention, the register and the I / O
Are clearly limited, and as a result,
It is not only easy to make chips
After storing data in a register, I / O buffer
Transfer the data to the external loader
During this time, data can be checked as needed.
Input is possible, so that incorrect data can be
There is no danger of being output to the load,
High reliability at all times.
You can.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram showing an example of an integrated wiring system in a vehicle. FIG. 2 is a block diagram illustrating an example of a data transmission method. FIG. 3 is a schematic block diagram showing one embodiment of a communication processing circuit according to the present invention as a basic functional configuration. FIG. 4 is an explanatory diagram of operation mode switching by an address. FIG. 5 is a functional block diagram showing an embodiment of the present invention in a DIO mode. FIG. 6 is a block diagram illustrating one embodiment of the present invention in DIO mode in more detail. FIG. 7 is an explanatory diagram showing one embodiment of data contents in the present invention. FIG. 8 is an explanatory diagram showing one embodiment of a transmission waveform in the present invention. FIG. 9 is a timing chart for explaining the operation of one embodiment of the present invention in the DIO mode. FIG. 10 is a functional block diagram showing an embodiment of the present invention in an AD mode. FIG. 11 is a block diagram showing one embodiment of the present invention in the AD mode in further detail. FIG. 12 is a functional block diagram showing one embodiment of the present invention in the MPU mode. FIG. 13 is an explanatory diagram showing one embodiment of a transmission waveform in the MPU mode of the present invention. FIG. 14 is a block diagram showing an embodiment of the present invention in the MPU mode in further detail. FIG. 15 is a block diagram showing one embodiment of a signal processing circuit according to the present invention. FIG. 16 is a block diagram showing one embodiment of a signal processing circuit according to the present invention. FIG. 17 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 18 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 19 is an explanatory diagram showing a selecting operation by a register select signal in the present invention. FIG. 20 is a block diagram showing an embodiment of an interrupt request signal generation circuit according to the present invention. FIG. 21 is a timing chart for explaining the operation of an embodiment of an interrupt request signal generation circuit according to the present invention. FIG. 22 is a timing chart for explaining the operation of an embodiment of an interrupt request signal generation circuit according to the present invention. FIG. 23 is a timing chart for explaining an operation in the MPU mode in one embodiment of the present invention. FIG. 24 is a block diagram showing one embodiment of a circuit for setting a counter. FIG. 25 is a timing chart for explaining the operation of one embodiment of a circuit for setting a counter. FIG. 26 shows the CPU mode and D in one embodiment of the present invention.
FIG. 10 is a state transition diagram illustrating a data transmission operation by a combination of IO modes. DESCRIPTION OF SYMBOLS 10 Central processing unit 20 Signal transmission path 30 to 32 Terminal processing unit 33 Communication control unit 40 A / D (analog-digital converter) 51 to 58 External load 101 Control circuit 104 Shift register 105 I / O buffer 106 A / D control circuit 107 Clock generator 301 Synchronous circuit 302 Counter 303 Sequence counter 304 Sequence decoder 305 Abnormality detector 306 Address decoder 307 Comparator 308 Error detection circuit 310 Complex gate 311 Exclusive OR gate 312 AND gate 320 Shift register 321 Register 322 Gate 323 Counter 324 A / D control signal generation circuit 325 Counter

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Akira Hasegawa               Katsuta, Ibaraki Pref.               Hitachi, Ltd. Sawa Plant                (56) References JP-A-58-97997 (JP, A)                 JP-A-56-21229 (JP, A)                 JP-A-58-112170 (JP, A)                 JP-A-54-19316 (JP, A)                 JP-A-51-32242 (JP, A)                 JP-A-58-136149 (JP, A)                 JP-A-57-147392 (JP, A)                 Patent 2502491 (JP, B2)

Claims (1)

(57) [the claims] 1. A communication control computer that controls data transmission and reception between the terminal processing unit in accordance with a communication control program, is connected to the communication control computer, said end end process instrumentation
A first communication processing circuit having a register for temporarily storing transmission data and received data from location to the terminal apparatus
A central processing unit comprising: a reception data from the first communication processing circuit; and the terminal
A register for temporarily storing data indicating a state of the external load connected to the processing device ; and a register between the register and the external load.
A second communication processing circuit having an I / O buffer connected to the first communication processing circuit, and a communication line connecting the first communication processing circuit and the second communication processing circuit so as to be capable of data transmission. Automotive data transmission system. 2. 2. The communication control computer according to claim 1, wherein when the reception data from the terminal processing device is established in a register of the first communication processing circuit, the communication control computer stores the data in an attached storage device. Characteristic automotive data transmission system. 3. 2. The communication control computer according to claim 1, wherein the communication control computer transmits data to the terminal processing device in a programmed order, and the terminal processing device that has received the transmission data executes the terminal processing.
A data transmission system for a vehicle, wherein data indicating a state of an external load connected to the device is returned to the communication control computer. 4. In Claim 1, the second communication processing circuit stores its own address, compares the address of communication data with an address present on the communication line with its own address, and finds a match. only the terminal processor <br/> receives the communication data, the second communication processing circuit of the terminal apparatus which has received the communication data, the data indicating the state of an external load connected to the end end processor And transmitting the data back to the first communication processing circuit via the communication line . 5. The vehicle data transmission system according to any one of claims 1 to 4, wherein the communication data is formed as one frame in which address data is followed by transmission data and reception data. 6. Between the terminal processing unit according to the communication control program
A communication control computer for controlling data transmission and reception ;
Is connected to the communication control computer, said end end process instrumentation
Data received from the terminal and data transmitted to the terminal processing device.
Communication processing circuit having a register for temporarily storing data
A central processing unit comprising: a first communication processing circuit;
Received data and external data connected to the terminal processing device.
Equipped with a register to temporarily store data indicating the load status
A second communication processing circuit, and said first communication processing circuit and the second communication processing circuit Day was
System with a communication line connected to enable data transmission
Te, the second communication processing circuit, said second register in the communication processing circuit and the external load
An I / O buffer connected therebetween, and an address data temporarily stored in a predetermined bit of the register.
Address comparison for comparing the over data and known address data
And the register in synchronization with a clock generated at a predetermined cycle.
Latch timing of communication data to the I / O bus
Control to control the delivery timing of the communication data to the Ffa
Control circuit, wherein the register temporarily stores the encoded communication data.
Was paid, the I / O bus Ffa has a known address data
Address data temporarily stored in the register matches
When the communication data following the address data is
Automotive data transmission system characterized by being configured to take received from. 7. 7. The I / O buffer according to claim 6, wherein the I / O buffer outputs communication data stored in the register to an external load.
Bei a function of, and a function of inputting data from the external load to register
Data transmission system for automobiles
M 8. 2. The circuit according to claim 1, wherein the register and the I / O buffer are an LSI module.
It is characterized in that it is built on the same chip as the Le
Automotive data transmission system. 9. 2. The communication data according to claim 1, wherein the communication data from the register to the I / O buffer is stored.
Data writing is, this heat transmission errors and address mismatch there is no
Is configured to be executed after confirmation
Automotive data transmission system.