JPH05204849A - Synchronous serial bus system - Google Patents

Abstract

PURPOSE:To provide the synchronous serial bus system has a diagnostic mode in addition to various transmission modes. CONSTITUTION:A master station 1 and plural slave stations 2(1)-2(n) are connected by a four-wire line consisting of a clock transmission line 3A, a 1st data transmission line 3B which sends data from the master station to the slave stations, a 2nd transmission line 3C which sends data from the slave stations to the master station, and a control signal line 3D which transmits control signals; and the data are transmitted mutually between the master station 1 and slave stations 2(1)-2(n) by the 1st data transmission line 3B and 2nd transmission line 3C.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous serial bus system in which serial data is transmitted from one or a plurality of master stations to one or a plurality of slave stations and reception confirmation is output from the received slave stations. ..

[0002]

^2. Description of the Related Art As a synchronous serial bus system, a two-wire I ² C bus system (Philips), a three-line IM bus system (ITT / Inter Metallic), 4
Wire M bus system (Motorola) or 5 wire D
The MP bus system (SONY) and the like are known.

The I ² C bus system uses a clock (CL
K) and data (DATA) are bidirectionally transmitted by using two cables.

Further, in the IM bus system, a control signal (CTRL) is transmitted in order to detect a device address at the head of a command code of a plurality of bytes sent from a master station to a slave station, in addition to a clock and data. The line is added. In this IM bus system, by putting an "END" code on a control signal line for an instruction composed of a plurality of bytes, a delimiter for each instruction is clarified and a malfunction is prevented.

Further, the M bus system uses four cables, that is, a clock line, two transmission / reception data lines, and a slave select cable. M slave station connected to the bus system is accessed by the slave select signal from the master station (the slave) because the device is determined, the I ² C
Unlike the bus system and the IM bus system, it is not necessary to assign a device address.

Furthermore, the DMP bus system uses a clock line, two data lines for transmission / reception, a control line, and a multi-master control line,
It enables data transmission between multiple master stations and multiple slave stations.

[0007]

By the way, the above-mentioned I ²
Since the C bus system is a two-wire system, the hardware configuration is simple, but an identification number is assigned to each slave station connected to this I ² C bus system, and the identification number is identified. Therefore, there is a problem that a special decoder is required. In addition, since data is transmitted and received by one data line, the protocol (communication procedure) is complicated, and there is a risk of causing a hangup (a state in which a plurality of CPUs continue to stand by in a slave state) in the multi-master mode.

In the IM bus system, the probability of malfunction is reduced as described above, but it is not possible to confirm whether the talker (master station) commands are correctly interpreted by the listener (slave station), and the multi-master system is not available. There is a problem that the structure cannot be formed.

Further, although the M bus system can adopt a multi-master configuration, there is a problem in that the number of slave selects increases in proportion to the number of master stations and the wiring becomes complicated.

Furthermore, in the DMP bus system, the configuration of the interface connecting the bus and the peripheral device becomes complicated,
Further, the return data from each slave station is not sufficient for diagnosis of all peripheral devices, and there is a problem that the number of bits of the usable device is limited.

The present invention has been made in view of the above points, and various types of transmission modes, particularly a diagnostic mode, can be realized by a simple protocol, and a synchronous serial bus whose bus interface is greatly simplified. The challenge is to provide a method.

[0012]

SUMMARY OF THE INVENTION The synchronous serial bus system of the present invention, which has been made to achieve the above object, has a plurality of stations connected to each other by a 4-wire line and a plurality of 4-wire lines. A clock transmission line that transmits a clock between one master station and a plurality of slave stations, a first data transmission line that transmits data from the master station to the slave stations, and a slave station to the master. In the synchronous serial bus system connected via a second transmission line for transmitting data to the station and a control signal transmission line for transmitting a control signal, each slave station is set with a device address and the master station is , A control signal is output to the control signal transmission line, a clock is output to the clock transmission line, and serial data is transmitted to the first data transmission line. Device address and serial data of the slave station, the slave station receives the serial data in response to the control signal and the clock sent from the master station, and the slave station whose device address matches the second data Receiving data is transmitted to the master station via the transmission line, and the level of the control signal transmission line is set to a high level while the first data transmission line is at least transferring the data indicating the device address. , And the first data transmission line is at least transferring serial data from the master station to the slave station,
The second data transmission line is characterized in that the level of the control signal transmission line is set to the low level during the transfer of the return data from the slave station to the master station.

[0013]

In the synchronous serial bus system of the above construction, a clock transmission line for transmitting a clock between one master station and a plurality of slave stations, and a first line for transmitting data from the master station to the slave stations. 1 data transmission line, 2nd for transmitting data from slave station to master station
And a four-line control signal transmission line for transmitting control signals are connected to each other, and the first data transmission line and the second transmission line mutually connect between a master station and a plurality of slave stations. Data is transmitted.

At this time, the first data transmission line is
At least during the transfer of data indicating the device address, the level of the control signal transmission line is set to a high level, and the first data transmission line is at least during the transfer of serial data from the master station to the slave station, And while the second data transmission line is transferring the return data from the slave station to the master station,
The level of the control signal transmission line is set to low level.

Therefore, the access and data transmission modes are set according to the level of the control signal transmission line, and the data transmission between the master station and a plurality of slave stations can be achieved by a simple protocol. A method can be provided.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a synchronous serial bus system by a single master system which is a first embodiment of the present invention. In this synchronous serial bus system, a master station 1 and first to Nth slave stations 2 (1) ... 2 (n) are connected by four transmission lines (cables) 3A to 3D. The first to Nth slave stations 2 (1) ... 2 (n) are respectively connected to a plurality of peripheral devices 5 (1) .. 5 (n) via bus interfaces 4 (1) .. 4 (n). ) Is adopted.

The four cables are clock (CL
Clock transmission line 3A for transmitting K), first data transmission line 3B for transmitting data (MOSI) from the master station to the slave station, second transmission for transmitting data (MISO) from the slave station to the master station It is composed of a line 3C and a control signal transmission line 3D for transmitting a control signal (CTRL).

FIG. 2 shows the plurality of slave stations 2 (1) ...
2 (n) shows an example of one slave station 2, and other slave stations have the same configuration as the example shown in FIG. That is, in FIG. 2, reference numeral 4 surrounded by a broken line indicates an interface, and the four cables 3A to 3D are connected to the interface 4 as described above.

Of the four cables, the timing signal generating section 10 to which the three cables of the clock transmission line 3A, the first data transmission line 3B, and the control signal transmission line 3D are connected, write signals W0 to W0. W15 (illustrated example uses W0 to W7), read signal RD, buffer control signals G0 to G15 (illustrated example uses G0 to G7)
Are generated and output from the output terminals indicated by the same symbols.

The write signals W0 to W15 are output to the output device, that is, the LD of the parallel-in / serial-out shift register 11 functioning as a writing device.
Supplied to the terminal. In the illustrated example, as the write device, only the shift register 11 to which the write signal W0 is supplied is shown, and the others are omitted. Then, only one of the write signals W0 to W15 is made active. Data (MOSI) is supplied to the serial input terminal SI of the shift register 11 from the first data transmission line 3B. The clock (CLK) is supplied to the clock input terminal CLK of the shift register 11 from the clock transmission line 3A.

The read signal RD is supplied to the LD terminals of the input device, that is, the parallel-in / serial-out shift registers 12 and 13 functioning as a read device. Although only the shift registers 12 and 13 are described as the reading device in the illustrated example, there are other devices. Serial input terminals S of the shift registers 12 and 13
For I, the data (M
OSI) is supplied. A clock (CLK) is supplied to the clock input terminals CLK of the shift registers 12 and 13 from the clock transmission line 3A.

The serial output terminals SO of the shift registers 11, 12, and 13 function as return data output terminals, and D-type flip-flops 14, 15, and 16 are provided.
Is supplied to the D terminal. This D-type flip-flop 1
Clocks (CLK) are supplied from the clock transmission line 3A to the clock input terminals CK of 4, 15, 16 respectively, and the outputs from the Q terminals thereof are supplied to the input terminals of the MISO buffers 17, 18, 19 respectively. ..

Any one of the buffer control signals G0 to G15 in the timing signal generator 10 becomes active, and the return data is sequentially sent to the transmission line 3C as MISO data.

FIG. 3 shows details of the interface 4 portion surrounded by the broken line in FIG. That is, the MOSI data obtained via the transmission line 3B is applied to the serial input terminal SI of the first 8-bit shift register 30 and further serially input to the second 8-bit shift register 31 via the serial output terminal SO. It is applied to the terminal SI.

The first and second shift registers 30, 3
1 to the clock input terminal CK from the clock transmission line 3A via the clock transmission switch SW.
LK) is applied. The clock transmission switch SW is on / off controlled by a control signal (CTRL) from the control signal transmission line 3D, and is turned on when the control signal (CTRL) is at a high level "H", so that the clock (CLK) is supplied to both shift registers 31. , 32.

First and second shift registers 30, 31
, The control signal (CTRL) becomes low level in the state that a total of 16 bits of data are loaded by the clock (CLK), and therefore the clock transmission switch SW is turned off. On the other hand, the clock (CLK) is also supplied to the counter 32 via the clock transmission switch SW,
The counter 32 counts the number of incoming clocks (CLK) according to the control signal (CTRL). The output is applied to the first and second count detection circuits 33 and 34. First
The count detection circuit 33 detects the count value "8" or "16", which can be switched according to a continuous mode or a basic mode described later. Also,
The second count detection circuit 34 detects the count value "16".

The upper 4 bits loaded in the first shift register 30 are stored in the 4-bit latch circuit 35 as follows.
It is latched by the output from the first count detection circuit 33. The output of the latch circuit 35 is applied to the 4/16 decoder 36, and the 16-bit signal decoded by the 4/16 decoder 36 is supplied to the first and second gate control circuits 37 and 38, respectively.

On the other hand, of the 8-bit data loaded in the second shift register 31, the MSB is latched in the latch circuit 39 by the signal from the second count detection circuit 34. Also, of the 8-bit data loaded in the shift register 31, the lower 7 bits are added to one of the comparison circuits 40. A 7-bit address A0 to 6 assigned to the bus interface is added to the other side of the comparison circuit 40, and the output of the comparison circuit 40 generated when the two coincide with each other is the second count detection circuit 34.
Latched by the signal from.

The outputs of the latch circuits 39 and 41 are supplied to the timing pulse generating circuit 42. The timing pulse generation circuit 42 includes a clock transmission line 3A.
Further, the clock (CLK) is applied, and in addition, the control signal (CTRL) from the control signal transmission line 3D is also applied. Then, from the timing pulse generation circuit 42, a write control pulse Wx, a buffer control pulse Gx,
And the read control pulse RD is output.

The write control pulse Wx is supplied to the first gate control circuit 37, and actively controls any one of the write signal transmission lines W0 to W15 output from the gate control circuit 37 in order. Further, the buffer control pulse Gx is supplied to the second gate control circuit 38, and sequentially controls any one of the buffer control signal transmission lines G0 to G15 output from the gate control circuit 37 to be active. Further, the read control pulse RD is supplied to the input terminals of the peripheral devices, that is, the LD terminals of the shift registers 12 and 13 functioning as read devices, respectively, as described in FIG.

The operation of each operation mode will be described below with reference to the timing charts shown in FIG. First, FIGS. 4 and 5 show basic mode timing in the synchronous serial bus system of the present invention. FIG. 4 shows a write operation and FIG. 5 shows a read operation. In FIG. 4, CLK indicates a clock in the clock transmission line 3A, and is intermittently transmitted in units of 8 clocks. Further, CTRL represents a control signal transmitted to the control signal transmission line 3D, and takes a binary value of a high level "H" or a low level "L", which will be described later.
Identifies whether it indicates an address or data.

Further, MOSI indicates the data transmitted to the first data transmission line 3B, which is the 8-bit function data F, the 8-bit device address A following the function data F, and the 8-bit serial data following it. D occurs cyclically. In the function data F, one bit of the MSB is an R / W bit indicating a read operation or a write operation, and when it is "1", it is a write W and when it is "0", it is a read R. The lower 7 bits of the function data F are a functional address and determine which of the 4 (1) to 4 (n) bus interface is to be used. The upper 4 bits of the device address A determine which of the shift registers 11 to 13 which are peripheral devices is to be used. Further, the lower 4 bits of the device address A are channel select information,
It is used to select a channel to be used by DAC or the like. And MISO indicates the data transmitted to the second data transmission line 3C.

Here, when CTRL is at a high level, the clock transmission switch SW is turned on in FIG. 3, and the 8-bit function data F of MOSI is converted into the second shift register 31 by the clock CLK. Loaded in. Further, the subsequent 8-bit device address A is loaded into the first shift register 30.

The 7-bit functional address F loaded in the second shift register 31 is applied to one side of the comparison circuit 40, and is applied to the other side of the comparison circuit 40. Compared to 6. That is, among the 4 (1) to 4 (n), only when the bus interface is called by the master station 1, an output is generated from the comparison circuit 40, and the output is sent to the latch circuit 41. The latch command is sent to the latch circuit 41 from the second count detection circuit 34 at the timing when the 16 clocks CLK are counted up. Therefore, the matching output is applied from the latch circuit 41 to the timing pulse generation circuit 42.

On the other hand, the MSB of the 8-bit data loaded in the second shift register 31 is the latch circuit 39.
Latched by. At this time, as described above, MSB
Is a write operation, and the MSB is a "0", a read operation. The R / W pulse that is the identification output is applied to the timing pulse generation circuit 42.

On the other hand, the upper 4 bits of the device address A are latched by the latch circuit 35 and decoded from the 4 bit signal to the 16 bit signal by the 4/16 decoder 36, and the first gate control circuit 37 and the second gate control circuit 37. It is applied to the gate control circuit 38.

Here, CTRL becomes low level, and MO
8-bit serial data D in SI is supplied to the shift registers 11 to 13. At the same time, a Gx pulse is output from the timing pulse generating circuit 42 as shown in FIG. 4, and the second gate control circuit 38 outputs the buffer control signal transmission lines G0 to 15 corresponding to the peripheral device designated by the device address A. Activate one of them.

As a result, one of the buffer circuits 17 to 19 becomes active and the D-type flip-flop 14
The return data is sent to MISO via any one of 16 to 16. When the 8-bit serial data D in MOSI is loaded into the shift registers 11 to 13, the timing pulse generating circuit 42 causes the timing pulse generating circuit 42 shown in FIG.
The Wx pulse is generated at the timing shown in (the timing when the 8-bit data is taken into the shift register 11).

As a result, one of the write signal transmission lines W0 to W15 (W0 in the case of the embodiment) generated from the gate control circuit 37 becomes active,
For example, a shift register 1 as a writing device
From 1 (only one is shown as a representative in FIG. 2), parallel output (writing) corresponding to the serial data D is performed to another device.

Note that the write operation shown in FIG. 4 is characterized in that the return data is returned to MISO even if it is not in the diagnostic mode as will be described later.

FIG. 5 shows a read operation. That is, since the MSB of the function code F in MOSI is "0", that is, read, the bus interface is read by the R / W pulse from the latch circuit 39 in FIG. In this case,
As shown in FIG. 5, when CTRL is shifted to the low level, the timing pulse generating circuit 42 generates an RD pulse, that is, a read signal.

Therefore, the read signal RD is added to the shift registers 12 and 13 which are the read devices in FIG. 2, and all the read shift registers 12 and 13 perform a read operation of, for example, 8-bit parallel data at the same time. To do. Here, a Gx pulse is generated and the second gate control circuit 38 causes the device address A
Any one of the buffer control signal transmission lines G0 to 15 corresponding to the peripheral device designated by 1 is activated.

As a result, one of the buffer circuits 17 to 19 becomes active, and the D-type flip-flop 15
Alternatively, the read data from the shift register 12 or 13 corresponding to the device address A is transmitted to the MISO via 16 or 16.

6 and 7 show diagnostic mode timing in the synchronous serial bus system of the present invention. FIG. 6 shows a write device diagnostic operation and FIG. 7 shows a read device diagnostic operation. That is, in FIG.
The MSB of the OSI function data F is made "0", while the corresponding portion in FIG. 7 is made "1".

First, in the write device diagnosis shown in FIG. 6, the R / W pulse in the latch circuit 39 becomes "0", and the timing pulse generating circuit 4
From No. 2, Gx pulse is generated without Wx pulse being generated. For this reason, one of the buffer control signal transmission lines G0 to 15 (which is determined by the device address A) output from the gate control circuit 38 becomes active, and the MISO shift corresponding to the writing device is shifted. Register (reference numeral 1 in FIG. 2)
MOSI data that has gone through (only one shown by 1) appears. That is, the diagnostic mode is realized without providing a special bit in the functional address or device address.

Next, in the read device diagnosis shown in FIG. 7, the R / W pulse in the latch circuit 39 becomes "1", and the timing pulse generating circuit 4
From 2, the Gx pulse is generated without the RD pulse. For this reason, one of the buffer control signal transmission lines G0 to 15 (one determined by the device address A) derived from the gate control circuit 38 becomes active, and the MISO is a corresponding read device. MOSI data that has passed through the shift register 12 or 13 appears.

Next, FIG. 8 shows the timing of the continuous multi-byte mode in the synchronous serial bus system of the present invention. This corresponds to the first 16 bits while CTRL
Becomes high level, and at this time, 8-bit function data F and 8-bit device address A are sent to MOSI. Therefore, the operation of the bus interface shown in FIG. 3 at this time is the same as the basic mode operation described above. Thereafter, CTRL sequentially repeats low level and high level at intervals corresponding to 8 bits.

At the low level of CTRL, the shift register 12 or 13 as the read device in which the serial data D is determined by the device address A is selected.
Loaded in. At the same time, one of the buffer circuits 17 to 19 generates return data for MISO.

After that, the device address A is sent to the same bus interface in the high level section of the CTRL, and in the next low level section of the CTRL, the device is a read device determined by the device address A as described above. The serial data D is loaded into the shift register 12 or 13, and at the same time, the return data is generated from any of the buffer circuits 17 to 19 to the MISO.

FIG. 9 shows the timing of the irregular mode. The difference from the continuous multi-byte mode shown in FIG. 8 is that, in the case of this embodiment, after the high level in the section corresponding to the first 16 bits of CTRL, the section corresponding to 24 bits is set to the low level. It At this time, the serial data D is loaded twice into the shift register 12 or 13 serving as a read device determined by the device address A, and at the same time, the buffer circuits 17 to 19 corresponding to the device address A respond to the MISO. Return data is generated.

FIG. 10 shows the configuration of the synchronous serial bus system by the multi-master system which is the second embodiment of the present invention. This synchronous serial bus system has a plurality of master stations 1 (1) to 1 (n) as compared with the first embodiment of the present invention shown in FIG. 1, and furthermore, a bus inhibit signal line (BusInh) 3E. Has been added. If the level of the bus inhibit signal line 3E is low level,
The master stations 1 (1) to 1 (n) desiring to transmit output a bus inhibit signal (BUSINH) to the signal line 3E to bring the cable 3E to a high level and acquire its own transmission right (bus right). .. As a result, even if another master device desires transmission immediately after that, the transmission right cannot be acquired until the cable 3E becomes low level. 1 who got the bus transmission right
The transmission operation of one master station, its transmission data, the response operation of the slave station side, etc. are the same as the operations and transmission data in the synchronous serial bus system of the first embodiment described above.

The master station that has acquired its own transmission right is
When the desired communication is completed, the bus inhibit signal line 3E is set to low level to release the inhibit state of the cable 3E. Therefore, after that, the second master station can communicate.

[0053]

As is apparent from the above description, according to the synchronous serial bus system of the present invention, a clock transmission line is provided between one master station and a plurality of slave stations, and the master station is connected to the slave station. A first data transmission line for transmitting data to the station, a second transmission line for transmitting data from the slave station to the master station, and a control signal transmission line for transmitting control signals. Data is mutually transmitted between the master station and the plurality of slave stations by the first data transmission line and the second transmission line.

At this time, the first data transmission line is
At least during the transfer of data indicating the device address, the level of the control signal transmission line is set to a high level, and the first data transmission line is at least during the transfer of serial data from the master station to the slave station, And while the second data transmission line is transferring the return data from the slave station to the master station,
The level of the control signal transmission line is set to low level.

Therefore, the access and data transmission modes are set by the level of the control signal transmission line, data transmission between the master station and a plurality of slave stations can be achieved by a simple protocol, and the bus interface is relatively simple. Can be realized with a simple configuration. In addition to the basic mode, continuous mode, and irregular mode, it is possible to set the write device and read device diagnostic modes, and highly reliable synchronous data communication can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a synchronous serial bus system of the present invention.

FIG. 2 is a connection diagram showing a configuration of a slave station in the embodiment of FIG.

FIG. 3 is a connection diagram showing a configuration of a bus interface portion surrounded by a broken line in FIG.

FIG. 4 is a timing diagram showing a write operation in a basic mode of the synchronous serial bus system of the present invention.

FIG. 5 is a timing chart showing a read operation in the same basic mode.

FIG. 6 is a timing diagram showing a write device diagnostic mode.

FIG. 7 is a timing diagram showing a read device diagnostic mode.

FIG. 8 is a timing diagram showing a continuous multi-byte mode.

FIG. 9 is a timing diagram showing an irregular mode of the same.

FIG. 10 is a block diagram showing the configuration of a second embodiment of the synchronous serial bus system of the present invention.

[Explanation of symbols]

 1, 1 (1) to 1 (n) Master station 2, 2 (1) to 2 (n) Slave station 3A Clock transmission line 3B First data transmission line 3C Second data transmission line 3D Control signal transmission line 3E Inhibit signal line 4, 4 (1) to 4 (n) interface

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[Procedure amendment]

[Submission date] March 17, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

The I ² C bus system uses a clock (SC
L) and data (SDA) are bidirectionally transmitted by using two cables.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

In the IM bus system, a control signal (Ident) is transmitted in addition to the clock and data to detect the device address at the head of the instruction code of a plurality of bytes sent from the master station to the slave station. The line is added. In this IM bus system, the control signal line is "EN
By placing the "D" code, the delimiter for each instruction is clarified and the occurrence of malfunction is prevented.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

The write signals W0 to W15 function as an output device, that is, a write device.
It is supplied to the LD terminal of the serial-in / parallel-out shift register 11. In the illustrated example, as the write device, only the shift register 11 to which the write signal W0 is supplied is shown, and the others are omitted. Then, only one of the write signals W0 to W15 is made active. The serial input terminal SI of the shift register 11 has a first data transmission line 3
Data (MOSI) is supplied from B. The clock (CLK) is supplied to the clock input terminal CLK of the shift register 11 from the clock transmission line 3A.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

Further, MOSI represents data transmitted to the first data transmission line 3B, and is an 8-bit fan.
Function address F, the subsequent 8-bit device address A, and the subsequent 8-bit serial data D are cyclically generated. The function
The address F is an R / W bit in which one bit of the MSB indicates a read operation or a write operation. When the address F is "1", it is a write W and when it is "0", it is a read R. Also,
The lower 7 bits of the function address F are a functional address and determine which bus interface is used among 4 (1) to 4 (n). The upper 4 bits of the device address A determine which of the shift registers 11 to 13 which are peripheral devices is to be used. Further, the lower 4 bits of the device address A is channel select information, which is used for selecting a used channel such as DAC.
And MISO indicates the data transmitted to the second data transmission line 3C.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0050

[Correction method] Change

[Correction content]

FIG. 9 shows the timing of the irregular mode. The difference from the continuous multi-byte mode shown in FIG. 8 is that, in the case of this embodiment, after the high level in the section corresponding to the first 16 bits of CTRL, the section corresponding to 24 bits is set to the low level. It At this time, 16-bit serial data D is loaded into the shift register 12 or 13 as a read device determined by the device address A, and at the same time, the buffer circuits 17 to 19 corresponding to the device address A Return data is generated for MISO.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0051

[Correction method] Change

[Correction content]

FIG. 10 shows the configuration of a synchronous serial bus system based on the multi-master system which is a second embodiment of the present invention. This synchronous serial bus system has a plurality of master stations 1 (1) to 1 (n) as compared with the first embodiment of the present invention shown in FIG. 1, and furthermore, a bus inhibit signal line (BusInh) 3E. Has been added. If the level of the bus inhibit signal line 3E is high level ,
The master stations 1 (1) to 1 (n) desiring to transmit output a bus inhibit signal (BUSINH) to the signal line 3E to set the cable 3E to a low level and acquire their own transmission right (bus right). .. As a result, even if another master device desires transmission immediately after that, the transmission right cannot be acquired until the cable 3E becomes high level . 1 who got the bus transmission right
The transmission operation of one master station, its transmission data, the response operation of the slave station side, etc. are the same as the operations and transmission data in the synchronous serial bus system of the first embodiment described above.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0052

[Correction method] Change

[Correction content]

When the desired communication is completed, the master station which has acquired the transmission right of itself sets the bus inhibit signal line 3E to the high level to release the inhibit state of the cable 3E. Therefore, after that, the second master station can communicate.

Claims (1)

[Claims] 1. A plurality of stations connected to each other by a four-wire circuit, wherein the four-wire circuit supplies a clock between one master station and a plurality of slave stations of the plurality of stations. A clock transmission line for transmission, a first data transmission line for transmitting data from the master station to the slave station, a second transmission line for transmitting data from the slave station to the master station, and a control signal transmission line for transmitting control signals. In the synchronous serial bus system connected via, a device address is set for each slave station, and the master station outputs a control signal to a control signal transmission line and a clock to a clock transmission line. With
The device address of the slave station to which the serial data is to be transmitted and the serial data are transmitted to the first data transmission line, and the slave station receives the serial data in response to the control signal and the clock transmitted from the master station. A data received by a slave station having a matching device address is transmitted to the master station via the second transmission line, wherein the first data transmission line indicates at least a device address. Of the control signal transmission line is set to one of a high level and a low level, and the first data transmission line is transmitting at least serial data from the master station to the slave station. , And the second data transmission line is a return signal from the slave station to the master station. During data transfer, the synchronous serial bus system, characterized in that the level of the control signal transmission line is made to the other level. [0001]