KR20140030159A - Control device having a digital interface - Google Patents

Abstract

The present invention relates to a control device 10 and a microcontroller 40 for the control device 10. The control device 10 includes a microcontroller 40 and a digital interface, the digital interface comprising a transceiver unit 44 and one or more interface controllers 46, wherein the one or more interface controllers 46 of the digital interface are micro It is integrated in the controller.

Description

CONTROL DEVICE HAVING A DIGITAL INTERFACE

The present invention relates in particular to control devices for automobiles and microcontrollers for such control devices.

The interface is used for example for data exchange between the sensor and the control device assigned to it. In particular, automobiles use digital interfaces to enable safe and fast exchange of data. PSI5 (Peripheral Sensor Interface 5) is a digital interface for sensors, which is based on a two-wire track and is used to connect sensors mounted in automotive electronics to electronic control devices. Point-to-point and bus configurations are assisted with concurrent and asynchronous communications.

PSI5 is then operated to transmit data to the supply line according to the principle of current interface modulation of the transmit current. Higher coherence resistance is achieved through relatively high signal currents and bit coding in Manchester code, which is enough to use inexpensive two-wire lines for wiring.

For several years, the automotive industry has also used sensors with PSI5-interfaces and corresponding receiver data receivers and transceivers. Similarly bidirectional communication is possible via synchronization pulses, where data from the control device to the sensor is via synchronization pulses, with or without the presence. Thus, the information of "exists" corresponds logically "1" and the information of "not present" logically corresponds to "0".

All receivers and transceivers provide a Manchester decoder and SPI interface for transferring data to the microcontroller. Commercially available receivers and transceivers for generating synchronization pulses require a higher voltage (Vsync) than the sensor supply voltage for sensor standby current (VAS). However, there is no time stamp and no information on how old the received data is.

It should be noted that currently used engine control devices provide no overall solution or at least a low cost overall solution for measurement of Manchester coded data and bidirectional communication with PSI5 sensors. Therefore, there is no possibility of recognizing engine performance tuning.

In this context, a control device according to claim 1 and a microcontroller having the features of claim 9 are provided. Embodiments are provided through the dependent claims and the specification.

The provided control device provides a low cost hardware solution for the engine control device. This feature is ensured even at low battery voltages up to 3V at start-up. Logic also allows bidirectional communication when using synchronization pulses of varying lengths for "1" and "0".

The generation of the Vsync voltage can be implemented with a circuit (boot strap) integrated in the transceiver. In addition, fast data transmission of time-critical sensor data and generation of sensor data can be determined. In addition, recognition of engine performance adjustments is possible through distortion of the sensor data. This is made possible by bidirectional communication.

The hardware described above is a low cost solution for the measurement of PSI5 sensor data and bidirectional communication with PSI5 sensors. Significant advantages are provided over known solutions in at least some embodiments. This allows a lower cost solution when using a bootstrap circuit inside the transceiver to generate Vsync voltages than a solution using a step-up converter. In addition, by moving most of the digital functions from the transceiver (CRC calculations, error management of PSI5 frames, etc.) to the microcontroller, cost reduction can be achieved since this results in a reduction in the area of silicon.

While synchronization pulses having various lengths for "0" and "1" are used for bidirectional communication, the prevention of additional jitter of sensor data caused by nonexistent synchronization pulses can be further achieved. Direct triggering of the sync pulse output through discrete computer ports can reduce latency and latency jitter on sensor data. The maximum achievable data transmission is particularly important for the detection of time critical sensor data (rail pressure sensors).

It should also be noted that the "age determination" of the rail pressure sensor data, in turn, enables the development of software functions that ensure the achievement of the EURO 6 regulations or OBDII. Bi-directional communication is very useful for automakers, for example, to be able to recognize engine coordination via sensor manipulation and thereby detect unwarranted warranty cases (eg, warranty investigation in case of engine damage).

Software resource demand can also be reduced by lifetime, RAM demand, and interruption processing through hardware interfaces. The digital interface is not necessarily required as an interface for transmitting diagnostic information. Diagnostics can be made for all three (or more) transceivers via the ADC input. For all PSI5 transceivers integrated in the ASIC, diagnostics can be made according to UBAT and GND. Load reduction can also be diagnosed. All cases of error are clearly distinguishable.

Other advantages and embodiments of the present invention are provided in the specification and the accompanying drawings.

The features previously specified and further described below, as well as the combinations provided respectively, may be used alone or in other combinations without departing from the scope of the invention.

1 is a schematic diagram of an embodiment of a provided control device.
2 is a block circuit diagram of another embodiment of a provided control apparatus.

The invention is schematically illustrated by the embodiments in the drawings and described in detail in connection with the drawings as follows.

The embodiment of the control device described above in FIG. 1 is shown in schematic diagram and generally indicated by reference numeral 10. The control device 10 has a first sensor 12, a second sensor 14, a third sensor 16, a fourth sensor 18, and a fifth sensor via a two-wire line 26. And a plurality of sensors of the 20, the sixth sensor 22, and the seventh sensor 24.

The control device 10 includes a microcontroller 40 and a dedicated integrated circuit (ASIC) 42 which is again provided with a transceiver unit 44 for a digital interface. The interface controller 46 for digital interface is integrated in the microcontroller 40. Through the digital interface realized through the transceiver unit 44 and the interface controller 46, communication between the control device 10 and the sensors 12 to 24 takes place.

The microcontroller 40 and the transceiver unit 44 are connected to each other via an interface, in this case via an SPI interface 48. This exchanges the necessary data. Similarly, an ASC interface and / or a parallel interface that can be used for communication between the transceiver and the microcontroller can alternatively be used.

The digital interface of the control device 10, which is implemented via the transceiver unit 44 and the interface controller 46, bidirectionally communicates with the sensors 12 to 24 and, of course, the closed circuit control and the opening of the progress of the functional unit of the automobile engine, for example. It also allows bi-directional communication with actuators (not shown) for control.

FIG. 2 shows a block circuit diagram of a control device 50 having a microcontroller 52 and a transceiver unit 53 implemented in an ASIC 54. The control device 50 communicates with the first sensor 56, the second sensor 58, and the third sensor 60 via the first PSI5 transceiver 130.

In the microcontroller 52, a block 70 having a RAM module 72 and a computer core 74 is provided. The microcontroller 52 also includes an SPI module 76, an ADC 78, a block 80 and a GTM 82 for direct access memory (DMA). In the microcontroller 52, a first interface controller 84, a second interface controller 86, and a third interface controller 88 are provided. Of the three interface controllers 84, 86, 88 formed as PSI5 controllers, only the first interface controller 84 is shown in detail for simplicity. Basically, a few interface controllers can also be integrated.

The first interface controller 84 intermediates the received PSI5 frame, the time registers attributed to the frame and the RAM register 100 for storing the diagnostic bits, and the immediately received PSI5 frame and the time stamps attributed to the frame. RAM receive register 102 for storage, Manchester decoder 104, RAM register 106 for any serial data frame (PSI5 specification V2.0: see serial channel), and diagnostics of the immediately received PSI5 frame. Diagnostic register 108 for intermediate storage of bits, unit 110 for the output of trigger pulses for generating synchronization pulses, and upstream data for the preparation and intermediate storage of data to be sent to sensors or actuators 112 Register and configuration register 114.

In the transceiver unit 53, the multiplexer 120, the first bootstrap circuit 122, the second bootstrap circuit 124, the first PSI5 transceiver 130, and the second PSI5 transceiver 132 are provided. And a third PSI5 transceiver 134 and a load pump 136 are provided. The voltage regulator 140 is provided for the voltage supply. A few PSI5 transceivers and bootstrap circuits may also be integrated.

The illustrated control device 50 is applied, for example, to a drive or power train of a motor vehicle. The voltage supply of the PSI5 transceiver 130, the PSI5 transceiver 132, and the PSI5 transceiver 134 in the ASIC 54 is via the VPR voltage of the voltage regulator 140. For this purpose the regulator is provided via a boost regulator as well as a buck regulator.

This allows the VPR voltage to be at approximately 6V, even if the battery supply voltage of the engine control device drops to, for example, 3V during the startup process. In order to ensure minimum supply voltages specific to PSI5 for sensors 56, 58 and 60, initial voltage regulator 140 offers the possibility to increase the VPR voltage from 6V to 6.5V per SPI. Two bootstrap circuits 122 and 124 are used for the generation of the Vsync voltage. These solutions are more cost effective than solutions using step-up converters.

The main functions of the PSI5 transceivers 130, 132 and 134 are:

Voltage supply of sensors such as, for example, sensors 56, 58 and 60 in the PSI5 transceiver 130,

Generating a synchronization pulse,

To convert current modulated sensor data into voltage modulated data.

Transceiver inputs 160, 162, and 164 are used as trigger signals for synchronization pulses. Trigger signals are generated at PSI5 controllers 84, 86, and 88 of microcontroller 52. Manchester coded data is sent directly to the microcontroller 52 via separate lines 150, 152 and 154 for each transceiver 130, 132 and 134. This enables higher transmission rates and stability of transmission than the transmission of all sensor data via SPI or ASC. Other advantages over SPI data transmission are latency optimized transmission and SW resource optimized transmission.

This gives an advantage for time critical sensors, for example rail pressure sensors. The sync signal (in the form of sync pulses) can be generated with minimal latency jitter. The data are decoded at the PSI5 controllers 84, 86, and 88 of the microcontroller 52 and provided with a time stamp. This makes it possible to determine the generation time of the sensor data.

PSI5 controllers 84, 86, and 88 in microcontroller 52 generate a trigger signal for the sync pulse and determine the length of the sync pulse. This enables "upstream" communication (microcontroller to sensor). This type of communication has the advantage that additional jitter caused by different sensor clocks and microcontroller clocks can be avoided, compared to a communication solution via nonexistent sync pulses.

This depends on the sensors 56, 58 and 60 being synchronized to the rising flank of the sync pulse and transmitting data after the recognition of the flank. If the microcontroller 52 has to send data to sensors 56, 58 and 60, for example comprising three consecutively output "0s", the controller results in three non-existent synchronization pulses.

Sensors 56, 58, and 60 must provide a timer that enables the transmission of data within the correct time period. Since the sensor clock provided to the timer has a different frequency than the microcontroller clock, additional jitter occurs at this time.

The sensor data is transferred from the RAM register 100 of the PSI5 controller 84 to the RAM 72 of the microcontroller 52 via the DMA 80 and then provided to the computer core 74. The block 70 (RAM 74 + computer core or μC core 74) meets ASIL D.

The integration of RAM registers and digital functions such as generation of trigger signals for sync pulses and Manchester decoding into the microcontroller 52 results in cost savings over solutions using "stand-alone" PSI5 transceivers. This, together with the bootstrap circuit, makes it an optimal cost solution for PSI5 applications.

The microcontroller 52 may provide an encryption concept that enables secure performance tuning recognition, and a question-and-answer method through bidirectional communication is also possible.

Claims (10)

A control device with a microcontroller 40, 52 and a digital interface, wherein the digital interface includes transceiver units 44, 53 and one or more interface controllers 46, 84, 86, 88, and one or more of the digital interfaces. The interface controller (46, 84, 86, 88) is integrated in the microcontroller (40, 52). The control device of claim 1 comprising a PSI5 interface as a digital interface. The control device according to claim 1 or 2, wherein an external voltage regulator (140) is provided for supplying voltage to the transceiver unit (44, 53). 4. Control device according to any one of the preceding claims, wherein an SPI interface (48) is provided for communication between the microcontroller (40, 52) and the transceiver unit (44, 53). 5. The control device according to claim 1, wherein the transceiver unit (44, 53) is implemented in a dedicated integrated circuit (ASIC). The control device according to any one of the preceding claims, wherein a Manchester decoder (104) is provided in at least one interface controller (46, 84, 86, 88). The control device according to any one of the preceding claims, wherein a charge pump (136) is provided within the transceiver unit (44, 53). 8. The control according to claim 1, wherein in the microcontroller 40, 52 an ADC 78 is provided for diagnosis of the output voltage of the transceiver units 44, 53. 9. Device. A microcontroller for a control device (10, 50), wherein an interface controller (46, 84, 86, 88) of a digital interface is integrated in the microcontrollers (40, 52). 10. The microcontroller of claim 9, wherein an interface controller (46, 84, 86, 88) is provided for a PSI5 interface.

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