JPS6219746U - - Google Patents

Info

Publication number
JPS6219746U
JPS6219746U JP11066085U JP11066085U JPS6219746U JP S6219746 U JPS6219746 U JP S6219746U JP 11066085 U JP11066085 U JP 11066085U JP 11066085 U JP11066085 U JP 11066085U JP S6219746 U JPS6219746 U JP S6219746U
Authority
JP
Japan
Prior art keywords
layer
insulating layer
circuit body
covering
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11066085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11066085U priority Critical patent/JPS6219746U/ja
Publication of JPS6219746U publication Critical patent/JPS6219746U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係わる混成集積回
路を示す断面図、第2図は本考案の他の実施例に
係わる混成集積回路を示す断面図である。 1……基板、2……回路部品、3……引出端子
、4……回路本体、5……第1絶縁層、6……導
電体層、7……第2絶縁層、8……引出線。
FIG. 1 is a cross-sectional view showing a hybrid integrated circuit according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a hybrid integrated circuit according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Board, 2... Circuit component, 3... Output terminal, 4... Circuit body, 5... First insulating layer, 6... Conductor layer, 7... Second insulating layer, 8... Drawer line.

Claims (1)

【実用新案登録請求の範囲】 (1) 基板上に各種回路部品を搭載し引出端子を
引出した回路本体と、該回路本体を被覆した第1
絶縁層と、該第1絶縁層を被覆した導電体層また
は磁性体層と、該導体層または磁性体層を被覆し
た第2絶縁層とを具備したことを特徴とする混成
集積回路。 (2) 第1絶縁層を貫通し回路本体と導電体層ま
たは磁性体層とを引出線にて導通したことを特徴
とする実用新案登録請求の範囲第(1)項記載の混
成集積回路。
[Claims for Utility Model Registration] (1) A circuit body with various circuit components mounted on a board and a lead-out terminal, and a first circuit body covering the circuit body.
1. A hybrid integrated circuit comprising: an insulating layer; a conductive layer or a magnetic layer covering the first insulating layer; and a second insulating layer covering the conductive layer or the magnetic layer. (2) The hybrid integrated circuit according to claim (1) of the utility model registration, characterized in that a lead wire penetrates the first insulating layer and connects the circuit body and the conductive layer or the magnetic layer.
JP11066085U 1985-07-18 1985-07-18 Pending JPS6219746U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11066085U JPS6219746U (en) 1985-07-18 1985-07-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11066085U JPS6219746U (en) 1985-07-18 1985-07-18

Publications (1)

Publication Number Publication Date
JPS6219746U true JPS6219746U (en) 1987-02-05

Family

ID=30989867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11066085U Pending JPS6219746U (en) 1985-07-18 1985-07-18

Country Status (1)

Country Link
JP (1) JPS6219746U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157498U (en) * 1988-04-06 1989-10-30
WO2018206594A1 (en) 2017-05-12 2018-11-15 Magna Powertrain Bad Homburg GmbH Component having emv protection for an electronic board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0235467A (en) * 1988-07-26 1990-02-06 Fuji Xerox Co Ltd Reference timing signal generating device for recorder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0235467A (en) * 1988-07-26 1990-02-06 Fuji Xerox Co Ltd Reference timing signal generating device for recorder

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157498U (en) * 1988-04-06 1989-10-30
WO2018206594A1 (en) 2017-05-12 2018-11-15 Magna Powertrain Bad Homburg GmbH Component having emv protection for an electronic board
DE102017208075A1 (en) * 2017-05-12 2018-11-15 Magna Powertrain Bad Homburg GmbH Component with EMC protection for electronic board

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