JPS62191974A - Pattern memory reading circuit - Google Patents

Abstract

PURPOSE:To improve operability and to decrease the load on a processor in a device by providing an index register, a selector to make variable the connecting condition between an address counter and a pattern memory and a pattern size register to control it. CONSTITUTION:When a processor stores pattern data to a pattern memory 3, the size is also stored into another RAM. When the 'surface' processing is executed and a pattern number is set to an index register 1, simultaneously, the size is stored into a pattern size register 7, read from the RAM and set as a pattern size code. Thus, the selector generates the connecting condition in accordance with the value of the pattern size code.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a raster scan type display device and a raster type printing device, in which three types of data that a user causes these devices to process, namely "dots", "Line 1." Surface (
This invention relates to a method for reading a pattern memory that stores data to be embedded in a "surface" when performing one process.

(Summary of the Invention) The present invention provides a process in which a user determines an area using a specified pattern.
By making it possible to vary the pattern size of 8x8.16x16 dots in powers of 2, such as 2x, 4x, 8x, etc., it is possible to increase the whiteness of the data handled by the user. It is also possible to reduce the load on the processor within the device.

(Prior art) A conventional pattern memory readout circuit is shown in Fig. 2.
As shown in FIG.
A pattern/memory 3 for storing data and an image memo 1 for forming and holding data to be output to a display device or printing device.
4, and a write control circuit 5 that generates write pulses for the image memory 4 and updates the value of the address counter 2. Although not shown, it goes without saying that the image memory 4 includes additional circuits for "dot" and "line" processing, a display device, and a circuit specific to a printing device. In this configuration, a processor (hereinafter referred to as μP
) stores the "surface" processing data in the pattern memory 3 in advance, and when actually performing surface 1 processing, index register 1 stores the number of the pattern to be used in address register 2. The writing start address to the image memory 4 is set to the image memory 4, the writing end address is set to the reading control circuit 5, and the reading control circuit 5 is started. To simplify the J3 device, the address register 2 and write control circuit 5 are not specially installed), and the μP
In some cases, the address bus 1 acts as the address counter 2, and the μP control signal and the program 1 act as the write control circuit 5.

The write control circuit 5 whose start is applied to μP is μP.
Signal 1 for updating address counter 2 and writing to image memory 4 until the end condition given to
Give 3. At this time, all or part of the output 10 of the index register 1 and the output 11 of the address counter 2 constitute the address line of the pattern memory 3, and the pattern memory 3 corresponding to the value of the address line
The output 12 is the data to be written into the image memory 4.

More specifically, output 1 of index register 1
0 is connected to the upper part of the address line of the pattern memory 3, and the output 11 of the address counter 2 is connected to the lower part, so the address line of the pattern memory 3 is connected to the upper part - fixed part, and the lower part -
It becomes the circulation part. For example, if the lowest 6 bits of address counter 2 are connected to the lower 6 bits of pattern memory 3, and the upper half is connected to index register 1, then the entire value of address counter 2, etc. At best, it only affects the lower 6 bits of the pattern memory 3, and the pattern memory 3 can only be read within the range indicated by the 16 bits of the address fixed part. In other words, by causing a cycle of 6 bits [.

The size of the Zunawara circulation part indicates the size of the pattern. The value of 6 bits 1 to 1 given here as an example means an 8.times.8 dot 1-nice pattern when the output 12 of the pattern memory 3 is 1 bit. The upper 3 bits of the 6 bits are the address in the X-axis direction, and the lower 3 bits are the Y address.
This is an axial address. The names X and Y are given for convenience, and it does not matter if either of the orthogonal coordinates is called X or Y.

(Problems to be Solved by the Invention) The conventional method has a problem in that the pattern memory 3 is uniformly divided by the output 10 of the index register 1. Conversely, there is a problem in that the number of connected address counters 2 and pattern memories 3, which indicate the size of the pattern, is fixed. For example, if the number of connections between the address counter 2 and the pattern memory 3 is 6 trees, the size is 8 x 8 dots as shown in the example above, and a pattern larger than that cannot be processed, and a pattern of a smaller size, for example 4 When the ×4 dot pattern is stored in the pattern memory 3 by the μP, the same data must be written four times. This is because the memory capacity ff for 8x8 dots, 164 bits, is four times as large as the 16 bits of data for 4x4 dots. This problem imposes extremely strong restrictions on the user's processing, and places an unnecessary load on μ[).

(Means for solving the problem) In order to solve the conventional problem, a selector that changes the connection state between the index register, address counter, and pattern memory, and a selector that controls them are provided. The structure has a pattern size register or a pattern size RAM.

(Operation) The operation of the selector will be explained using FIG. pattern·
For example, it is assumed that the memory has 12 address lines, starting from A11 and ending with AO. Also, the output of the index register is I
Although the number of bits of the address counter itself depends on the image memory, the number of bits input to the selector is assumed to be 10 from the top to AC9-O. SC in Table 1 means the output 2 pins 1 to 1 of the pattern size register, and the selector can create four connection states depending on the values of the 2 pins. Among them, when 5C=11, the output of the index register is IR7.

6-2, the output of the address/7J counter is connected to the address line of the pattern memory with 10 lines of AO9 and -0, and handles a pattern with a size of 32 x 32. Also, 5c
When =oo, the output of the address counter can handle a 4-tree r4x4 size pattern of AC3 to O.

From this table, the meaning of the index register (from the fourth
It will look like the figure.

The operation is as follows. First, when μP stores the pattern data in the pattern memory, the size of the data is also stored in another RAM. Then, when performing the process, the pattern number is set in the index register, and at the same time, the size is stored in the pattern size register a3, read out from the RAM, and set as SC. This allows the selector to create a connection state according to the SC value.

(Example) Embodiments of the present invention will be described below based on the drawings.

As shown in FIG. 1, there is an index register 1 for specifying a pattern number, an address counter 2 that holds the reload address to the image memory 4, and whose value is updated each time the fortune-telling progresses. Index register 1 output 10
A selector 6 generates a read address 13 of the pattern memo 3 from the output 11 of the 7 address counter 2.
and a pattern (size register 7) that outputs the control line 14 that determines the operation of the selector 6.
and the image memory 4 which receives the output 12 of the pattern memory 4 and forms and holds data to be output to an actual display device or printing device, until the value of the address counter 2 matches the end address at which μP is set. address counter 2
It consists of a write control circuit 5 that updates the value of and applies write pulses to both image lenses 14. The explanation will be made assuming that the selector 6 is -6 which performs the operation η shown in Table 1. After μP sets the write start address in address counter 2, SC in pattern size register 7, and write end address in write control circuit 5, it becomes 1! Input control circuit 5
I will start on. At this time, if the value of SC is, for example, 01, reading is performed from pattern measurement 3 as follows. The number specified by IR7~2 is pattern memory 3.
The lower six lines AC5-0 of the output 11 of the address counter 2 act on A11-6 of the address lines 13 of the address counter 2. Therefore, address 1 in the range indicated by AC5 to AC0.
3 is cycled, and a repeating pattern appears at the output 12 of pattern method 3. If you choose the SC value of Haku, there is a C as well. In this way, in the example in Table 1, four pattern sizes can be selected, but register 1. Pattern/Size/
Regisuf 6. It goes without saying that increasing the number of bits in the reflector 5 will increase its degree of freedom.

In this configuration, f is stored in pattern memory 3 in advance.
- When storing a pattern, its size is stored in a RAM (not shown), and the pattern size is
The register must be set.

Figure 3 solves the problem of the pattern/1 size register described in Figure 1, that is, the problem of having to set the pattern, size, and code SC each time when [area] is processed. Here is an example.

In other words, pattern size RAM 8 is placed instead of pattern size register, and pattern memory 3
When data is stored in the pattern/swiss RAM
[When performing one-plane processing, all outputs 10 of index register 1 (
, or the part is the pattern size RAM
8, the SC is automatically output, and the operation of the selector 6 is determined.

(Effects of the Invention) As described above, the present invention provides a method for using a pattern memory for "area" processing, and enables "■" to freely select the size of pattern data by a power of 2 with a small amount of effort. This has the effect of greatly improving operability and reducing the load on the μP inside the device.Furthermore, by setting the pattern, size, and RAM, the It also improves processing speed.

[Brief explanation of drawings]

FIG. 1 is a diagram of a first embodiment of the present invention, FIG. 2 is a diagram of a conventional pattern merging readout circuit, and FIG. 3 is a block diagram of a second embodiment of the present invention. , FIG. 4 is an explanatory diagram of the index register, and FIG. 5 is an explanatory diagram of the operation of the selector. 1... Index register 2... Address counter 3... Pattern memory 4... Image memory 5... Write control circuit 6... Selector 7... Pattern size register 8... ...Pattern/Size/RAM Applicant: Seiko Electronics Co., Ltd. bD Bataan no Sori? Ushiμ Lord, Ward jhere 7ν,
, Figure 2, Figure 3

Claims (2)

[Claims] (1) An image memory that holds image data to be displayed or printed, a pattern memory that stores data to be transferred to the image memory, an index register for specifying the read address of the pattern memory, and a pattern memory that stores the data to be transferred to the image memory. an address counter that determines a memory read address and an image memory write address; and a write control circuit that updates the address counter value until the address counter value matches a certain value and provides a write control signal to the image memory. In a pattern memory readout circuit consisting of a selector that switches the connection between the output of the index register and address counter and the address line of the pattern memory, and a pattern size register that specifies the operation of the selector, the pattern memory is read out. A pattern memory read circuit characterized by being able to vary the size of data read from. (2) Claim (1) characterized in that the pattern size register is provided with a pattern size RAM.
pattern memory readout circuit.