JPS60173583A - Texture pattern generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a texture pattern generation method for filling in the white sum of a closed figure with a specified dream-like stealth pattern in a graphic display. , [Prior Art] In computer graphics, etc., conventional patterns have been used, such as horizontal hunting, vertical... As shown, V! of closed figure A! When filling in all of A, the Uri-Stu-Batare-Yao method is as follows.
Broadly speaking, the following two methods are adopted. One method is to use software to determine whether a certain point inside closed figure A is white or black (in the case of multivalued or color display, a specified gradation or color), and store the information in display memory. Hereinafter, this method will be referred to as conventional method I). In this conventional method, the address of a point inside the closed figure A is calculated, and one point and whether it is white or black are calculated. It is necessary to perform all the determinations, which has the drawback of requiring a large amount of processing time for the IP and CPU (central processing unit).

Another method is to store a two-dimensional texture pattern (or part of it) on a turntable in advance in the form of a secondary light array, and then create a pattern corresponding to the address of a point inside the closed figure A. information is stored in the display memory by referring to the contents of the pattern table.
(Hereinafter, this method will be referred to as all conventional methods ■).

The third figure is a block diagram showing the configuration of conventional method (2), which is an example of a conventional chixtenia pattern generation method. In the figure, 1 is the host computer, 2. is C for graphic processing
PU, 3 is display memory, 4 is data selector, 5 is C
An RT (cathode ray tube) display, 6 is a pattern table. In the conventional system shown in FIG. 3, the CPU 2 for graphic processing is the host computer JI! #Receives the graphic command sent from machine 1 and displays this graphic command?
7)" k Interpretation.Then, the necessary operations are performed for each graphic command, and the specified closed figure is developed into dots and written into the display memory 3.The CRT display 5 has - The contents of memory 3 are 60)t
It is read out and displayed on Z and . Note that readout from the display memory 3 to the CRT display 5 and access to the display memory 3 from the graph ink processing CPU 2 and the like are performed in a time-sharing manner. In a mode other than when painting the inside of a closed figure with a chixtenia pattern, such as drawing a straight line or a contour, the data bus is selected by the data selector 4 as the data input to the display memory 3, and the graph is The address of each dot constituting the closed figure calculated by the ink processing CPU 2 is transmitted via the address bus, or the contents of the dot (in the case of binary display,
0" or "1") are applied to the display memory 3 via the data bus and written therein. In the mode of filling the inside of a closed figure with a chixtenia pattern, the address inside the closed figure calculated by the graphics processing CPU 2 is given to the display memory 3, and that address (or part of it) is used as the pattern. given in Table 6. In the pattern table 6, a chixtenia pattern to be read out by the graphic processing CPU 2 is specified in advance, and the contents of the chixtenia pattern are sequentially read out according to the given address. At this time, (1) the data selector 4 selects the pattern table 1IllK cut coating etc.)1. Tetsu? Then, the chixtenia pattern read from the given address t1t: pattern table 6 is written into the display memory 3.

4(a) and 4(b) respectively show configuration examples of the pattern table in FIG. 3. FIG. 4(a) shows horizontal and vertical (X direction and Y direction) hatching intervals (Lx
, Ly ) is (1,1), (2,2), (3゜3)
This is an example of the configuration of a cross hunting pattern table in the case of . The pattern table shown in the figure has a minimum configuration for each cutting interval (Lx, Ly). That is, in Fig. 4(b), the batten (interval (Lx, Ly) = (2, 2)
In this case, the minimum area constituting the crosshatching pattern is a 4×4 area.

Therefore, the pattern table Kli shown in FIG. 4 (81 and (b)) is
The lower address of the internal address of the closed figure given from 2 is given to each tucking interval (LX e Ly ). For example, when the hatching interval (Lx, Ly)=(2°2), only the lower two bits of each x and y address are given to the pattern table, and the contents of the pattern table of that address are read out.

In the conventional method H described above, the pattern table is configured with a memory that can be read out at high speed, and the coordinates of the points inside the closed figure O divided by the graphic processing CPU 2 in Fig. 3 are calculated using a vector generator, etc. By calculating with a hardware circuit and providing it to the pattern table, it is possible to fill the inside of a closed figure at high speed using a chixtenia pattern. However, Fig. 4(a)
As explained in and (b), since the size of the pattern table differs depending on the hunting interval (Lx, Ly), control is performed according to the lower order hatching interval (Lx, Ly) of the address given to the pattern table. Is it necessary? If pattern tables of different sizes are configured without waste on an actual memory, this address control generally has the disadvantage of becoming extremely complex. In addition, in order to solve this problem of address control, if all the pattern tables are made into paddles of the same size and k as shown in Fig. 5, then one pattern table in the case of cross hunting is Size SL
is S+ "" (L-C1vN(2,4, --...
, 2n, ) ) 2 ''-... (1 n. However, ng is the rhyme value of the hunting interval (Lx, Ly), and L, C, and M indicate the least common multiple. (−
Therefore, hatching fiJ [(Lx, Ly)=
(n, n), (n=1121...In+l
&le), the total size S of the pattern table is:

52-3・nl, 1・S ・・・ ・ ・・・・・
...It becomes 121. Since it is clearly 82χ(n,), there is a drawback that if nl is large, the pattern table becomes very large.

[Summary of the invention]

This invention was made for the purpose of improving the conventional system as described above, and it uses a one-dimensional X-direction pattern and Y-direction pattern addressing from an X-direction pattern table and a Y-direction pattern table. The X-direction pattern and the Y-direction pattern read out according to the internal address of the chixtenia pattern and the closed figure are synthesized, and 2
To provide a chixtenia pattern generating device having a configuration configured to generate a dimensional chixtenia pattern and capable of filling the inside of a closed figure with a chixtenia pattern at high speed.

[Real examples of inventions]

Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

FIG. 6 shows a chixtenia pattern generator according to an embodiment of the present invention. This is a block diagram showing the p# configuration, in which the same parts as in FIG. 3 are indicated using the same reference numerals, and detailed explanation thereof will be omitted. 7 and 8 are an X-direction pattern table and a Y-direction pattern table, and 11 is an OR circuit. What is shown in FIG. 6 is K, an X-direction pattern table 7, and a Y pattern table instead of the pattern table 6 of the conventional method
A direction pattern table 8 is used. The operation is the same as in the conventional method (2) shown in FIG. 3, except for the mode in which the circular portion of the closed figure is filled with a chixtenia pattern. Now paint the inside of the closed shape with a chixtenia pattern 9
In the crush mode, the graphics processing CPU 2 first searches the It is applied to the direction pattern table 7 and the Y direction pattern table 8. Next, the internal address of the closed figure calculated by the graphics processing CPU 2 is given to the display memory 3, the X address (or a part thereof) of that address is given to the X direction pattern table 7, and the Y address (or a part thereof) is given to the Y-direction pattern table 8. In each of the X-direction and Y-direction pattern tables 7 and 8, each X-direction and Y-direction pattern instructed in advance by the graphic processing CPU 2 is read out according to the given address, and
R circuit] 1 performs an OR operation for each bit.

At this time, the data selector 4 is switched to the OR circuit 11M, and a chixtenia pattern is written in the display memory 3 at the given address.

FIG. 7 is a diagram showing the configuration of the X-direction pattern table and Y-direction pattern table of FIG. 6.

What is shown in Figure m7 is a pattern table for generating horizontal, vertical, and cross-hunting chixtenia patterns with hunting intervals of 1 to 3 to completely fill the area. The pattern address in the figure is determined by the graph ink processing CPU 2 shown in FIG.
These are the addresses of the patterns in each X direction and Y direction given in advance to the direction pattern table 8.

Figures 8 (tal to d) are diagrams showing all aspects of generating various patterns using the pattern table of Figure 7, respectively. Figure 8 (a) shows a completely filled pattern; The direction pattern and the Y direction pattern are all "1" patterns.

The X direction pattern and Y direction pattern are ORed bit by bit.
is taken, so if either the X-direction pattern or the Y-direction pattern is a pattern of all "1"s, a completely filled pattern can be generated. Figure 8(b) is
It shows a horizontal threading pattern with threading interval = 1, the X-direction patterns are all rOJ patterns, and the Y-direction pattern is l'-0101 with Is threading interval = 1.
...This is a pattern that becomes OIJ. By ORing these patterns, the Y direction pattern becomes “
The part of the X address corresponding to "0" is all "0" regardless of the part of the X address, and the part of the X address corresponding to the Y direction pattern of "1" is unrelated to the part of the X address. are all "1", and therefore a horizontal tucking pattern can be formed.

FIG. 8(C) shows a vertical notching pattern with a hunting interval of 2, and the X direction pattern is [00110011...0011 J with a notching interval of 2.
This is the pattern. As in the case of the horizontal hunting pattern, a vertical hunting pattern can be constructed by ORing all of these patterns. Fig. 8(d) shows a cross hunting pattern with hunting interval = (3, 2), and the X direction pattern is [000111000111...] with hunting interval = 3.
・The pattern is 0OOIIIJ, and the X direction pattern is [00110011・
...This is a pattern of 0011J. By taking 0Rvi- of these patterns, "1" is written to the address corresponding to "1" of each pattern, and "0" is folded only to the address where both patterns are "()". By doing so, a cross stitching pattern can be constructed. Figures 7 and 8 (a) to ft.
j) As is clear from the completely filled pattern, ・1
X-direction pattern table and Y-direction pattern table for generating all horizontal, vertical, and cross-hunting patterns (vertical and cross-hatching may have different hatching intervals in the X and Y directions) up to n. The sum S3 of the size of the pattern table is S s 22 (nl, c+2) (L, C1M (
2, 4, -. 11- The pattern table can be configured to be small, and the larger n is, the greater the effect becomes.

FIG. 9 is a block diagram showing the configuration of a chixtenia pattern generator according to another embodiment of the present invention. In the figure, 9 is a vector generator and 10 is an address selector. The embodiment shown in FIG. 9 has a configuration in which a vector generator 9 and an address selector 10 are added to the embodiment shown in FIG. 6 in order to draw the four straight lines seen at high speed. In the chixtenia pattern generating device shown in FIG. X2, Xa X4, Xa ．． The X and X addresses (or part thereof) are given to the X and Y direction pattern tables 7 and 8, respectively.

12- At this time, the address selector 10 has been switched to the vector generator 9 side. Each of the X-direction and Y-direction pattern tables 7 and 8 is composed of a memory that can be read out at high speed, and a pattern specified in real time is read out from an address given at high speed. Then, an OR operation is performed for each bit, and a chixtenia pattern is provided to the display memory 3. Note that when the vector generator 9 is used in a mode other than the mode in which 1 full of closed figures is filled, the address selector 10 is switched to the vector generator 9 side, and the data selector 4 is switched to the graphics processing CPU 2 side.

In addition, in the above embodiment, the chixtenia pattern is
Although the explanation has been given with reference to the cutting pattern as shown in Figure 1, the contents of the pattern table, the OR function of each X direction and Y direction pattern, EX-OR operation, etc. etc., Figure 1O (
Various chixtenia patterns as shown in a) to e) can be generated. Furthermore, in the above example, shark,
As explained above, straight line patterns such as solid lines, oval lines, and broken lines can also be generated by the same procedure as the chixtenia pattern for filling the inside of a closed figure with gold.

〔Effect of the invention〕

As explained above, Jin's invention is based on a specified chixtenia pattern and an internal address of a closed figure from an X-direction pattern table and a Y-direction pattern table that store one-dimensional X-direction patterns and Y-direction patterns. The readout X-direction pattern and Y-direction pattern are combined to generate all two-dimensional chixtenia patterns, so chixtenia patterns such as hunting patterns can be generated extremely easily using a small pattern table. It is also possible to fill the inside of a closed shape with a chixtenia pattern at high speed using software such as a vector generator or a circuit that fills the inside of the closed shape. It has excellent effects such as:

[Brief explanation of the drawing]

FIGS. 1(a) to 1(c) respectively show an example of the structure of a conventional chixtenia pattern, and FIG. 2(a) shows an example of a closed figure filled with a conventional chixtenia pattern. , FIG. 3 is a block diagram showing the configuration of the conventional method ■, which is an example of the conventional textico and avatar generation method,
Fourth rudder? l (a) and (b), Figure 5 is the third
Figure 6 is a block diagram showing a textured pattern generator according to an embodiment of the present invention, and Figure 7 is the X-direction pattern table shown in Figure 6. FIG. 8 (al to d), which shows the entire configuration of the Y-direction pattern table, is a mode in which the pattern table in FIG. 7 is combined to generate various patterns. FIG. 9 is a block diagram showing the configuration of a chixtenia pattern generator according to another embodiment of the present invention, and FIG. FIG. 3 is a diagram showing an example of the structure of various chixtenia patterns that are generated. In the figure, 1...Host computer, 2...CPU for graphic processing, 3. Display memory, 4. Data selector, 5., CRT display, 6.. Pattern display.
- pull, 7, X direction pattern table, 8...Y direction pattern table, 9...vector generator,
1O19, address selector, 11...OR excitation path. In each figure, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Fig. 1 (a) (b) (C) Fig. 2 ■ Fig. 3 Fig. 4 (a) (b) (Lx, Ly) = (1, 1) (Lx, Ly) Engineering ( 2, 2) Fig. 8 Y7fr5'Iha"7-n Fig. 8 Y77r1/Y5-, / Fig. 10 V Kuhn Fig. 10 Procedural Amendment C Irobo) Showa 5 Reed 1 car 17th 1, Indication of the case: Japanese Patent Application No. 59-25773 No. 3, Part 5 to Hitoshi Katayama, representative of the person making the amendment, ``Detailed explanation of the invention'' and ``Brief explanation of the drawings'' of the specification to be amended.
columns and drawings. 6. Contents of amendment (1) "Computer graphics" in the third line of page 2 of the specification is corrected to "computer graphics." (2) I-L, CMJ on page 7, line 4 of the same book, [L,
Correct as C0M, J. (3) In the same book, page 7, line 6, [L, C, Ml is changed to “L,
Correct as C, M, and J. (4) "3·nmax-8" on page 7, line 13 of the same book is corrected to r 3 '"max" Si J. (5) "Completely fill in" in the same book, page 10, lines 6-7, is corrected to "completely fill in and". (6) Delete "conventional" in the first and second lines of page 16 of the same book. (7) Figure 8 (C) of the attached drawings is corrected as shown in the attached sheet.

Claims (1)

[Claims] An X-direction pattern table and a Y-direction pattern table that store one-dimensional X-direction patterns and Y-direction patterns that are constituent elements of a two-dimensional texture pattern when filling the inside of a closed figure with a specified texture pattern; , an arithmetic circuit for generating a two-dimensional texture pattern by synthesizing the specified texture pattern and the X-direction pattern and Y-direction pattern read out according to the internal address of the closed figure. A texture pattern generator characterized by comprising: