JPS62189551A - セルアレイプロセツサの２ワイア／３ポ−トｒａｍ - Google Patents

セルアレイプロセツサの２ワイア／３ポ−トｒａｍ

Info

Publication number
JPS62189551A
JPS62189551A JP61295071A JP29507186A JPS62189551A JP S62189551 A JPS62189551 A JP S62189551A JP 61295071 A JP61295071 A JP 61295071A JP 29507186 A JP29507186 A JP 29507186A JP S62189551 A JPS62189551 A JP S62189551A
Authority
JP
Japan
Prior art keywords
cell array
array processor
information storage
signal lines
storage means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61295071A
Other languages
English (en)
Inventor
ステイーブン・グレゴリー・モートン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Corp filed Critical Deutsche ITT Industries GmbH
Publication of JPS62189551A publication Critical patent/JPS62189551A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［産業上の利用分界］ 本発明は、アレイプロセッサに関し、特に単一命令多重
データ（ＳＩＭＤ）アーキテクチャの高度に並列で、非
常に規則的構成を有するセルアレイプロセッサに関する
。
［従来技術］

Claims (8)

    【特許請求の範囲】
  1. （１）複数のプロセッサセルを有するセルアレイプロセ
    ッサにおいて、 各プロセッサセルに関連し、２つの信号ラインを介して
    前記関連したプロセッサセルと通信する情報記憶手段を
    備え、この情報記憶手段が、前記２つの信号ラインのそ
    れぞれを介して読み出し可能であり、前記２つの信号ラ
    インの両方を介して書込み可能であるセルアレイプロセ
    ッサ。
  2. （２）前記各情報記憶手段に関連し、前記２つの信号ラ
    インの１つを介して前記情報記憶手段と通信する読み出
    しアドレスデコーダと、 前記各情報記憶手段に関連し、前記２つの信号ラインの
    他方を介して前記情報記憶手段と通信する読み出し／書
    込みアドレスデコーダとを備えている特許請求の範囲第
    １項記載のセルアレイプロセッサ。
  3. （３）前記各情報記憶手段と関連し、クロック信号の第
    １の部分の間に前記情報記憶手段の２つの独立した読み
    出しアドレスでデータを読み取る手段と、 前記各情報手段と関連し、前記クロック信号の第２の部
    分の間に前記情報記憶手段の単一の信号書き込みアドレ
    スにデータを書込む手段とを備えている特許請求の範囲
    第２項記載のセルアレイプロセッサ。
  4. （４）前記２つの独立したデータ読み出し手段が第１お
    よび第２のラッチを備え、前記各ラッチが前記２つの信
    号ラインの１つと通信する特許請求の範囲第３項記載の
    セルアレイプロセッサ。
  5. （５）前記データ書込み手段が前記２つの信号ラインの
    一方に接続された反転バッファと前記２つの信号ライン
    の他方に接続された非反転バッファとを備えている特許
    請求の範囲第４項記載のセルアレイプロセッサ。
  6. （６）前記各ラッチが前記ラッチを使用可能にする手段
    を備えている特許請求の範囲第４項記載のセルアレイプ
    ロセッサ。
  7. （７）前記各情報記憶手段が複数の専用レジスタと複数
    の汎用レジスタを備え、全ての前記レジスタが前記２つ
    の信号ラインと通信する特許請求の範囲第１項記載のセ
    ルアレイプロセッサ。
  8. （８）前記専用レジスタと前記汎用レジスタがアドレス
    ラインを共用する特許請求の範囲第７項記載のセルアレ
    イプロセッサ。
JP61295071A 1985-12-12 1986-12-12 セルアレイプロセツサの２ワイア／３ポ−トｒａｍ Pending JPS62189551A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/808,393 US4783732A (en) 1985-12-12 1985-12-12 Two-wire/three-port RAM for cellular array processor
US808393 1991-12-16

Publications (1)

Publication Number Publication Date
JPS62189551A true JPS62189551A (ja) 1987-08-19

Family

ID=25198636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61295071A Pending JPS62189551A (ja) 1985-12-12 1986-12-12 セルアレイプロセツサの２ワイア／３ポ−トｒａｍ

Country Status (3)

Country Link
US (1) US4783732A (ja)
EP (1) EP0234147A3 (ja)
JP (1) JPS62189551A (ja)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985832A (en) * 1986-09-18 1991-01-15 Digital Equipment Corporation SIMD array processing system with routing networks having plurality of switching stages to transfer messages among processors
US5230079A (en) * 1986-09-18 1993-07-20 Digital Equipment Corporation Massively parallel array processing system with processors selectively accessing memory module locations using address in microword or in address register
US5170484A (en) * 1986-09-18 1992-12-08 Digital Equipment Corporation Massively parallel array processing system
US6108763A (en) * 1986-09-18 2000-08-22 Grondalski; Robert S. Simultaneous parity generating/reading circuit for massively parallel processing systems
US5146606A (en) * 1986-09-18 1992-09-08 Digital Equipment Corporation Systems for interconnecting and configuring plurality of memory elements by control of mode signals
US4980817A (en) * 1987-08-31 1990-12-25 Digital Equipment Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
GB8820237D0 (en) * 1988-08-25 1988-09-28 Amt Holdings Processor array systems
WO1990015385A1 (en) * 1989-06-02 1990-12-13 Atari Corporation System and method for cyclical, offset multiport register operation
DE4002348A1 (de) * 1990-01-30 1991-08-01 Productech Gmbh Verfahren zur herstellung von loetverbindungen
DE69132495T2 (de) * 1990-03-16 2001-06-13 Texas Instruments Inc., Dallas Verteilter Verarbeitungsspeicher
WO1994007200A1 (en) * 1992-09-21 1994-03-31 Unisys Corporation Multiported buffer memory system for disk drive complex
US5546569A (en) * 1993-02-19 1996-08-13 Intergraph Corporation Apparatus for writing data to and reading data from a multi-port RAM in a single clock cycle
US5485572A (en) * 1994-04-26 1996-01-16 Unisys Corporation Response stack state validation check
JPH0954761A (ja) * 1995-08-15 1997-02-25 Sony Corp デイジタル信号処理装置及び情報処理システム
US5898828A (en) * 1995-12-29 1999-04-27 Emc Corporation Reduction of power used by transceivers in a data transmission loop
US6262937B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Synchronous random access memory having a read/write address bus and process for writing to and reading from the same
US6262936B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Random access memory having independent read port and write port and process for writing to and reading from the same
US6069839A (en) 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
EP1238473B1 (en) 1999-12-08 2004-04-28 ED & D, Inc. System and method for transmitting and receiving power and data using time division multiplex transmission
US6744681B2 (en) * 2001-07-24 2004-06-01 Hewlett-Packard Development Company, L.P. Fault-tolerant solid state memory
US7444559B2 (en) * 2004-01-28 2008-10-28 Micron Technology, Inc. Generation of memory test patterns for DLL calibration
US7694202B2 (en) * 2004-01-28 2010-04-06 Micron Technology, Inc. Providing memory test patterns for DLL calibration

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3364472A (en) * 1964-03-06 1968-01-16 Westinghouse Electric Corp Computation unit
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
US3968480A (en) * 1974-04-25 1976-07-06 Honeywell Inc. Memory cell
US3906458A (en) * 1974-08-28 1975-09-16 Burroughs Corp Odd-sized memory having a plurality of even-sized storage elements of the same capacity
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4092728A (en) * 1976-11-29 1978-05-30 Rca Corporation Parallel access memory system
US4287563A (en) * 1979-11-13 1981-09-01 Motorola, Inc. Versatile microprocessor bus interface
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
NZ207326A (en) * 1983-03-08 1988-03-30 Stc Plc Associative data processing array

Also Published As

Publication number Publication date
EP0234147A3 (en) 1989-06-07
EP0234147A2 (en) 1987-09-02
US4783732A (en) 1988-11-08

Similar Documents

Publication Publication Date Title
JPS62189551A (ja) セルアレイプロセツサの２ワイア／３ポ−トｒａｍ
DE3583573D1 (de) Digitale speicheranordnung mit doppeltem zugriff.
KR920010624A (ko) 반도체기억장치
IE872505L (en) Executing the instruction sequences in an order determined¹in advance
JPS55108027A (en) Processor system
EP0256134A4 (en) CENTRAL COMPUTER.
JPS60128543A (ja) アドレス交換仮想記憶装置
SU680052A1 (ru) Запоминающее устройство
JPS585133U (ja) デ−タ伝送システム
SU1735864A1 (ru) Устройство обработки информации
SU932567A1 (ru) Запоминающее устройство
JPS59130146U (ja) メモリ装置
SU1179351A1 (ru) Устройство дл сопр жени электронно-вычислительной машины с периферийными устройствами
JPS58118599U (ja) 記憶装置
JPS6436363A (en) System for making access to dual port memory
SU1619282A1 (ru) Запоминающее устройство
JPS6431253A (en) Data transferring system
JPS59134842U (ja) 車載電子機器用のワンチツプマイコンのメモリ拡張装置
JPS617175U (ja) 画像表示装置
JPS6136854A (ja) メモリ切換装置
JPS58163095U (ja) 欠陥処理回路
JPH0455658U (ja)
JPS6174055A (ja) プロセツサ間のデ−タ通信装置
JPS6289052U (ja)
JPS62129659U (ja)