JPS62188520A - Weighting arithmetic type analog-digital converter - Google Patents

Abstract

PURPOSE:To attain the A/D conversion with high accuracy at a high speed by repeating the operation until the absolute value of a difference voltage becomes smaller than the reference voltage corresponding to the weighting of the least significant bit. CONSTITUTION:A tentative digital quantity stored in a memory 15 is read by a latch circuit 16, a D/A converter 3 generates an analog voltage Vdac, a differential amplifier 2 takes a difference between an input analog voltage Vin and the voltage Vdac and its difference voltage DELTAVin is outputted, which is compared simultaneously with plural reference voltages +Vr and -Vr at a voltage comparator circuit 4, a binary number for weighting corresponding to the absolute value of the difference voltage DELTAVin is set by an addition/ subtraction data set circuit 7, an OR circuit 12 ORes the numbers and the result is inputted to a full adder 13. The data is added or subtracted to/from the tentative digital quantity by the full adder 13 and a new digital quantity is stored in a memory 15. The correcting operation is repeated until the absolute value of the difference voltage DELTAVin becomes smaller than a reference voltage corresponding to the weighting of the least significant bit.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to a weighted calculation type A/D converter that allows highly accurate A/D conversion to be performed at high speed.

[Technical use of the invention and its problems] Conventional A/D that can perform high-precision A/D conversion
As the converter, for example, a successive approximation type A/D converter is known.

This A/D converter includes a voltage comparison circuit, a successive approximation register, a D/A converter forming a feedback circuit, and a clock oscillator for controlling the entire circuit.

Then, from the bottom of the successive approximation register (from the f7 bit side,
The converted voltage corresponding to each bit is output from the D/A converter, and the converted voltage is compared with the input analog voltage using a voltage comparison circuit. If these two voltages do not match, the voltage is set one bit at a time. This is repeated until a match is reached, and the digital signal corresponding to the input analog voltage is output.

However, in the above-mentioned successive approximation type A/D converter, since the analog voltage is converted to digital m by sequentially comparing the smallest bit units, it takes a relatively long time to convert to digital quantity. However, there was a problem in that it lacked high speed.

On the other hand, conventional A/D conversion that can perform high-speed A/D conversion
As the A/D converter, for example, a parallel comparison type A/DI converter is known.

This A/D converter assumes that the digital amount to be output is n bits, and divides a constant voltage into 2n equal parts (2"-1).
a resistance ladder circuit that generates reference voltages of (20-1
) are installed in parallel, and each reference terminal has a voltage comparator to which each M quasi-voltage generated in the resistor ladder circuit is set, and the output from this voltage comparator is converted into a binary code, and then converted into an n-bit digital code. and a decoder that outputs it as a quantity.

The incoming analog voltages are input in parallel to the input terminals of all the voltage comparators and compared at the same time with all reference voltages, and a digital amount corresponding to the input analog voltages is output from the decoder.

However, in the parallel comparison type A/DI converter described above, a large number of (2n-1) voltage comparators are required for n-pit digital data. For this reason, factors that deteriorate accuracy increase, such as variations due to the threshold voltage, input bias current, input off-bit voltage, and delay time of each voltage comparator, and the relative accuracy of the resistor ladder circuit, making it difficult to convert high-precision A/D converters. The problem was that it was difficult to implement.

[Object of the Invention] The present invention was made based on the above circumstances, and an object of the present invention is to provide a weighted calculation type A/D converter that can perform high-precision A/D conversion at high speed.

[Summary of the Invention] In order to achieve the above object, the present invention sets a plurality of positive and negative reference voltages of voltage values related to weighting of each bit in a voltage comparison circuit, and stores the reference voltages in a memory. A D/A converter generates an analog voltage proportional to the provisional digital quantity, and a voltage comparison circuit simultaneously compares the difference voltage between the input analog voltage and the analog voltage with the plurality of reference voltages. Based on the output from the circuit,
A full adder adds or subtracts a weighted binary number corresponding to the absolute value of the differential voltage depending on whether the differential voltage is positive or negative to the digital amount read from the memory, and adds or subtracts the weighted binary number corresponding to the absolute value of the differential voltage to the digital amount read from the memory, and adds or subtracts the weighted binary number corresponding to the absolute value of the differential voltage, and adds or subtracts the weighted binary number corresponding to the absolute value of the differential voltage. Store digital quantities in memory,
High-precision A/D conversion is performed at high speed by repeating the above operation until the absolute value of the differential voltage becomes smaller than the reference voltage corresponding to the weighting of the least significant bit.1゜"Embodiments of the Invention" First, the principle of the weighted calculation type A/D converter according to the present invention will be explained using FIG.

Reference numeral 1 in FIG. 1 is an input terminal for input analog voltage Vin;
2 is a differential amplifier, and differential amplifier 2 has an input analog voltage V
The differential voltage ΔVin between the input voltage in and the analog voltage Vdac generated from the D/A converter 3 forming the feedback circuit is output.

4 is a voltage comparator circuit, which outputs a digital amount B(4)
When is n bits, 2n voltage comparators 5.6 are arranged, and the reference voltage +v of the voltage value corresponding to the weighting of each bit in digital ff1B(4)
A plurality of positive and negative r, -vr are prepared, and these bases t
l! Voltages +Vr and -Vr are set in the corresponding voltage comparators 5.6, respectively.

7 is an addition/subtraction data setting circuit, and the addition data setting section 7
a, a reduced-choice data set section 7b, and an OR circuit 12 that takes the logical sum of the outputs of both of these data set sections 7a and 7b.

The output terminal of the 017 circuit 12 is connected to the full adder 13,
The output terminal of the additional tV unit 13 is connected via a buffer 14 to a memory 15 for digital storage. The memory 15 also stores data B read out from the memory 15.
(3) connected to a latch circuit 16 for latching the
The output terminal of the latch circuit 16 is the D/A converter 3
It is connected to the.

The data latched in the latch circuit 16 becomes A/D converted digital fliB(4), so the latch circuit 1
Output terminal 1 of digital ff1B (4) to the output terminal of 6
7 is connected.

Then, the temporary digital value initially stored in the memory 15 is read out to the latch circuit 16, and the D/A converter 3 converts the analog voltage V proportional to this temporary digital amount.
daC occurs. In the differential amplifier 2, the difference between the input analog voltage Vdac input from the input terminal 1 and the analog voltage VdaC generated in the D/A converter 3 is calculated, and the difference voltage ΔVin ΔV in = V in - Vdac - (
D is output. The value of this differential voltage Δvin is proportional to the conversion error.

The voltage difference Δvin is simultaneously compared with a plurality of reference voltages +vr and -vr in the voltage comparison circuit 4. As a result, if the sign of the difference voltage ΔV1n is positive and its value is larger than the reference voltage +yr, C+→ is output from the voltage comparator 5, and the addition data set section 7 in the addition/subtraction data setting circuit 7
At a, a weighted binary number for addition (addition data) corresponding to the absolute value of the differential voltage ΔVin is added.

On the other hand, when the sign of the differential voltage ΔVin is negative and its value is smaller than the reference voltage of -vr, the voltage comparison 16 to 01
is output, and in the subtraction data set section 7b of the addition/subtraction data set circuit 7, a weighted binary number for subtraction (subtraction data) corresponding to the absolute value of the differential voltage ΔVin is output.
is set.

The above addition data and subtraction data are logically summed by the OR circuit 12, and the addition and subtraction data B(1) is input to the full adder 13. Since the provisional digital quantity is input from the latch circuit 16 to the other input terminal of the full adder 13, the above addition and subtraction data B(1) is added to and subtracted from this provisional constant digital quantity m, and this operation is performed. The resulting new digital IIB(2) is transferred to memory 1 via buffer 14.
5 is stored.

Thus, the data stored in the memory 15 is a digital value f corrected based on the differential voltage ΔVin from the provisional digital quantity.
Captured by llB(3).

The above correction operation by addition, subtraction, etc. of the full adder 13 is performed until the starting value of the differential voltage ΔVin becomes smaller than the reference voltage corresponding to the weighting of the least significant bit, that is, −vr<Δy
This is repeated until rn<+yr.

In this way, the digital 1B(4) which has been A/Dlfr-converted with high precision is finally outputted from the output terminal 17.

Next, a first embodiment of the present invention will be described using FIGS. 2 to 10.

This embodiment uses 4-bit A/DV! Figure 2 shows the overall configuration, Figure 3 shows the main circuit diagram for explaining the operation of the D/A converter, and Figure 4 shows the sample and hold circuit, differential amplifier, and voltage comparison circuit. , and a circuit diagram of an analog circuit including a D/A converter, etc., Figure 5 is a circuit diagram of a voltage comparison circuit and an addition/subtraction data set circuit, and Figure 6 is a circuit diagram of an addition/subtraction circuit set in the circuit of Figure 5. Figure 7 is a logic diagram of the above-mentioned full adder, Figure 9 is a truth table of the above-mentioned full adder, and Figure 10 is the first embodiment. This is a timing chart for explaining the effect of

First, to explain the overall configuration using Fig. 2, the input terminal 1
A sample hold circuit 18 is provided between the differential amplifier 2 and the differential amplifier 2.
is connected. The sample and hold circuit 18 temporarily holds the input analog voltage Vin.
It is used to avoid color distortion to the output digital ff1B(4) due to variations in the input analog voltage Vin during conversion.

In the voltage comparison circuit 4, eight voltage comparators 5a to 5d and 6a to 6d, which correspond to twice the number of bits, are arranged in parallel.

In addition, a voltage of +16Vr is divided by a voltage divider circuit in which five resistors with resistance values of R, R, 2R, 4R, and 8R are connected in series, and the voltage value corresponding to the weighting of each bit is divided. Reference voltage vr, 2Vr, 4Vr, 8V
r is generated, which is applied to each voltage comparator 5a, 5b, 5C1.
5d, respectively. On the other hand, the same 5
-16V by another voltage divider circuit with resistors connected in series.
A negative reference voltage −Vr whose absolute value corresponds to the weighted G of each pit by dividing the voltage of the value r,
-2Vr, -4Vr, and -8Vr are generated and set to each voltage comparator 6a, 6b, 6c, and 6d, respectively.

The addition data set section 7a in the addition/subtraction data set circuit 7 has three AND circuits 8a, 8b, and 8C arranged in parallel, and one of the two AND circuits 8a has a voltage comparator 5a.
is directly connected to the other voltage comparator 5b via an inverter 9a.

Regarding the other two AND circuits 8b and 18C, similarly to the above, the voltage comparator 5b is directly connected to the AND circuit 8b, and the voltage comparator 5C is connected via the inverter 9b. There is.

A voltage comparator 5C is directly connected to the AND circuit 8C, and another voltage comparator 5d is connected via an inverter 9C.

Regarding the subtraction data set section 7b, three AND circuits 10a to 10 are connected in substantially the same manner as above.
C1 and inverters 118 to 11C are arranged in parallel.

The full adder 13 is a well-known one, as will be described later. 〜B4.) and the data after the operation B(2)=Bzt+〜8
21 is output to the buffer 14.

Buff? 14 is driven by the clock pulse CK input from the terminal 19b, and exhibits high impedance when the low clock pulse GK is at the H level, and becomes active when the low clock pulse GK is at the low level, and the full adder 13
Data after calculation from B(2)-B2. 821 is transmitted to the memory 15.

Table 1 shows a series of operation timings of the buffer 14, memory 15, and latch circuit 16 driven by the clock pulse CK.

As shown in the table above, when the Otsuk pulse CK is at H level,
The data as a whole is read from the memory 15, and the data is incorporated into the memory 15 at the L level.

Next, the configuration and functions of each part will be explained in more detail with reference to FIGS. 3 to 9.

First, the 4-bit D/A converter 3 will be explained with reference to FIG.

The main part of the D/A converter 3 has a resistance value of 2R.
and an operational amplifier 21 and <1615).
and an inverting amplifier formed by a resistor with a resistance value of R.

As shown in FIG. 3, voltages of V1, V2, ■43, and ■44 are applied to one end of each resistor with a resistance value of 2R, respectively.
Assuming that voltages Va, v2 and vl appear at the connection of resistance value R, respectively, according to Kirchhoff's law, (V43-Vl)/2R-V1/R + (V2 Vl)/R=0 (V+2-V2 )/2R+ (Vl-V2)/R+
(Va-V2)/R=0 (V41-Va)/2R+ (V2-Va)/R-
V 3 / 2 R = 0 ... (2) From the above formula (2), V43 5V1 + 2V2 = O ... (3) V
42 + 2V1 5V2 +2V3 =O...(4
)V4+ +2V2-4V3=O...1S)
Perform equation (4) + equation (5) x (1/2) to obtain V42+
(1/2) V4++2V1-4V2 =0 Furthermore, multiply this formula by 2 to get 2V42+V41+4V1-8V2 =O-(6)(3
) Do the formula x 4 and get 4 V43-20 V 1+ 8 V 2±0
...(7) From formula (6) + formula (7), V44 + 2 V42 + 4 V Lee-16V1-0
...(8) 1tff flowing through the feedback resistor in the inverting amplifier! 1 = V 44/2 R+ V 1/ R-(91
Substituting the value of vl obtained from the above equation (8) into equation (9), 1= (1/16R) ・(V4+ + 2 V42+ 4 V4.3+ 8
VZ44) ... (The analog output voltage in the circuit shown in IO Table 3 is -Vout= (1615)R1
= (115) (v hour 1 + 2 v salary 2 + 4 V43 + 8 V 44) ... (11
1 Here, (■ in formula 1, each voltage of +1 to V44 corresponds to the digital IB(4) = 844 to B41 output from the latch circuit 16 as shown in Table 2, so
If the H level voltage of this digital signal 8(4)=Ba4 to B41 is, for example, VCC-5V, then the analog output voltage -VOut can be changed as shown in the following equation.

-Vout=<115) (Bcb+X5V+8pm 2X
2X5V+B43X4X5V+B44X8×5■) = 841 + 2 8*z+ 4 8 43
・Volt...(In the circuit shown in Figure 3, the analog output voltage is a negative value as shown in the cutout above, so the D/A converter 3 in Figure 2 , as shown in FIG. Output.

Vd'ac=k (Be, 1.+2B42+4BI+3
+8B44)...(11 As explained in the above formula (0), it can be set to =1 by setting the circuit constants and the VCC value, so the following explanation will be made assuming =1.At this time, digital ff1B
(4) For the six values of =847+ to 84-1, the following values of analog voltage Vdac are obtained.

Next, referring to FIG. 4, an analog circuit portion including the non-pull hold circuit 18, the differential amplifier 11is2, the voltage comparator circuit 4, and the D/A converter 3 described in FIG. 3 above will be explained.

The sample hole path 18 includes two operational amplifiers 23.
24, a switch 25 and a capacitor 26 connected to the two operational amplifiers 23 and 24. The switch 25 is driven by (1/4) GK, which is obtained by dividing the clock GK by four, and the input analog voltage Vin is held in the capacitor 26.

As the differential amplifier 2, a normal one composed of an operational amplifier 2a is used.

Although not shown in FIG. 2, the voltage comparator circuit 4 has transistors 27a, 27b, . diodes D1, D2 and three resistors R
+s Analog logic interface circuits composed of R2 and R3 are connected to each other.

The analog circuit part operates with a power supply voltage of, for example, ±15V, whereas the logic circuit part after the addition/subtraction data set circuit 7 operates with a power supply voltage of, for example, +5V, and the operating voltage ranges of both circuit parts are usually different. There is. Therefore, an interface circuit is used to supply a signal of normal logic amplitude from the analog circuit section to the logic circuit section.

To explain the operation of the interface circuit, now ΔVi
When n<+vr and the output of the voltage comparator 5a is 1-level, the transistor 27a turns on, and the voltage 1 at the input terminal 28a becomes V+ -Vee+Vce5at -15 (V)...
(2) becomes. Vee is the emitter voltage of the transistor 27a,
vcesat is the saturation voltage, and if vcesat can be ignored, the voltage v1 will be equal to Vee. on the other hand,
Assuming that the voltage at the output terminal 28b is 2, and the voltage at the connection point of both diodes D1 and 02 is v3, both voltages V1 and v3 are V2 = V3 - Vf2, V3 = Vf+ - (
It becomes B. Vf+ and Vr2 are the forward voltage drops of the respective diodes D+ and C2.

As described above, when the transistor 27a is in the on state, a forward current flows through the diodes D1 and C2, and Vfl and V
Since r2 is almost equal, the voltage V2 at the output terminal 28b is
v2=o(v).

That is, when ΔV i n <+vr, the negative voltage V1 is turned off, and the voltage comparator circuit 4 normally outputs the ``'0'' signal.

On the other hand, when Δvin>+Vr, the output of the voltage comparator 5a becomes L level, and the transistor 27a is turned off. As a result, only one current flows through the resistors R2 and R3, and the voltage (2) at the output terminal 28b becomes 5 (2), so that the 11111 signal is normally output.

In this way, 0 to 5V is output from the interface circuit.
A logical output that swings normally between .

Next, based on the outputs C1 to C4 and C1- to C4- of the voltage comparator circuit 4, the addition/subtraction data B(1) = 814 to
The logical process by which B11 is output will be explained.

First, the sign of the differential voltage Δ■in is positive, and each time its value exceeds each reference voltage vr to 8vr set in the voltage comparator circuit 4, added data A1 to A4 are output and each bit is divided as follows. Addition/subtraction data B(1) corresponding to is set.

That is, when the differential voltage ΔVin exceeds the reference voltage vr, Vr<ΔV
When in<2Vr, the lower bit Bn of the addition/subtraction data B(1) becomes "1".

Similarly, when the differential voltage Δ■in exceeds 2Vr, 812 becomes '1', and when it exceeds 4Vr, 813 becomes 111 I+, 3
When it exceeds vr, the most significant bit B14 is set to “°1pa”.

Note that the addition data A1 to A4 are the voltage comparators 5a to 5.
The outputs C1 to C4 of d have the following relationship.

A1==C1・C2 A 2 = 02・C3 Δ3−03・C4 A a ” Ca On the other hand, if the sign of the differential voltage ΔVin is negative and the voltage is lower than each reference voltage = −Vr to −8Vr, subtraction is performed. data 8
1 to S4 are output, and addition/subtraction data B(1) corresponding to each bit is set as follows.

That is, when the differential voltage ΔVin becomes lower than -vr, it is only necessary to subtract (0001) from the digital @8(4) in the full adder 13, so the addition/subtraction n data B(1) becomes (111
1) is set. The setting value of this (1111) is (00
It corresponds to the least significant bit of (1110) with each bit of (01) inverted and 1 added.

Similarly, when the differential voltage Δvin falls below -2Vr, it is sufficient to subtract (0010), so the addition/subtraction data 8(1) of (1110) is set, and when it falls below -4Vr, (1100) is set. When it becomes lower than -8Vr, (1000) is set.

Note that the subtraction data 81 to S4 are obtained by each voltage comparator 6a to 6d.
The outputs C1- to C4- have the following relationship.

Sl=C1-・C2-82-01-・Cs-33=C1-・Ca-8a=C1- Since a known 4-bit full adder 13 is used, its logic diagram is shown in FIG. , FIG. 8 is a block diagram, and FIG. 9 is a truth table between humans and outputs, and detailed explanations of their internal configurations and the like will be omitted. In addition, in FIGS. 7 to 9, input signals A1 to A4 are digital signals B(4)=84t to B4.
4, and the other input signals 81 to B4 correspond to addition/subtraction data B(1)=B II to B +4.

Next, using the timing diagram in Figure 10, adjust A in Figure 2.
The physical operation of the /D converter will be explained.

Initially, the value of the input analog voltage ■in sampled and held in the sample and hold circuit 18 is 15V+゛α, and the value of the digital MB (4) −(
B44.84B, B 42, Bt+,)ha (0000)
Suppose that Analog voltage ■da generated from the D/A converter 3 in proportion to this digital ff1B(4)
Since C becomes OV, the differential voltage Vi from the differential amplifier 2 is
n=+15V+α is output.

The voltage difference ΔV i n=+15V+α is simultaneously compared with the reference voltages Vr to 8Vr in the voltage comparison circuit 4, and outputs (C4, C3, C2, CI
)=(1111) is output.

The addition/subtraction data set circuit 7 outputs the above outputs 04 to C1.
Based on addition/subtraction data B(1) = (B shrine, B 13,
B12, B11) are set to (1000).

The full adder 13 adds (
1000) and add/subtract data B(1) to obtain data B.
(2) Outputs (1000) as = (B, B23, B22, B21). This data B(2) is transferred to the buffer 14 at the timing when the clock pulse GK is at L level.
becomes active, so data B(3) = (B, pm,
B33.832, B51) are written into the memory 15.

Due to this pile of data B(3), the digital ff1B(4) stored in the memory 15 becomes (1000). Therefore, D/A is proportional to digital ff1B(4).
The analog voltage vdaC output from converter 3 is 8
Changes to V.

As a result, the differential voltage is Δvin=15+α-8-+7V+
α, and the output of the voltage comparison circuit 4 is (C4, C3, C2
, CI)=(0111), and based on this output, the addition/subtraction data B(1)-(0100) is set. Therefore, the full adder 13 performs the following binary operation.

B(4)=1000 oneto)13 1=C100B(2)
=1100 This data B(2) is transferred to data B(2) via the buffer 14.
3) and is written into the memory 15.

Then, at the next timing, D/A converters 3 to 8
(4) = An analog voltage Vdac=12V proportional to (11'OO) is generated, and the differential voltage is ΔV in=
15+α-12-+3V4 a.

As a result, the output of the voltage comparison circuit 4 is (C4, C3, C2
, C1)=(0011), addition/subtraction data B (1)=
(0010), the data for writing is B(2)=(111
0), and B(3)=(1110) is written into the memory 15.

In this way, the digital ff1B(4) initially stored in the memory 15 is corrected in sequence, and at the rising edge of the fifth clock pulse CK, the input analog voltage Vin=1
Digital ff1B(4)=(11
11) is output from the output terminal 17.

Assume that the input analog voltage V in =0V-α is sampled and held at the fifth clock pulse GK following the above conversion action.

At this time, the D/A converter 3 outputs a digital amount B (4
) = analog voltage proportional to (1111) Vdac = 1
Since 5V is generated, jff? The pressure of 1 is ΔV i
n=-15V-α. Due to this differential voltage ΔVin,
The output of the voltage comparison circuit 4 is (Ca-, C5-1C2-1C
1-)=(1111), addition/subtraction data is B(1)=
(1000).

Therefore, the next subtraction is performed in the addition sieve 13.

B(4)=1111 +>8(1)=1000 B(2>=0111 This is a mold that corresponds to a voltage drop of 15V-8V=7V.The above data B(2) is passed through the buffer 14. The data becomes data B (3) and is stored in the memory 15.
Device 13 ignores the carry.

At the next timing, D/A converters 3 to 8 (4)
= Analog voltage proportional to (0111) Vdac = 7V
occurs, and the differential voltage becomes ΔVin=−7V−α. Due to this difference voltage ΔVin, the output of the voltage comparator circuit 4 is (C
a −, Ca −, C2-1C1-) = (0111)
, addition/subtraction data is set to B(1)-(1100). Therefore, the next subtraction n is made at the current addition step 13.

13(4)=0111+)B(1)=1100B(2)=0011 This is an operation corresponding to a voltage drop of 7V-4V=3V. The above data B(2) becomes data B(3) via the buffer 14 and is written to the memory 15.

Then, at the next timing, D/A converters 3 to 8
(4) = analog voltage y proportional to (0011)
dac=3V is generated, and the differential voltage is ΔVin--3V-
becomes α.

As a result, the output of the voltage comparison circuit 14 is (C4-1C3
-, C2-1C1-) = (0011), addition and subtraction data B (1) - (1110), the write data of the subtraction result is B (2) = (0001), and B (3) = (
0001) is written into the memory 15.

As described above, the difference voltage ΔV is calculated according to the result of the correction calculation.
The absolute value of in becomes -15V, -7V, -3V, -1■, 0■, and its absolute value decreases in sequence, and at the rising edge of the 9th zero-off pulse GK, the sampled and held input analog voltage V
Digital filter B corresponding to i n=0V-α (4)
-(0000) is output from the output terminal 17.

In this way, four clock pulses GK are required for 4-bit A/D conversion, making high-speed conversion possible.

This conversion time is determined by the input analog voltage v as shown in the following table.
If the change width of in is small, the lock pulse CK becomes necessary.
Since the number of is reduced, it is further shortened.

In addition, the 4-bit A/
When the D conversion is completed, the output of the voltage comparator circuit 4 becomes C4, C3, C2, C1-0000 C4-, C3-, C2-, C1--0000, all outputting 0'', so this is the end of the conversion. By detecting this as the C0NV signal, it is possible to know the end of A/D conversion at an early stage.

Next, FIG. 11 shows a modification of the voltage comparison circuit and the addition/subtraction data set circuit in a 4-bit A/D converter.

In this modification, only two voltage comparators Z5a and 6a are arranged in parallel in the voltage comparator circuit 34, and these voltage comparators 5a,
l of +vr and -Vr in 6a! A quasi-voltage is set for each.

Furthermore, the addition/subtraction data set circuit 7 includes one OR circuit 2.
9 is provided, and the output terminals of voltage comparators 5a and 5a are connected to two terminals of this OR circuit 29, respectively.

Addition/subtraction data B(1)=(B14,B
13, [312, Least significant bit 131 in B word 1)
1 is output. Other pits 814, B 13, B 1
2 is output directly from the voltage comparator 6a.

When the differential voltage ΔVIn7J'M is larger than the quasi-voltage Vr, the output C+ of the voltage comparison circuit 34 becomes 1p, and the addition/subtraction data is set to B (1) = (0001). On the other hand, when the differential voltage Δvin is smaller than the reference voltage -Vr, the output C1- of the voltage comparison circuit 34 becomes "1'°, and the addition/subtraction data is set to B(1)=(1111)."

Table 4 shows the above relationship in a table.

Table 4 The above addition/subtraction data B(1) is added to the digital mB(4) read from the memory 15 in the full adder 13,
The digital ff1B(4) is sequentially corrected in minimum bit units, and the A/D converted digital ff1B(4) is output from the output terminal 17.

This modification has the advantage that the configurations of the voltage comparison circuit 34 and the addition/subtraction data set circuit 37 can be extremely simplified. However, after correcting the digital ff1B(4) read out from the main 15ht etc. in the minimum bit unit, the A/D
Since the conversion is performed, the conversion time is slightly longer than that of the circuit including the voltage comparison circuit 4 and the addition/subtraction frame datalet circuit 7 shown in FIG.

Next, FIG. 12 shows a modification of the memory section.

The memory 15 shown in FIG. 2 has a fixed address for storing digital quantities, but in this modification, the address III is fixed.
A III unit 31 is attached to enable address control.

When the digital ff1B(4) to be A/D converted has 4 bits, the A/D conversion of the digital ff1B(4) is completed in a maximum of 4 clock times, as shown in the timing chip 1 sheet of FIG. 10. Therefore, address controller 3
1 is driven by (1/4) GK obtained by dividing the clock CK by four, outputs address data, and controls the address of the memory 15.

As a result, the memory 15 stores A10 converted data B(3)
=(B, B33.8j2, B□) can be sequentially stored in separate addresses.

Next, FIGS. 13 and 14 show a second embodiment of the present invention.

This embodiment is an 8-bit A/D converter.

As shown in FIG. 13, the voltage comparator circuit 4 for 4 bits shown in FIG. 2 is used as is. Then, 8-bit addition/subtraction data B' (1)=(B11]%B+7KameBada1Bus is sent to the output terminal of the voltage comparator 6a set to the reference voltage -vr in the voltage comparison circuit 4.
, B14q B+3%B+2. The output lines of the upper 4 bits (81B, 817, Bee, Bee) in an) are connected and expanded to 8 bits in the addition/subtraction data set circuit 32.

In the case of 8 bits in this way, the required number of voltage comparators in the voltage comparison circuit can be reduced.

Although not shown in FIG. 13, J3 is shown in FIG.
Adder 13, buff? 14, memory 15, and latch circuit 16 are simply expanded to 8 bits. Therefore, each data and digital quantity is expressed as follows.

B' (2) = 82g ~ B21 B' (3) = B ~ Bit B' (4) = 8. ,~B- FIG. 14 shows the magnitude of the differential voltage Δ■in and the addition/subtraction data B'(1) set in the addition/subtraction data set circuit 32.
=B+e~B++ This shows which relationship.

Addition/subtraction data B' (1) shown in FIG. 14 = 8.8
~B u is added to or subtracted from the digital ff1B' (4) read from the memory 15 in the full adder 13, and the digital ff1B' (4) is corrected. At this time, addition and subtraction are performed on the upper 4 bits in units of 4 bits (00001000) of addition/subtraction n data B'(1).

[Effects of the Invention] As explained above, according to the present invention, the voltage comparator circuit calculates the base tP-voltage of the voltage value related to each pitch (. Set multiple numbers of 1) /A] to generate an analog voltage proportional to the digital m stored in the memory with the inverter, and calculate the difference voltage between the input analog voltage and the analog voltage generated by the O/A converter. , the plurality of reference voltages are simultaneously compared in a voltage comparison circuit, and based on the output from the voltage comparison circuit, a weighted binary number of t corresponding to the absolute value of the difference voltage is obtained from the memory by a full adder. Addition and subtraction are performed to the read digital signal, the new digital amount resulting from this calculation is stored in memory, and the above process is performed until the absolute value of the difference voltage becomes smaller than the reference voltage corresponding to the weighting of the least significant bit. Since the calculations are repeated, there is an advantage that highly accurate A/D conversion can be performed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a weighted WA calculation A/D converter according to the present invention, and FIGS. 2 to 10 show a first embodiment of the present invention. is a block diagram showing the overall configuration, Fig. 3 is a circuit diagram of the main part of the D/A converter, Fig. 4 is a circuit diagram of the analog circuit section in the front stage, and Fig. 5 is a circuit diagram of the voltage comparator circuit and addition/subtraction data set circuit section. Circuit diagram, Fig. 6 is a diagram showing the addition/subtraction data set in the addition/subtraction data set circuit as above, Fig. 7 is a logic diagram of the full adder,
Fig. 8 is a block diagram of the full adder as above, Fig. 9 is a truth table of the full adder as above, Fig. 10 is a timing chart for explaining the operation, Fig. 11 is a voltage comparison circuit and an addition/subtraction data set circuit. 12 is a block diagram showing a modification of the memory portion, FIG. 13 is a main circuit diagram showing a second embodiment of the present invention, and FIG. 14 is a circuit diagram showing a second embodiment of the same.
It is a figure which shows the relationship between the difference voltage and addition/subtraction data in an Example. 1: Input terminal for input analog voltage, 2: Differential amplifier, 3: D/A converter, 4: i! Voltage comparison circuits 5.5a to 5d16.6a to 6d: Voltage comparator, 7: Addition/subtraction data set circuit, 13: Full adder, 14: Buffer 7. 15: Memory, 16: Latch circuit, 17: Digital quantity output terminal, 18: Double hold circuit. Figure 3 Figure 5 Figure 6 Figure 7 Country (○ Figure 8

Claims (1)

[Claims] A memory that stores a digital quantity, a D/A converter that generates an analog voltage proportional to the digital quantity read from the memory, and an input analog voltage and an analog signal generated from the D/A converter. A differential amplifier outputs a voltage difference from the voltage, and a plurality of positive and negative reference voltages of voltage values related to the weighting of each bit in the digital quantity are set, and the plurality of reference voltages and the difference voltage are set. A voltage comparison circuit to be compared; and a weighted binary number corresponding to the absolute value of the difference voltage is added or subtracted from the digital quantity read from the memory based on the output of the voltage comparison circuit, and this addition or subtraction is performed. and a full adder for storing the new digital quantity in the memory, and the full adder adds the new digital quantity until the absolute value of the difference voltage becomes smaller than the reference voltage corresponding to the weighting of the least significant bit. Alternatively, a weighted operation type A/D converter is characterized in that it converts an input analog voltage into a digital quantity by repeating subtraction.